JPH0136710B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a bipolar semiconductor integrated circuit device (hereinafter referred to as "BIP").
IC”. This invention relates to an improvement in the method for forming an electrode extension portion of a transistor in the above-mentioned method.

[Prior art]

Generally, the transistor in BIP/IC is pn
They are formed in electrically independent islands by methods such as junction isolation, oxide film isolation using selective acid technology, or triple diffusion. Here, a method for forming an npn transistor using an oxide film separation method will be described. Of course, when using the above-mentioned various separation methods other than this, it is also applicable to pnp transistors.

FIGS. 1a to 1e are cross-sectional views showing the main process steps of a conventional manufacturing method. The conventional method will be briefly explained below with reference to this figure. After selectively forming an n-type (n ⁺ type) layer 2 with a high impurity concentration to serve as a collector buried layer on a p-type (p ^- type) silicon substrate 1 with a low impurity concentration, an n ^- type epitaxy layer is formed on the layer 2. 1. Grow the coating layer 3 [FIG. 1a]. next,
Selective oxidation is performed using the nitride film 201 formed on the underlying oxide film 101 as a mask to form a thick isolation oxide film 1.
02 is formed, but at this time, this isolation oxide film 10
At the same time, a p-type layer 4 for channel cutting is formed under 2 (FIG. 1b). Next, the nitride film 201 used as a mask for the selective oxidation described above is removed together with the underlying oxide film 101, an oxide film 103 for protecting ion implantation is formed again, and a photoresist film (the photoresist film at this stage is shown in FIG. (not shown) is used as a mask to form the p ⁺ type layer 5, which becomes the external base layer.
Further, the photoresist film 301 is removed, a new photoresist film 301 is formed, and using this as a mask, a p-type layer 6, which will become an active base layer, is formed by ion implantation (FIG. 1c). Subsequently, the photoresist film 301 is removed, a passivation film 401 generally made of phosphosilicate glass (PSG) is deposited, and a heat treatment is performed that combines the annealing of the base ion-implanted layers 5 and 6 and the baking of the PSG film 401. After forming the intermediate stage external base layer 51 and active base layer 61, the PSG film 401 is formed.
After forming the required openings 70 and 80 in the n ⁺ type layer 7 to become an emitter layer by ion implantation,
Then, an n ⁺ type layer 8 which is to become a collector electrode extraction layer is formed [FIG. 1d]. Thereafter, each ion-implanted layer is annealed to complete the external base layer 52 and active base layer 62, and the emitter layer 71 and collector electrode extraction layer 81 are formed. After that, an opening 50 for extracting the base electrode is formed, and each The openings 50, 70, and 80 are filled with metal silicide (platinum silicide) to prevent electrode penetration.
pt-Si, palladium silicide Pd-Si, etc.] film 501 is formed, and then a base electrode wiring 9, an emitter electrode wiring 10, and a collector electrode wiring 11 are formed of a low resistance metal such as aluminum Al.

FIG. 2 is a plan pattern diagram of a transistor manufactured by this conventional method. Incidentally, the frequency characteristics of a transistor depend on the base-collector capacitance, base resistance, etc., and it is necessary to reduce these to improve the frequency characteristics. In the above structure, the p ⁺ type external base layer 5 is used to reduce the base resistance.
However, this has the disadvantage of increasing the base-collector capacitance. The base resistance also depends on the distance _D1 between the emitter layer 71 and the base electrode opening 50, and in the conventional case, the distance between the base electrode wiring 9 and the emitter electrode wiring 10 and each opening 50 of each electrode wiring 9, 10 are determined. , 70. Even if the photoetching accuracy is improved and the electrode wiring spacing is reduced,
The above protrusion will inevitably remain.

[Summary of the invention]

This invention has been made in view of the above points, and it is possible to manufacture a transistor with low base resistance by having an emitter layer and a base electrode lead-out part close to each other in a self-aligned manner and having a double base structure. The present invention provides a method.

[Embodiments of the invention]

3a to 3f are cross-sectional views showing the main process steps of an embodiment of the method for manufacturing a semiconductor device according to the present invention. In the same figure, 601, 61
1,612 is a polysilicon film, 202, 203 is a nitride film, 104, 106 is an oxide film formed by oxidizing a polysilicon film, 105 is an oxide film formed by low-temperature oxidation of a substrate, 501, 511, 512 is a metal silicate film.

Next, the manufacturing process of the semiconductor device with the above configuration will be explained. First, as shown in Figure 3a,
After selectively forming the n ⁺ type layer 2, which will become the collector buried layer, on the p ^- type silicon substrate 1 in the same manner as before,
An n ^-type epitaxial layer 3 is grown thereon,
Furthermore, an isolation oxide film 102 is formed, a p-type layer 4 for channel cut is formed at the same time, and a base region 6 is formed.
was formed by ion implantation, and then a nitride film 202 was formed on the oxide film 103 used as a protective film at this time.
, and etched away the rest, leaving only this part so that the exposed part of the junction between the collector layer 3 and the base layer 6 to the substrate surface is protected, and then etching the nitride film 202, including the top of the nitride film 202. A polysilicon film 601 is deposited on the entire upper surface. Next, as shown in FIG. 3b, a nitride film 203 is deposited on the polysilicon film 601, and the nitride film 203 is deposited on the polysilicon film 601 so that the portion above the area where the emitter layer and the collector lead layer are to be formed remains. Using this nitride film 203 as a mask, the polysilicon film 60 is patterned.
1 is selectively oxidized, leaving a polysilicon film 611 on the emitter layer formation region and a polysilicon film 612 on the collector lead-out layer formation region, and converting the other portions of the polysilicon film 601 into an oxide film 104.
At this time, the polysilicon film 611 on the emitter layer formation region is formed so as not to overlap the protective nitride film 202, and the polysilicon film 612 on the collector lead layer formation region is formed so as to partially overlap the nitride film 202. Then, n-type ions are implanted into the polysilicon films 611 and 612 from above. Here, the ion implantation region is determined by the masking effect of the oxide film 104. Since the oxide film 104 is used as a mask during ion implantation, a thickness of about 3000 Å is sufficient, and when the polysilicon film 601 is thick,
It is more efficient to etch it a little to make it thinner and then selectively oxidize it. Next, as shown in FIG. 3c, from the polysilicon films 611, 612 to
After the emitter layer 7 and the collector lead layer 8 are formed by diffusing the type impurity, the oxide film 104 is completely removed. Next, as shown in FIG. 3D, the upper surface is subjected to low-temperature oxidation to form an oxide film 105 on the surface of the exposed base layer 6 and an oxide film 106 on the side surfaces of the polysilicon layers 611 and 612. As is well known at this time, in low-temperature oxidation, the oxide film 106 on polysilicon is formed thick, and the oxide film 105 on the silicon substrate is formed thin. Then, as shown in Figure 3e,
The polysilicon film 6 is etched by anisotropic etching such as reactive ion etching (RIE).
After removing the oxide film 105 on the surface of the base layer 6 while leaving the oxide film 106 on the sides of the base layer 6, the nitride film 203 is completely removed using hot phosphoric acid (at this time, the nitride film 202 is also removed). Although some parts are removed,
The collector-base junction is protected by an oxide film 103. ) The base layer 6 exposed in this way,
Metal silicide films 501, 511 and 512 are formed on the surfaces of polysilicon films 611 and 612, respectively. Subsequently, as shown in FIG. 3f, a passivation film 401 such as phosphosilicate glass is formed, and holes are formed at desired positions.
Base electrode wiring 9 and emitter electrode wiring 10 made of aluminum (not shown in FIG. 3f). ], and the collector electrode wiring 11 are formed. FIG. 4 is a plan pattern diagram of the transistor thus obtained.

In this way, the obtained transistor is
The emitter layer 7 is a polysilicon film 61 on which a metal silicide film 511 is superimposed on the emitter electrode wiring 10.
1, and the opening position in the passivation film 401 for the base electrode wiring 9 is different from the conventional example, and is formed near the polysilicon film 611. Furthermore, this base electrode wiring 9 is connected to the metal silicide film 501. It is connected and separated from the emitter region by an oxide film 106 in a self-aligned manner. Furthermore, the base metal silicide 501 surrounds the emitter region as shown in the figure, forming a so-called double base structure. In the conventional double base structure, the base electrode and the aperture area are large, resulting in an increase in capacitance, but this invention does not require any special electrode or aperture, and there is no increase in capacitance, and the base resistance can be reduced. Can be lowered.

FIG. 5 is a plan pattern diagram showing another example of a transistor formed by the method of the present invention, in which an oxide film 1
By passing under a portion of the polysilicon film 611 in the emitter region and leaving it on the boundary between the isolation oxide film 102 and the silicon island, a so-called wall emitter structure can be prevented.

This wall emitter structure is a structure in which the emitter-base junction is in contact with the isolation oxide film 102, as shown in FIG. 4. In this wall emitter structure, the collector-emitter pipe (C
-Epipe), but the 5th
The diagram structure avoids this.

It is of course possible to further reduce the emitter width by utilizing a side etching effect due to over etching in patterning the nitride film when forming a mask for selective oxidation as described above. Moreover, although the case of an npn transistor has been described above, it goes without saying that the same can be done for a pnp transistor as well. Furthermore, for isolation between elements, the various isolation methods described above can be applied.

〔Effect of the invention〕

As explained above, according to the method of manufacturing a semiconductor device according to the present invention, the emitter layer is connected to the emitter electrode wiring through the metal silicide film on the polysilicon film used for diffusion formation of the emitter layer. The metal silicide film extends and connects the base electrode wiring from the emitter layer to a position separated by the thickness of the oxide film formed by oxidizing the side surface of the polysilicon film above it, resulting in a self-aligned structure. And because it has a double base structure, the base resistance can be extremely small. Furthermore, since emitter diffusion is performed through the polysilicon film, it can be formed shallowly and accurately. Furthermore, since selective oxidation is used to leave this polysilicon film on the emitter layer formation region, the emitter width can be made narrower than in the past.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing the main stages of the conventional semiconductor device manufacturing method, FIG. 2 is a plan view of a transistor obtained by the conventional manufacturing method, and FIG. 3 is the invention according to the present invention. 4 is a plan view of an example of a transistor according to the method of this embodiment, and FIG. FIG. In the figure, 1 is a silicon substrate, 3 is a collector layer, 6 is a base layer, 7 is an emitter layer, 8 is a collector electrode extraction layer, 9, 10, 11 are low resistance metal wirings, 103 is a silicon oxide film, 104, 10
5, 106 is an oxide film, 202 is a silicon nitride film,
203 is a mask (nitride film), 401 is a passivation film, 501, 511, 512 are metal silicide films, and 601, 611, 612 are polysilicon films. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Scope of Claims] 1. The first conductivity type region on the surface of a silicon substrate in which a first conductivity type region to become a collector layer and a second conductivity type region to become a base layer are formed in a part of the surface portion thereof.
a first step of sequentially forming a silicon oxide film and a silicon nitride film in a region including the junction between the conductive type region and the second conductive type region, on the surface of the silicon substrate including on the silicon nitride film; A second step in which a silicon film is directly formed on the silicon film, and a portion of the silicon film except for a portion where an emitter layer and a collector electrode extraction layer are to be formed is oxidized by a selective oxidation method. A third step of diffusing impurities of the first conductivity type at a high concentration into the silicon film on the portions where the emitter layer and the collector electrode lead-out layer are to be formed using the oxide film as a mask; a fourth step of removing the oxide film after diffusing the impurity from the film and forming the emitter layer;
Using the mask used for selective oxidation in the second step again as a mask, low-temperature oxidation is performed to form a thick oxide film on the side walls of the silicon film and a thin oxide film on the surface of the silicon substrate exposed in the fourth step. A fifth step of forming a film, after removing the thin oxide film on the surface of the silicon substrate while leaving an oxide film on the sidewalls of the silicon film, removing the mask used in the fifth step. a seventh step of forming a metal silicide film on the upper surface of the silicon film exposed in the sixth step and the surface of the silicon substrate; and after depositing a passivation film on the entire upper surface, depositing the metal silicide film on the entire upper surface. A method for manufacturing a semiconductor device, comprising an eighth step of opening a required electrode window on the film and forming a low resistance metal wiring connected to the metal silicide film through the electrode window. 2. The method of manufacturing a semiconductor device according to claim 1, characterized in that a polysilicon film is used as the silicon film.