JPH0136751B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a frame synchronization signal detection circuit.
A video synchronization signal consists of two fields, an odd field and an even field, making up one frame signal.
A frame synchronization signal is generated from the video synchronization signal to synchronize each frame. Conventionally, in high-end video tape recorders that have a rotary erase head and perform completely electronic editing rather than overwrite editing, a frame synchronization signal detection circuit has been installed to prevent screen disturbances at editing points. It is configured to perform frame-by-frame synchronization.

FIG. 2 shows a conventional frame synchronization signal detection circuit, which includes first, second, and third monostable multivibrators 1, 2, and 3 whose time constants are determined by capacitors and resistors, a differentiator circuit 4, and The adder 5 is configured as follows. The first monostable multivibrator [hereinafter referred to as MM1] 1 has a specified time
It is set to a pulse width W of 0.5H or more and 1H or less, and is triggered at the falling edge of the video synchronization signal a in Figure 1A or a in Figure 1B, with a different number of equivalent pulses in even and odd fields. In the even field, the signal b in FIG. 1A from which the equivalent pulse is removed is obtained, and in the odd field, the signal b in FIG. 1B from which the equivalent pulse is removed is obtained. The second monostable multivibrator [hereinafter referred to as MM2] 2 is MM1, 1
It is triggered by the falling edge of the output signal and is used as the horizontal drive signal HD.
However, in the odd field, c in FIG. 1B is output. Comparing these two horizontal drive signals HD, since the number of equivalent pulses is different in the even field and the odd field as described above, the vertical synchronizing signal VD
The horizontal drive signal HD falls at the same time as the start position t, but in the odd field (in the case of FIG. 1B), it falls 0.5H behind the start position t.

Also, the vertical synchronization signal extracted from the video synchronization signal
VD is delayed by a predetermined time by a third multivibrator (hereinafter referred to as MM3) 3, and this signal is passed through a differentiating circuit 4 to generate a pulse P.
The horizontal drive signal HD generated at the MM22 output
If the pulse P and the horizontal drive signal HD are in phase, the level will be doubled and this will become the frame detection output, and if they are out of position, a frame detection output will be generated. do not.

Conventionally, frame synchronization signals are detected in this way, but MM1, MM2, MM31, 2,
3 is used, so there are changes over time, and there are many time constant adjustments to be made during production.Furthermore, since analog signals are used, it is easy to malfunction due to noise.

Therefore, the present invention has been made to avoid the above-mentioned problems, and provides an apparatus in which a frame synchronization signal can be obtained by processing a video synchronization signal with a digital circuit.

An embodiment of the present invention will be described below with reference to FIG.

6 is a first counting means for excluding equal pulses of 0.5H or more and 1H or less from the video synchronization signal V;
The first D-type flip-flop 7 has a clock input CK, and each time the first D-type flip-flop 7 is set, it starts counting the clock signal 8.
Detects the passage of a certain period of time of 0.5H or more and 1H or less.
and a first counter 9 for resetting the D-type flip-flop 7. 10 is a second counting means that outputs the horizontal drive signal HD of a predetermined width synchronized with the video synchronization signal V every time a signal is input;
a second D-type flip-flop 11 whose clock input is the output signal of the D-type flip-flop 7;
A second counter 12 starts counting the clock signal 8 every time the second D-type flip-flop 11 is set, and resets the second D-type flip-flop 11 after a predetermined period of time. A shift register 13 uses the clock signal 8 as a shift pulse to delay the horizontal drive signal HD generated at the output of the second D-type flip-flop 2 for a certain period of time. 14 is a third D-type flip-flop, which receives the video synchronization signal V
The vertical synchronizing signal VD extracted from the shift register 13 is used as a clock input, and the shift register 13 is used as a data input.
A delayed horizontal drive signal HD' is inputted through the gate, and it is detected whether the delayed horizontal drive signal HD' and the vertical synchronization signal VD match or do not match in phase. Note that the shift register 13
The delay amount is set so that the third D-type flip-flop 14 can perform sampling accurately.

With this configuration, the first and second counting means 6 and 10 do not require adjustment because they process digitally using the first and second counters 9 and 12, and there is no problem of aging. , can output accurate signals. Therefore, the output of the third D-type flip-flop 14 is the vertical synchronizing signal VD and the horizontal drive signal.
A frame synchronization signal 15 is generated which has a logic level "H" if the positions are equal to HD', and which has a logic level "L" if the two are not in phase.
Furthermore, since the shift register 13 delays the horizontal drive signal HD of the vertical synchronization signal VD and the horizontal drive signal HD, the amount of delay can be small.

As explained above, according to the present invention, the first pulse excluding the equivalent pulse of 0.5H to 1H from the video synchronization signal
a second counting means for inputting the output signal of the first counting means and outputting the horizontal drive signal of a predetermined width synchronized with the video synchronization signal; and a shift register for delaying the horizontal drive signal. , the output of the shift register is sampled every time the vertical synchronization signal extracted from the video synchronization signal is generated, and two states are detected: a state in which the delayed horizontal drive signal and the vertical synchronization signal match and a state in which the phases do not match. Third
A D-type flip-flop is provided, and when the delayed horizontal drive signal and the vertical synchronization signal are in phase, a frame synchronization signal is obtained at the output of the third D-type flip-flop. The configuration allows the number of adjustment points to be significantly reduced compared to the conventional system, and there is no deterioration over time, and there is no malfunction due to noise.In the present invention, if the clock signal is accurate, a frame detection signal with accurate phase and width can be obtained. The present invention can contribute to high-precision editing of video tape recorders.

[Brief explanation of drawings]

FIG. 1 is a waveform diagram of main parts of a conventional frame synchronization signal detection circuit, FIG. 2 is a diagram of a conventional frame synchronization signal detection circuit, and FIG. 3 is a configuration diagram of an embodiment of the frame synchronization signal detection circuit of the present invention. . 6...First counting means, 7...First D-type flip-flop, 8...Clock signal, 9...First
counter, 10... second counting means, 11...
second D-type flip-flop, 12... second counter, 13... shift register, 14... third
D-type flip-flop, 15...frame detection signal, V...video synchronization signal, HD...horizontal drive signal, VD...vertical synchronization signal.

Claims (1)

[Claims] 1 1st clock input with video synchronization signal as clock input CK
a D-type flip-flop, and a first D-type flip-flop that starts counting the clock signal every time the first D-type flip-flop is set, detects the passage of a certain period of time from 0.5H to 1H, and resets the first D-type flip-flop. a second D-type flip-flop whose clock input CK is the output signal of the first D-type flip-flop; and a second counter that starts counting the clock signal each time the second D-type flip-flop is set and resets the second D-type flip-flop after a predetermined time. a second counting means for outputting the horizontal drive signal of a width, a shift register for delaying the horizontal drive signal, and a second counting means for sampling the output of the shift register each time a vertical synchronization signal extracted from the video synchronization signal is generated. , a third D-type flip-flop is provided for detecting two states in which the phases of the delayed horizontal drive signal and the vertical synchronization signal match and those that do not match, and the phase of the delayed horizontal drive signal and the vertical synchronization signal is A frame synchronization signal detection circuit configured to obtain a frame synchronization signal at the output of the third D-type flip-flop when a match occurs.