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JPH0137072B2 - - Google Patents
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JPH0137072B2 - - Google Patents

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Publication number
JPH0137072B2
JPH0137072B2 JP58162806A JP16280683A JPH0137072B2 JP H0137072 B2 JPH0137072 B2 JP H0137072B2 JP 58162806 A JP58162806 A JP 58162806A JP 16280683 A JP16280683 A JP 16280683A JP H0137072 B2 JPH0137072 B2 JP H0137072B2
Authority
JP
Japan
Prior art keywords
circuit
flash
light
gain
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP58162806A
Other languages
Japanese (ja)
Other versions
JPS6054574A (en
Inventor
Tadashi Okino
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP58162806A priority Critical patent/JPS6054574A/en
Priority to DE19833342992 priority patent/DE3342992A1/en
Publication of JPS6054574A publication Critical patent/JPS6054574A/en
Publication of JPH0137072B2 publication Critical patent/JPH0137072B2/ja
Priority to US08/125,435 priority patent/US5398065A/en
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/70Circuitry for compensating brightness variation in the scene
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/70Circuitry for compensating brightness variation in the scene
    • H04N23/74Circuitry for compensating brightness variation in the scene by influencing the scene brightness using illuminating means

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)

Description

【発明の詳細な説明】 〔発明の分野〕 本発明は撮像管或はCCD等の撮像素子を用い
て被写体像を電気信号に変換する撮像装置に関す
る。
DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to an imaging device that converts a subject image into an electrical signal using an imaging device such as an imaging tube or a CCD.

〔従来技術の説明〕[Description of prior art]

従来、撮像管或はCCD等の撮像素子を使用し
た撮像装置においては撮像素子のダイナミツクレ
ンジが狭く、わずかの露光ずれに対しても撮像素
子の出力レベルが大幅に変化する。そこでこれを
電気的に補正するため、負帰還ループを用いた自
動利得制御回路(以下AGCと称す)を使用して
撮像素子からの出力の大小にかかわらず信号処
理、記録回路に伝達される信号のレベルを常にほ
ぼ一定に保つていた。しかしこのような装置にお
いては、フラツシユ撮影等の如く撮影前の測光条
件と撮影時の露光条件が全く異なる場合にはこれ
に対応できないという欠点を有していた。
Conventionally, in an imaging device using an imaging device such as an image pickup tube or a CCD, the dynamic range of the imaging device is narrow, and the output level of the imaging device changes significantly even with a slight exposure deviation. Therefore, in order to electrically correct this, an automatic gain control circuit (hereinafter referred to as AGC) using a negative feedback loop is used to transmit the signal to the signal processing and recording circuit regardless of the magnitude of the output from the image sensor. The level of was always kept almost constant. However, such an apparatus has the disadvantage that it cannot cope with cases where the photometry conditions before photography and the exposure conditions during photography are completely different, such as in flash photography.

そこで本出願人は特願昭57−208920号におい
て、このような欠点を解消し得る撮像装置を提案
した。
Therefore, in Japanese Patent Application No. 57-208920, the present applicant proposed an imaging device capable of eliminating such drawbacks.

即ち上記撮像装置においてはフラツシユ等の閃
光装置を用いた撮像を行う際には撮像信号のゲイ
ンを所定の一定のゲインとなるよう切換制御する
事により従来の欠点を解消している。
That is, in the above-mentioned image pickup apparatus, the conventional drawbacks are solved by controlling the gain of the image pickup signal to be a predetermined constant gain when taking an image using a flash device such as a flash.

〔目的〕〔the purpose〕

本発明は前記の撮像装置を改良し、より広いダ
イナミツクレンジを有する撮像装置を提供する事
を目的としている。
An object of the present invention is to improve the above-mentioned imaging device and provide an imaging device having a wider dynamic range.

〔実施例〕〔Example〕

以下に添付した図面を参照しながら本発明の内
容について詳しく説明する。第1図は本発明の一
実施例を示す電気系のブロツク図であり、図中1
はCCD、X−Yアドレス型MOSイメージセンサ
ーや撮像管等の撮像手段としての撮像素子であ
り、被写体像を電気信号に変換する。その出力は
信号処理回路2を経て自動利得制御(AGC)回
路3に伝達され、AGC回路3の出力はさらに記
録回路4に導かれる。AGC回路3の利得制御端
子3aは切換手段としてのスイツチ回路5の端子
5dに接続される。スイツチ回路5,6はその制
御端子5a,6aがハイレベルにあるとき端子5
b−5d、6c−6dが導通し、制御端子5a,
6aがローレベルにあるとき端子5c−5d、6
b−6dが導通する。スイツチ回路5の端子5a
は閃光発生回路Bの充電完了端子B1に接続さ
れ、端子5bはスイツチ回路6の端子6dに接続
され、端子5cは反転増幅器16を介してAGC
回路3の出力端に接続される。スイツチ回路6の
制御端子6aは抵抗7とアナログゲート10の接
続点7aに接続され、端子6bは基準電圧源8に
接続され、端子6cはサンプルホールド回路9の
出力端子に接続される。
The contents of the present invention will be explained in detail below with reference to the attached drawings. FIG. 1 is a block diagram of an electrical system showing one embodiment of the present invention.
is an image sensor as an imaging means such as a CCD, an X-Y address type MOS image sensor, or an image pickup tube, and converts a subject image into an electrical signal. The output is transmitted to an automatic gain control (AGC) circuit 3 via a signal processing circuit 2, and the output of the AGC circuit 3 is further guided to a recording circuit 4. A gain control terminal 3a of the AGC circuit 3 is connected to a terminal 5d of a switch circuit 5 as a switching means. The switch circuits 5 and 6 have terminals 5 and 6 when their control terminals 5a and 6a are at high level.
b-5d and 6c-6d are conductive, and control terminals 5a,
When 6a is at low level, terminals 5c-5d, 6
b-6d conducts. Terminal 5a of switch circuit 5
is connected to the charging completion terminal B1 of the flash generation circuit B, the terminal 5b is connected to the terminal 6d of the switch circuit 6, and the terminal 5c is connected to the AGC through the inverting amplifier 16.
Connected to the output end of circuit 3. A control terminal 6a of the switch circuit 6 is connected to a connection point 7a between the resistor 7 and the analog gate 10, a terminal 6b is connected to the reference voltage source 8, and a terminal 6c is connected to the output terminal of the sample and hold circuit 9.

サンプルホールド回路9は制御端子9aがハイ
レベルにあるとき入力電圧をサンプルし、制御端
子9aがローレベルにあるときは直前のサンプル
値を保持する。制御端子9aはタイミングパルス
発生器13に接続され、入力端子は逆数回路12
の出力端子に接続される。アナログスイツチ10
は制御端子10cがハイレベルにあるとき10a
−10bが導通状態に、ローレベルにあるとき非
導通状態になり、制御端子10cにはタイミング
パルス発生器13より出力されるパルスY1が供
給されている。
The sample and hold circuit 9 samples the input voltage when the control terminal 9a is at a high level, and holds the previous sample value when the control terminal 9a is at a low level. The control terminal 9a is connected to the timing pulse generator 13, and the input terminal is connected to the reciprocal circuit 12.
connected to the output terminal of analog switch 10
is 10a when the control terminal 10c is at high level.
-10b is in a conductive state, and is in a non-conductive state when it is at a low level, and the pulse Y1 output from the timing pulse generator 13 is supplied to the control terminal 10c.

垂直同期信号形成回路14、レリーズスイツチ
15の出力端子はともにタイミングパルス発生器
13に接続される。タイミングパルス発生器13
の出力端子は閃光発生回路Bのシンクロ端子B
2、記録回路4の記録制御端子4a等に接続され
る。
The output terminals of the vertical synchronizing signal forming circuit 14 and the release switch 15 are both connected to the timing pulse generator 13. Timing pulse generator 13
The output terminal is the synchro terminal B of the flash generation circuit B.
2. Connected to the recording control terminal 4a of the recording circuit 4, etc.

破線で囲まれた部分Aは閃光の反射光を検出す
る検出手段としての測光回路であり、コンパレー
タ101、基準電圧源102、積分キヤパシタ1
03、受光素子104よりなる。この測光回路A
は閃光発生装置Bの筐体C内に収納されており、
筐体Cは撮像装置16に対して着脱可能にされて
いる。
A portion A surrounded by a broken line is a photometry circuit as a detection means for detecting reflected light from a flash, and includes a comparator 101, a reference voltage source 102, and an integrating capacitor 1.
03, consists of a light receiving element 104. This photometry circuit A
is housed in the casing C of the flash generator B,
The housing C is detachably attached to the imaging device 16.

測光回路A中の受光素子104と積分キヤパシ
タ103の接続点A1はウインドウコンパレータ
11及び逆数回路12の入力に接続される。
A connection point A1 between the light receiving element 104 and the integrating capacitor 103 in the photometric circuit A is connected to the inputs of the window comparator 11 and the reciprocal circuit 12.

尚、端子B1は閃光発生回路B内の不図示のメ
インコンデンサの充電レベルが所定のレベルを越
える、充電完了時点以降ハイレベルとなる。
Note that the terminal B1 becomes high level after the charging level of the main capacitor (not shown) in the flash generation circuit B exceeds a predetermined level and charging is completed.

又、このメインコンデンサは閃光発生回路B内
の不図示の閃光光源を発光させる為のエネルギー
を蓄積する為のものである。
Further, this main capacitor is used to store energy for causing a flash light source (not shown) in the flash light generation circuit B to emit light.

又、ウインドウコンパレータ11、逆数回路1
2、サンプルホールド回路9、アナログスイツチ
10、スイツチ回路6等により本発明に係る補正
手段が形成されている。
Also, window comparator 11, reciprocal circuit 1
2. The sample and hold circuit 9, the analog switch 10, the switch circuit 6, etc. form a correction means according to the present invention.

本発明の一実施例は上述の如き構成からなるも
のであり、以下に第2図も参照しながらその動作
について説明する。
One embodiment of the present invention has the above-described configuration, and its operation will be described below with reference to FIG. 2 as well.

先ず撮像装置の不図示の電源スイツチを入れた
段階では端子B1がローレベルであり、スイツチ
回路5の制御端子5aがローレベルであるからス
イツチ回路5は5c−5d間が導通している。従
つてAGC回路3の利得制御端子3aにはAGC回
路3の出力が反転増幅器16を介してフイードバ
ツクされ、CCD1の出力の利得は一定となるよ
う制御される。
First, when the power switch (not shown) of the imaging device is turned on, the terminal B1 is at a low level, and the control terminal 5a of the switch circuit 5 is at a low level, so that the switch circuit 5 is electrically connected between terminals 5c and 5d. Therefore, the output of the AGC circuit 3 is fed back to the gain control terminal 3a of the AGC circuit 3 via the inverting amplifier 16, and the gain of the output of the CCD 1 is controlled to be constant.

次に閃光発生回路内の不図示の電源スイツチを
ONすると閃光発生回路内のメインコンデンサが
充電され始める。このメインコンデンサの充電エ
ネルギーが閃光発光に十分なものとなつたとき不
図示の表示器により充電完了表示を行うとともに
端子B1がハイレベルとなる。従つてスイツチ回
路5は5b−5d間が導通する。
Next, turn on the power switch (not shown) in the flash generation circuit.
When turned ON, the main capacitor in the flash generation circuit begins to charge. When the charging energy of this main capacitor becomes sufficient for flashlight emission, a display (not shown) indicates the completion of charging and the terminal B1 becomes high level. Therefore, in the switch circuit 5, conduction occurs between 5b and 5d.

又、メインコンデンサの充電が完了した後レリ
ーズスイツチ15をONすると、第2図bに示す
如くレリーズ信号X1が形成され、タイミングパ
ルス発生器13の作用によりレリーズしたフイー
ルドの次のフイールド期間内の適当なタイミング
で出力端子Y0よりシンクロ信号を発生させる。
(第2図c)但し、撮像素子が撮像管やX−Yア
ドレス型イメージセンサーの場合はレリーズ後の
垂直ブランキング期間内にこのシンクロ信号を発
生させる。Y0よりのシンクロ信号は閃光発生回
路の入力端子B2に入力され、閃光光源を発光さ
せる。閃光照射による被写体からの反射光は受光
素子104によつて光電変換され、その電気信号
で積分キヤパシタ103を充電する。積分キヤパ
シタの充電電圧は反射光量に応じてしだいに上昇
し、それが基準電圧源102の電圧よりも高くな
ると、コンパレータ101の出力はローレベルか
らハイレベルに変化し、、それが閃光発生回路B
に入力される。これにより閃光発生回路B内の閃
光光源の発光を停止させる。
When the release switch 15 is turned on after the charging of the main capacitor is completed, a release signal X1 is generated as shown in FIG. Generate a synchronization signal from the output terminal Y0 at an appropriate timing.
(Fig. 2c) However, if the image pickup device is an image pickup tube or an X-Y address type image sensor, this synchronization signal is generated within the vertical blanking period after release. The synchronization signal from Y0 is input to the input terminal B2 of the flash generation circuit, causing the flash light source to emit light. The reflected light from the object caused by the flash irradiation is photoelectrically converted by the light receiving element 104, and the integral capacitor 103 is charged with the electrical signal. The charging voltage of the integrating capacitor gradually increases according to the amount of reflected light, and when it becomes higher than the voltage of the reference voltage source 102, the output of the comparator 101 changes from low level to high level, which causes the flash generation circuit B to
is input. This causes the flash light source in the flash light generation circuit B to stop emitting light.

閃光光源の発光に十分と思われる時間(例えば
数msec)が経過してからタイミングパルス発生
器13の端子Y1より次のフイールド分までの長
さをもつ正のパルスを発生する。(第2図d) またパルスY1とともに立上りパルス幅の非常
に短いサンプリング用のパルスY2を発生させる。
(第2図e) このようにする事によりもしも閃光光源による
照明が適切であつて、被写体からの反射光の光電
変換積分値が基準電圧源102の電圧とほぼ等し
い場合、即ち適切な調光が試された場合、ウイン
ドウコンパレータ11の出力はローレベルにあ
り、この信号Y1がハイレベルの間アナログスイ
ツチ10、抵抗7を介してアースに導かれる。従
つて接続点7aはローレベルになりスイツチ回路
6は端子6bと6d間が導通する。よつてAGC
回路3の利得制御端子3aには基準電圧源8から
の一定電圧が入力され、AGC回路3は所定の固
定利得モードで動作する。
After a period of time considered sufficient for the flash light source to emit light (for example, several milliseconds), a positive pulse having a length up to the next field is generated from the terminal Y1 of the timing pulse generator 13. (Fig. 2d) In addition to the pulse Y1 , a sampling pulse Y2 having a very short rising pulse width is generated.
(Fig. 2 e) By doing this, if the illumination by the flash light source is appropriate and the photoelectric conversion integral value of the reflected light from the subject is approximately equal to the voltage of the reference voltage source 102, in other words, appropriate dimming is possible. is tested, the output of the window comparator 11 is at a low level, and while this signal Y1 is at a high level, it is guided to ground via the analog switch 10 and the resistor 7. Therefore, the connection point 7a becomes low level, and the switch circuit 6 becomes conductive between the terminals 6b and 6d. Yotsute AGC
A constant voltage from a reference voltage source 8 is input to the gain control terminal 3a of the circuit 3, and the AGC circuit 3 operates in a predetermined fixed gain mode.

一方もしも閃光の光量が被写体距離、反射率に
対して不十分であつたり、閃光発生回路による光
量制御がうまくいかなかつたりして被写体からの
反射光の光電変換分積値が基準電圧源102の電
圧と大幅にかけはなれた値になつた場合、ウイン
ドウコンパレータ11の出力はハイレベルとな
り、パルスY1がハイレベルの間アナログスイツ
チ10、抵抗7を介してアースに導かれ、スイツ
チ回路6の制御端子6aはハイレベルになる。従
つてスイツチ回路6は端子6c−6d間が導通す
る。その結果AGC回路3の利得制御端子3aに
はサンプルホールド9の出力が入力される。サン
プルホールド回路出力には閃光発光完了直後の積
分キヤパシタ103の充電電圧の逆数に比例する
電圧が保持されている。
On the other hand, if the light intensity of the flash is insufficient for the subject distance and reflectance, or if the light intensity control by the flash generation circuit is not successful, the photoelectric conversion integral value of the reflected light from the subject may be lower than that of the reference voltage source 102. When the voltage is significantly different from the voltage, the output of the window comparator 11 becomes high level, and while the pulse Y1 is at high level, it is led to the ground via the analog switch 10 and the resistor 7, and the control terminal of the switch circuit 6 is connected to the ground. 6a becomes high level. Therefore, the switch circuit 6 is electrically connected between the terminals 6c and 6d. As a result, the output of the sample hold 9 is input to the gain control terminal 3a of the AGC circuit 3. A voltage proportional to the reciprocal of the charging voltage of the integrating capacitor 103 immediately after the completion of flash emission is held at the output of the sample and hold circuit.

従つて、被写体からの反射光量が過多の場合即
ち積分キヤパシタ103の充電電圧源102のレ
ベルより非常に高い場合、サンプルホールド回路
の出力電圧は低くAGC回路3の利得は小さくさ
れる。逆に被写体からの反射光量が少ない場合、
AGC回路3の利得は大きくなる。従つて、閃光
照明の反射光量が撮像素子の要求と比べて大きく
かけ離れている場合にも、電気的にこれを補正す
る向きにAGC回路が作動する。
Therefore, when the amount of reflected light from the object is excessive, that is, when it is much higher than the level of the charging voltage source 102 of the integrating capacitor 103, the output voltage of the sample and hold circuit is low and the gain of the AGC circuit 3 is reduced. Conversely, if the amount of reflected light from the subject is small,
The gain of AGC circuit 3 increases. Therefore, even if the amount of reflected light from the flash illumination is significantly different from the requirement of the image sensor, the AGC circuit operates to electrically correct this.

以上の如くして利得制御回路の利得調整のなさ
れた信号はタイミングパルス発生器13から第2
図fに示したタイミングパルスY3を記録回路4
に供給する事によつて記録される。
The signal whose gain has been adjusted in the gain control circuit as described above is sent from the timing pulse generator 13 to the second
The recording circuit 4 records the timing pulse Y3 shown in Figure f.
recorded by supplying the

尚、第1図示の実施例では測光回路Aを閃光発
生回路Bの筐体内に設けているが、TTL調光等
を行う場合にはこの回路Aは撮像装置内に設けて
も良い。
In the embodiment shown in the first figure, the photometric circuit A is provided within the housing of the flash generation circuit B, but when performing TTL light control or the like, this circuit A may be provided within the imaging device.

又、本実施例では照明光として閃光(例えばス
トロボ光、フラツシユバルブ光)を考えている
が、本発明は照明開始直後に少なくとも1画分の
被写体像信号を形成し記録する場合すべてに適用
し得る事は勿論であり、その場合照明光は立上り
速度が大きいものであれば良く、発光後も暫く点
灯しているような閃光であつても何ら差し支えな
い。
Further, in this embodiment, flash light (e.g., strobe light, flash bulb light) is considered as the illumination light, but the present invention is applicable to any case where at least one frame of a subject image signal is formed and recorded immediately after the start of illumination. Of course, it is possible to do so, and in that case, the illumination light only needs to have a high rise speed, and there is no problem even if it is a flash of light that remains on for a while after being emitted.

〔効果〕〔effect〕

以上説明した如く、本発明の撮像装置によれ
ば、被写体像を電気信号に変換する撮像手段、前
記電気信号の利得を自動制御する自動利得制御回
路、閃光撮影時に前記電気信号の利得を所定値と
する切換手段、閃光の反射光量に応じて前記利得
を補正する補正手段を有するので、被写体を瞬間
的に照明し、これにより得られる被写体像を撮像
する場合に、自動利得制御回路による応答性をカ
バーし得るだけでなく、閃光撮影時の露光ミス等
を簡単に補正し得る効果を有する。
As described above, the imaging device of the present invention includes an imaging means that converts a subject image into an electrical signal, an automatic gain control circuit that automatically controls the gain of the electrical signal, and a gain control circuit that automatically controls the gain of the electrical signal to a predetermined value during flash photography. and a correction means for correcting the gain according to the amount of reflected light from the flash, so that when a subject is momentarily illuminated and a subject image obtained thereby is captured, the responsiveness of the automatic gain control circuit is improved. This has the effect of easily correcting exposure errors and the like during flash photography.

即ち、閃光撮影に際し調光回路により発光量制
御を行う場合に、極めて近接した被写体や、反射
率の高い被写体に対しては閃光発光直後に発光停
止をしなければならない。しかし調光回路の応答
特性によつてはこれを正確に行うのに困難な場合
があり、露出の誤差を生じる。このような場合に
おいても本発明によれば、適正な信号レベルが得
られるものである。従つて、広いダイナミツクレ
ンジを得る事ができる。
That is, when controlling the amount of light emitted by a light control circuit during flash photography, it is necessary to stop the light emission immediately after the flash light is emitted for a very close subject or a subject with a high reflectance. However, depending on the response characteristics of the dimming circuit, it may be difficult to do this accurately, resulting in exposure errors. Even in such a case, according to the present invention, an appropriate signal level can be obtained. Therefore, a wide dynamic range can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の撮像装置の一実施例の構成
図、第2図はその動作タイミング図である。 1;撮像手段としてのCCD等の撮像素子、
2;信号処理回路、3;自動利得制御(AGC)
回路、4;記録回路、5;切換手段としてのスイ
ツチ回路、6;スイツチ回路、8,102;基準
電圧源、9;サンプルホールド回路、10;アナ
ログスイツチ、11;ウインドウコンパレータ、
12;逆数回路、13;タイミングパルス発生
器、14;垂直同期信号形成回路、15;レリー
ズスイツチ、16;反転増幅器、A;測光回路、
101;コンパレータ、103;積分キヤパシ
タ、104;受光素子、B;閃光発生回路、C;
閃光発生回路筐体、16;撮像装置。
FIG. 1 is a configuration diagram of an embodiment of an imaging apparatus according to the present invention, and FIG. 2 is an operation timing diagram thereof. 1; An imaging device such as a CCD as an imaging means;
2; Signal processing circuit, 3; Automatic gain control (AGC)
Circuit, 4; Recording circuit, 5; Switch circuit as switching means, 6; Switch circuit, 8, 102; Reference voltage source, 9; Sample and hold circuit, 10; Analog switch, 11; Window comparator,
12; reciprocal circuit, 13; timing pulse generator, 14; vertical synchronization signal forming circuit, 15; release switch, 16; inverting amplifier, A; photometric circuit,
101; Comparator, 103; Integrating capacitor, 104; Light receiving element, B; Flash generation circuit, C;
Flash generation circuit housing, 16; imaging device.

Claims (1)

【特許請求の範囲】 1 被写体像を電気信号に変換する撮像手段、該
撮像手段の電気信号の利得を可変制御する利得制
御手段、 前記被写体からの光量を検出する為の前記撮像
手段とは別の光量検出手段、 閃光照明を用いた静止画記録に際して前記利得
制御手段における信号利得を所定値とする為の制
御信号形成手段、前記検出手段により被写体から
の光量を検出し該光量に応じて前記利得制御手段
における信号利得を前記所定値以外の値に補正す
る補正手段、 を有する撮像装置。
[Scope of Claims] 1. Imaging means for converting a subject image into an electrical signal, gain control means for variably controlling the gain of the electrical signal of the imaging means, separate from the imaging means for detecting the amount of light from the subject. a light amount detection means, a control signal forming means for setting the signal gain in the gain control means to a predetermined value when recording a still image using flash illumination, and a control signal forming means for detecting the light amount from the subject by the detection means, An imaging device comprising: correction means for correcting the signal gain in the gain control means to a value other than the predetermined value.
JP58162806A 1982-11-29 1983-09-05 Image pickup device Granted JPS6054574A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP58162806A JPS6054574A (en) 1983-09-05 1983-09-05 Image pickup device
DE19833342992 DE3342992A1 (en) 1982-11-29 1983-11-28 Image converter device
US08/125,435 US5398065A (en) 1982-11-29 1993-09-22 Image sensing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58162806A JPS6054574A (en) 1983-09-05 1983-09-05 Image pickup device

Publications (2)

Publication Number Publication Date
JPS6054574A JPS6054574A (en) 1985-03-29
JPH0137072B2 true JPH0137072B2 (en) 1989-08-03

Family

ID=15761571

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58162806A Granted JPS6054574A (en) 1982-11-29 1983-09-05 Image pickup device

Country Status (1)

Country Link
JP (1) JPS6054574A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2787147B2 (en) * 1987-05-22 1998-08-13 株式会社ニコン Electronic camera
JPH03126383A (en) * 1989-10-12 1991-05-29 Nikon Corp Electronic still camera

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5646364U (en) * 1979-09-14 1981-04-25
JPS5731270A (en) * 1980-08-04 1982-02-19 Toshiba Corp Flash pickup device
JPS58147721A (en) * 1982-02-26 1983-09-02 Canon Inc Camera

Also Published As

Publication number Publication date
JPS6054574A (en) 1985-03-29

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