JPH0139134B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for duplicating input/output devices in a computer.

In systems using computers, CPUs and input/output devices are often duplicated to improve reliability. In order to duplicate an auxiliary storage device as an input/output device, conventionally, the configuration shown in FIG. 1A or B is used. In Figure A, the auxiliary storage devices 1 and 2 are individually coupled to the system bus 3 via their respective controllers, and the CPU 4 uses the auxiliary storage devices 1 and 2 to exchange data between the CPU 4 or the memory 5 and the auxiliary storage devices 1 and 2. 2 individually. Therefore, in order to exchange data, it is necessary to prepare software that performs the same operation twice. In FIG. 1B, one dedicated controller 6 is provided for two auxiliary storage devices 1 and 2, and this controller writes the same data to the auxiliary storage devices 1 and 2, reads it, and checks for errors. This method requires a dedicated controller for the target device for duplication, and requires the development of its software. As described above, the conventional method imposes a double burden on the software or requires the development of a dedicated controller, resulting in problems with system performance deterioration and cost.

The present invention provides a bus controller between the controller of the input/output device and the system bus, and the bus controller controls data transfer between the redundant input/output device and the CPU or memory, thereby making it possible to use relatively simple hardware and software. The purpose is to provide a redundancy method that makes it possible to reduce the burden.

The method of the invention is illustrated conceptually by FIG. A bus controller 7 is provided between the system bus 3 and input/output devices 1 and 2 such as auxiliary storage devices.
A bus controller 7 transfers data between the controllers 1a and 2a of the input/output devices 1 and 2 and the bus 3.
It is controlled according to the control signal from the CPU4 side. As before, the input/output devices 1 and 2 are each assigned a unique address, and the bus controller 7 is connected to the CPU as shown by the solid line in FIG. 2A.
A function of controlling the input/output devices 1, 2 so that they can each send and receive individual data as separate devices by a control signal from the 4 side, and input/output devices 1, 2 as shown in FIG. 2B. It also has a control function that allows it to send and receive the same data as a duplex device. The redundant control shown in Figure 2B involves apparently matching the addresses of the two input/output devices 1 and 2, and writing the same data to the input/output devices 1 and 2 with one access from the CPU 4 side. The same data is read out from both devices 1 and 2, including priority processing and correct/incorrect checking.

FIG. 3 is a control mode diagram showing each function of the bus controller 7 individually. The bus controller 7 includes an input section 7A that exchanges control signals with the control bus of the system bus 3 and receives designated address signals of the input/output devices 1 and 2 with the address bus. 7A obtains various control signals from the ROM circuit in accordance with bus-side control signals or internal control signals to change the coupling manner between the input/output devices 1 and 2 and the bus 3.

Figure 3A shows the case where the input/output devices 1 and 2 are individually connected to the bus 3, and the enable bit of the input section 7A is set to "0" by a control signal from the CPU side.
By doing so, the duplication function is disabled and the input/output devices 1 and 2 have individual addresses and control signals are obtained for transmitting and receiving data individually with the CPU or memory. This combined state is the same as a normal system configuration, for example, when the input/output devices 1 and 2 are auxiliary storage devices, the storage capacity is doubled.

Figure 3 B and C are cases in which the input/output devices 1 and 2 are duplicated, of which B is the case in which data from the CPU or memory is written to the input/output devices 1 and 2, and conversely, C is the case in which the input/output devices 1 and 2 are duplicated. This is a case where data is read from 1 and 2. In this state of B and C, the input section 7A
The enable bit of is set to "1" to provide a duplex coupling function. In state B, the read/write (R/W) bit of the input section 7A is set to " ₁ " and the address input of the symbol line switching section 7B is switched from line _L1 to _L2 by the output line C1. The address input (line L ₃ ) to the input/output device 2 is made to be the address specified from line L ₂ . At this time, the address signal from the CPU side is set to the unique address of input/output device 1, and this address signal is connected to the control, data, and address lines.
The data is input to the input/output device 1 through _L4 and written, and the address converter 7C, which receives the address signal as input, converts it into a unique address of the input/output device 2 on the condition that the read/write signal is read. Send to line _L2 . Therefore, the same data can be written to both input/output devices 1 and 2 by an address signal specifying input/output device 1.

In state C, the enable bit is “1” (line
C ₁ ) causes the switching section 7B to slightly disconnect lines L ₁ and L ₃ in the same manner as in the above-mentioned state B.
The input/output device 2 is also addressed by coupling and address conversion between L ₂ and L ₃ , and data is read from both input/output devices. Among these, both data of the input/output devices 1 and 2 are selected by the data selection unit 7d based on the priority of the two, or logical product (or logical sum) is taken (synchronized) and output onto the bus 3. be done. Note that the data output from the input/output devices 1 and 2 is also taken in by the error detection section 7e and checked for errors, and the input/output devices 1 and 2 themselves are also checked for errors, and it is determined by this check that there are no errors. When data and addresses are allowed to be output to the system bus 3, the line _C1 of the input section 7A is made inactive through the line _L5 in the event of a fatal error.

Therefore, according to the present invention, control from the CPU side allows data transfer to and from the two input/output devices 1 and 2 with a single address specification, realizing redundancy that reduces the software load on the CPU side. can.
Furthermore, the input/output device itself, including its controller, handler, and interface, does not require any special processing on conventional devices, and the bus controller 7
The configuration can be realized with a small number of gate element circuits. Further, the input/output devices 1 and 2 can be switched to separate data exchange as independent devices, and implementation of duplication can be freely selected depending on the type of input/output devices to be combined.

Note that the input/output device is not limited to an auxiliary storage device, but can also be used to provide a logging function for duplicating typewriter printing.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of a conventional duplexing method, FIG. 2 is a conceptual explanatory diagram of the present invention, and FIG. 3 is a diagram showing individual control aspects in the present invention. 1, 2...I/O device, 3...System bus, 4...
CPU, 5...Memory, 7...Bus controller, 7
A...Input section, 7B...Symbol line switching section,
7C...address conversion section, 7d...data selection section, 7
e...Error detection unit.

Claims (1)

[Claims] 1. A bus controller is provided between the system bus of the computer and two input/output devices having the same function and unique addresses, and the bus controller connects the two input/output devices to the system according to a control signal. Input section 7A for individual coupling or double coupling to the bus, and in the double coupling state
an address conversion unit 7C that converts the unique address signal of one input/output device 1 from the CPU side into a unique address signal of the other input/output device 2 when reading/writing data to the input/output device; In the duplex connection state, switching to address designation of the other input/output device 2 using an address signal from the address converter instead of the address designation signal from the CPU side, and reading/writing data to the input/output device. a switching section 7B that causes the input/output device 1 to read/write the same data as the input/output device 1, and a data that outputs the same data read from both the input/output devices as one data onto the system bus by synchronization processing or priority. a selection section;
and an error detection unit that performs an error check on the same data read from both the input/output devices, and performs duplex read/write control of the same data to both the input/output devices in a duplex connection state. How to duplicate output devices.