JPH0139137B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a memory access control device that controls continuous access to data consisting of a plurality of elements in an information processing device.

[Prior art]

Conventionally, as a method for accessing data consisting of multiple elements, each element of which is arranged at equal intervals on the memory, it is tested whether the memory unit to be accessed element by element is in the used state, and the memory unit is used. A method has been proposed in which if there is no state, an access request signal is sent to the memory. According to this method, the amount of hardware can be reduced if the number of memory units is small, but the disadvantage is that the amount of hardware increases if the number of memory units is large. Furthermore, devices that handle data consisting of a plurality of elements generally tend to increase the number of memory units and avoid connections within the memory units, resulting in a noticeable disadvantage of an increase in the amount of hardware. As a method to solve this drawback of increasing the amount of hardware, all memory units are set to be in use.
A method has been proposed in which the sending of access request signals to memory is restricted so that conflicts within memory units do not occur. According to this method, after sending an access request signal for the last element of the preceding data, all memory units are in use for the cycle time of the memory unit, and the subsequent data is accessed by the preceding data. If an attempt is made to access a memory unit that has not been accessed, the user will have to wait for the cycle time of the memory unit, which poses a performance problem.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory access control device which eliminates the above-mentioned drawbacks and allows continuous access of data consisting of a plurality of elements at high speed.

[Structure of the invention]

A memory access device of the present invention controls access to data consisting of a plurality of elements, each element of which is arranged consecutively on the memory, to a memory that is addressed in the order of a plurality of memory units that can be accessed independently of each other. A control device, comprising: supply means for supplying the number of data elements; supply means for supplying address information in memory units of the first element; a calculation means for calculating the address information of the last element, and a holding means for holding the address information of the memory unit of the last element of the data consisting of the first plurality of elements; By calculating the difference between the memory unit address information of the first element of the data consisting of a second plurality of elements that is accessed subsequently to the data of and calculating means for calculating a time interval at which an access request based on the data consisting of the second plurality of elements can be sent to the memory unit that is connected to the memory unit.

[Embodiments of the invention]

Next, the present invention will be explained in detail with reference to the drawings.

Referring to FIG. 1, one embodiment of the present invention is comprised of adder circuits 1, 4, 6 and 9, register 2, complement circuits 3, 5 and 8, and gate circuit 7. Adder circuit 1 adds the number of elements of data supplied via connection 101 and the address information of the first element of data supplied via connection 102, and further subtracts the value "1" to obtain the address information of the last element of data. Address information is obtained and supplied to register 2 via connection 103. Register 2 is the adder circuit 1
The address information of the final element of data which is the output of is held, and the held content is supplied to the adder circuit 4 via the connection 104. The catch circuit 3 is connected to the connection 102.
The two's complement number of the address information of the first element of the data supplied via the link 105 is obtained, and the complement number is supplied to the adder circuit 4 via the connection line 105. The adder circuit 4 adds the address information of the last element of the data supplied via the connection 104 and the two's complement of the address information of the first element of the data supplied via the connection 105, and adds the address information of the last element of the data supplied via the connection 105, The difference between the address information of the element and the address information of the first element of the data is calculated and supplied to the complement circuit 5 and the adder circuit 9 via a connection 106. The complement circuit 5 is a circuit for calculating the one's complement of the difference between the address information of the last element of the data and the address information of the first element of the data, and is supplied to the adder circuit 6 via a connection 107. The adder circuit 6 receives the one's complement of the difference of the address information supplied via the connection 107 and
8 and memory unit cycle time information supplied via connection 109 to the gate circuit 7 via connection 109.
supply to. Depending on the logic value of the signal supplied via the connection 111, the gate circuit 7 determines whether the data supplied via the connection 109 is the value "0" or not via the connection 112.
The output is the number of clock cycles required for queuing. The complement circuit 8 takes the two's complement of the memory unit cycle time information supplied via the connection 108 and is supplied to the adder circuit 9 via the connection 110. The adder circuit 9 adds the difference of the address information supplied via the connection 106 and the two's complement of the cycle time information of the memory unit supplied via the connection 110, and further adds the value "1". The most significant bit is supplied to the gate circuit 7 via connection 111.

The operation of one embodiment with the above configuration will be described in detail. In this example, the number of memory units is
It is assumed that the cycle time per memory unit is 16 clock cycles, and the number of data elements is up to 64. When the first data access request is issued, the number of data elements is transferred via the connection 101 to the connection 10.
The address information of the first element is supplied via 2,
The adder circuit 1 adds the number of data elements, the address information, and the value "1" to obtain the address information of the final element, which is held in the register 2. The contents held in register 2 are held until a second data access request is issued. When the sending of the first data access request to the memory is started, a second data access request is issued. When a second data access request is issued, connection 102
The address information of the first element sent through is converted into two's complement by the complement circuit 3, and the address information of the last element of the first data held in the register 2 and the address information of the last element of the first data held in the register 2 by the adder circuit 4 are added to the connection 102. The difference in the address information of the first element of the second data supplied from the second data is determined. Connection 1 determined by complement circuit 8
By adding the two's complement of the memory unit cycle time Tc supplied via 08 and the value "1" in the adder circuit 9, the memory unit cycle time (Tc-1), i.e., is calculated from the difference in the address information. 1
5 is subtracted, and depending on the magnitude of the difference between the address information and the cycle time information, the most significant bit corresponding to the sign is connected to connection 1 as a signal for controlling the gate circuit 7.
11. That is, if the difference in the address information is 15 or more, the gate circuit 7
As soon as the output of ``0'' becomes the value and the access to the memory for the first data is completed, it becomes possible to send an access request signal to the memory for the second data. This means that when multiple elements are arranged consecutively on the memory, the second data will be accessed in the next clock cycle after sending the memory access request signal for the last element of the first data, as shown in Figure 2. Even if the memory access request signal for the first element of the second data is sent, the memory unit corresponding to the address information of the first element of the second data is in a usable state in that cycle. The memory unit is ready for use at the timing when the second data access request to the memory unit corresponding to the address information of the final element of the first data is sent. Therefore, if the difference in the address information is 15 or more, access to the first element of the second data will not be possible in the next clock cycle after sending the access request signal for the last element of the first data to the memory. Even if the request signal is sent to the memory, the second data access request signal is not sent to the memory unit that is in use due to the first data access request. Also, if the difference in address information is negative,
Since addition is performed modulo 64, adder circuit 4
The output can be used as is. For example, if the first element of the second data is 54 from the address information of the last element of the first data, the difference in address information is -
49, but the output of the adder circuit 4 is 15, which is the value modulo 64. In this case, the memory access request signal for the first data can be sent out in the next clock cycle after sending out the memory access request signal for the final element of the first data. Next, when the difference in address information is less than 15, the adder circuit 9 subtracts Tc-1, that is, 15, from the difference in address information, so the output of the adder circuit 9 becomes negative, and the connection 11
The logical value of 1 is "1". Therefore, the output of the adder circuit 6 is sent out from the gate circuit 7 via the connection 112. The adder circuit 6 adds the one's complement of the difference in address information obtained by the complement circuit 5 and the cycle time Tc of the memory unit supplied by the connection 108, subtracts the difference in the address information from this Tc, and further adds 1's complement of the difference in address information obtained by the complement circuit 5. The value obtained by subtracting the value is output. For example, if the difference in address information is 14, the output of adder circuit 6 is 16-14-1, which is the value "1," and the most significant bit of adder circuit 9 is 14-16+1, which is the value "-1." becomes. Therefore, the logic value of the connection 111 is "1", the output of the gate circuit 7 is the value "1", and the number of clock cycles required for waiting is one clock cycle. This is the third
As shown in the figure. The access request signal to the memory of the second data is sent from the timing when the access request signal to the memory of the final element of the first data is sent (number of waiting clock cycles).
Starts +1 number of clock cycles later. If the difference in address information is 14, an access request to the memory of the last element of the first data is sent.2
Sending of the access request signal to the memory for the second data starts after a clock cycle.

〔Effect of the invention〕

The present invention calculates the address information of the last element of the first data, compares it with the address information of the first element of the second data, and calculates the number of waiting clock cycles from the relationship between the address information and the cycle time of the memory unit. By configuring the memory unit to be able to perform calculations, it is possible to predict the timing at which a memory unit will no longer be in use, and to hasten the sending of the second data access request signal.

[Brief explanation of drawings]

FIG. 1 is a diagram showing one embodiment of the present invention, and FIG.
This figure and FIG. 3 are diagrams showing the relationship between address information, memory units in use, and the timing of sending an access request signal to the memory. In Figures 1 to 3, 1, 4, 6, 9...
Addition circuit, 2...Register, 3, 8...2's complement circuit, 5...1's complement circuit, 7... Gate circuit, 101
...Data element number line, 102...Address information line of the first element of data, 103-107, 109-1
11... Connection, 108... Memory unit cycle time information line, 112... Queue clock cycle number line.

Claims (1)

[Claims] 1. Memory access control that controls access to data consisting of a plurality of elements arranged consecutively on a memory, each of which is arranged in sequence on a plurality of memory units that can be accessed independently of each other. The apparatus comprises: a supply means for supplying the number of data elements; a supply means for supplying address information in memory units of the first element; and a final element from the number of data elements and the address information in memory units of the first element. calculation means for calculating memory unit address information of the last element; holding means for holding memory unit address information of the final element; and memory unit address information of the final element of the data consisting of the first plurality of elements; accessing the first multi-element data by calculating the difference between the memory unit address information of the first element of the second multi-element data that is accessed subsequently to the multi-element data; 2. A memory access control device, comprising: calculation means for calculating a time interval at which an access request based on data made up of the second plurality of elements can be sent to a memory unit that is in a used state.