JPH0139141B2 - - Google Patents
Info
- Publication number
- JPH0139141B2 JPH0139141B2 JP58242582A JP24258283A JPH0139141B2 JP H0139141 B2 JPH0139141 B2 JP H0139141B2 JP 58242582 A JP58242582 A JP 58242582A JP 24258283 A JP24258283 A JP 24258283A JP H0139141 B2 JPH0139141 B2 JP H0139141B2
- Authority
- JP
- Japan
- Prior art keywords
- processor
- communication
- inter
- command
- control device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
- G06F15/17356—Indirect interconnection networks
- G06F15/17368—Indirect interconnection networks non hierarchical topologies
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Physics (AREA)
- Software Systems (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Multi Processors (AREA)
- Maintenance And Management Of Digital Transmission (AREA)
Description
【発明の詳細な説明】
発明の属する技術分野
本発明は、情報処理システムにおける複数プロ
セツサ間のプロセツサ間通信方式に関し、特に、
プロセツサ間通信時の通信経路選択に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to an inter-processor communication system between multiple processors in an information processing system, and in particular, to
This relates to communication route selection during inter-processor communication.
従来の技術
従来、この種のプロセツサ間通信方式はプロセ
ツサ間通信を制御するプロセツサ間通信制御装置
がプロセツサ毎に必要であり、通信先への通信経
路は通信制御装置により一通りに決まつていた。Conventional technology Conventionally, this type of inter-processor communication system required an inter-processor communication control device for each processor to control inter-processor communication, and the communication route to the communication destination was determined by the communication control device. .
また、複数通信経路の構成にするには、各プロ
セツサに複数のプロセツサ間通信制御装置を接続
し、まつたく独立した通信経路を形成していた。 Furthermore, in order to configure a plurality of communication paths, a plurality of interprocessor communication control devices are connected to each processor to form completely independent communication paths.
したがつて、プロセツサ間通信制御装置または
通信経路に障害が発生すると、通信がまつたく不
能、あるいは特定プロセツサとの通信が不能とな
ることがあつた。 Therefore, if a failure occurs in the interprocessor communication control device or the communication path, communication may become completely impossible, or communication with a specific processor may become impossible.
また、複数通信経路構成を行うと、プロセツサ
間通信制御装置が多数必要となり高価なものとな
つていた。 Furthermore, when a plurality of communication paths are configured, a large number of interprocessor communication control devices are required, resulting in an expensive device.
発明の目的
本発明は従来の技術に内在する上記諸欠点を解
消する為になされたものであり、従つて本発明の
目的は、少ないプロセツサ間通信制御装置におい
てもプロセツサによる通信経路の選択を行なえる
様にすることにより、通信経路故障時の代替通信
経路の使用を容易にするとともに、通信経路の負
荷分散も行なえる様にした新規なプロセツサ間通
信手段を提供することにある。OBJECT OF THE INVENTION The present invention has been made in order to eliminate the above-mentioned drawbacks inherent in the conventional technology.Therefore, an object of the present invention is to enable processors to select communication paths even in a small number of inter-processor communication control devices. It is an object of the present invention to provide a new inter-processor communication means which facilitates the use of an alternative communication path in the event of a failure of the communication path and also enables load distribution of the communication path.
発明の構成
上記目的を達成する為に、本発明に係るプロセ
ツサ間通信方式は、プロセツサ問通信コマンドに
発信元プロセツサ及び受信元プロセツサを示すプ
ロセツサ毎にユニークなプロセツサ識別子を付与
する手段を有するプロセツサと、プロセツサを接
続可能なプロセツサポートを複数個有し前記プロ
セツサポートの一つを選択することが可能なプロ
セツサ間通信制御装置と、前記プロセツサが自由
に選択でき前記プロセツサと前記プロセツサ間通
信制御装置とを接続する通信経路とを具備して構
成される。Structure of the Invention In order to achieve the above object, the inter-processor communication system according to the present invention provides a processor-to-processor communication method that includes means for assigning a unique processor identifier for each processor indicating a source processor and a receiving processor to a processor-interrogation communication command. , an inter-processor communication control device having a plurality of processor supports to which processors can be connected and capable of selecting one of the processor supports; and a communication control device between the processor and the processor, which allows the processor to freely select one of the processor supports. The device is configured to include a communication path for connecting with the device.
発明の実施例
次に本発明をその好ましい一実施例について図
面を参照して詳細に説明する。Embodiments of the Invention Next, a preferred embodiment of the present invention will be described in detail with reference to the drawings.
第1図は本発明による一実施例の全体構成を示
すブロツク図である。図において、本発明の一実
施例は、複数のプロセツサ10,11,30,3
1と、複数のプロセツサ間通信制御装置20,2
1,22と、複数のプロセツサ10,11,3
0,31と複数のプロセツサ間通信制御装置2
0,21,22とを結ぶ通信線100〜105,
300〜305からなつている。 FIG. 1 is a block diagram showing the overall configuration of an embodiment according to the present invention. In the figure, one embodiment of the present invention includes a plurality of processors 10, 11, 30, 3
1, and a plurality of inter-processor communication control devices 20, 2
1, 22, and a plurality of processors 10, 11, 3
0, 31 and a plurality of processor communication control devices 2
Communication lines 100 to 105 connecting 0, 21, 22,
It consists of 300-305.
第2図は第1図のプロセツサ10とプロセツサ
間通信制御装置20とプロセツサ30及びその間
を結ぶ通信線100及び300を示した部分ブロ
ツク図である。図において、プロセツサ10には
通信用コマンド出力時にコマンドにプロセツサ識
別子を付与する識別子付与部110と、プロセツ
サ10と他のプロセツサとの接続状態を示す構成
テーブル120とを有し、その他のプロセツサ1
1,30及び31も同様に識別子付与部及び構成
テーブルを有する。 FIG. 2 is a partial block diagram showing the processor 10 of FIG. 1, the interprocessor communication control device 20, the processor 30, and the communication lines 100 and 300 connecting them. In the figure, a processor 10 has an identifier assigning unit 110 that assigns a processor identifier to a command when outputting a communication command, and a configuration table 120 that indicates the connection state between the processor 10 and other processors.
1, 30, and 31 similarly have an identifier assigning section and a configuration table.
プロセツサ間通信制御装置20は、複数のプロ
セツサと接続するためのポート200,201,
202及び203と、プロセツサ識別子とポート
との対応を知るための対応表記憶部210と、各
ポートからのコマンドを貯わえるためのコマンド
バツフア220とを有する。 The inter-processor communication control device 20 includes ports 200, 201,
202 and 203, a correspondence table storage unit 210 for knowing the correspondence between processor identifiers and ports, and a command buffer 220 for storing commands from each port.
この様に構成されたブロツク図でその動作につ
いて以下に説明する。 The operation will be explained below using the block diagram constructed in this way.
まず、システム立上げ時にプロセツサ識別子と
プロセツサ間通信制御装置20内のポート200
〜203との対応を示す対応表を対応表記憶部2
10に記憶させ、プロセツサ間通信制御装置21
及び22にも同様に記憶させておく。 First, when starting up the system, the processor identifier and the port 200 in the interprocessor communication control device 20 are
The correspondence table showing the correspondence with ~203 is stored in the correspondence table storage unit 2.
10, and the interprocessor communication control device 21
and 22 are also stored in the same way.
以上の準備を済ませた後に、プロセツサ10が
プロセツサ30に通信情報を送る必要が生じたな
らば、プロセツサ10は、通信先プロセツサ30
の識別子(今かりにid30とする)を付加した通信
コマンドを作成し、複数のプロセツサの構成を示
す構成テーブル120より複数ある通信線のうち
の一つの通信線100を選択して前記通信コマン
ドを出力する。この時、識別子付与部110で通
信コマンドにプロセツサ10の識別子(かりに
id10とする)を付与する。 After completing the above preparations, if it becomes necessary for the processor 10 to send communication information to the processor 30, the processor 10 sends the communication information to the communication destination processor 30.
Create a communication command with an identifier added (id30 for now), select one communication line 100 from the plurality of communication lines from the configuration table 120 showing the configuration of the plurality of processors, and output the communication command. do. At this time, the identifier assigning unit 110 adds the identifier of the processor 10 to the communication command.
id10).
前記通信コマンドがプロセツサ間通信制御装置
20に転送されると、プロセツサ間通信制御装置
20は通信コマンド内の通信先プロセツサ30の識
別子(id30)により対応表記憶部210を参照し、
通信先プロセツサ20が接続されているポート2
02を得て出力する。この時、ポート202がビ
ジーであれば、通信コマンドをコマンドバツフア
220に貯わえ、ビジー解除を待つ。また、障害
等で出力ができない場合には、通信元プロセツサ
10に障害ステータスを返す処理を行う。 When the communication command is transferred to the inter-processor communication control device 20, the inter-processor communication control device 20 refers to the correspondence table storage unit 210 using the identifier (id30) of the communication destination processor 30 in the communication command,
Port 2 to which the communication destination processor 20 is connected
Obtain and output 02. At this time, if the port 202 is busy, the communication command is stored in the command buffer 220 and waits for the port 202 to be released from the busy state. In addition, if output cannot be performed due to a failure etc., the communication source processor
Perform processing to return the failure status to 10.
ポート202から通信コマンドがプロセツサ30
に転送されると、プロセツサ30は、通信コマンド
で指示された動作を行い、その処理結果を通信元
プロセツサ10に返すために通信元プロセツサ10を
示す識別子(id10)を付加した通信コマンドを作
成し、複数のプロセツサの構成を示す構成テーブ
ル320より複数ある通信線のうちの一つの通信
線100を選択して前記通信コマンドを出力する。
この時、識別子付与部310で通信コマンドにプロ
セツサ30の識別子(id30)を付与する。以後は以
上で説明した流れと同様な処理を行つて通信コマ
ンドがプロセツサ10に転送される。 Communication commands from port 202 are sent to processor 30.
When the communication command is transferred, the processor 30 performs the operation instructed by the communication command, and creates a communication command with an identifier (id10) indicating the communication source processor 10 added in order to return the processing result to the communication source processor 10. , selects one communication line 100 from among the plurality of communication lines from a configuration table 320 showing the configuration of a plurality of processors, and outputs the communication command.
At this time, the identifier adding section 310 adds the identifier (id30) of the processor 30 to the communication command. Thereafter, the communication command is transferred to the processor 10 by performing the same process as explained above.
また、構成テーブル120を参照することによ
り、第1図にてプロセツサ10が通信線100〜102
のどの通信経路を選択しても目的のプロセツサ30
に通信コマンドを転送することができることを知
ることができるために、障害時の代替通信経路の
選択や負荷分散などの目的の通信経路の選択が容
易に行なえる。 Also, by referring to the configuration table 120, the processor 10 can connect the communication lines 100 to 102 in FIG.
No matter which communication route you choose, the target processor30
Since it is possible to know that communication commands can be transferred to the network, it is easy to select an alternative communication route in the event of a failure or to select a communication route for purposes such as load balancing.
さらに、通信コマンド送信時の通信経路とその
処理結果を示す通信経路が異なつていてもよいこ
とがわかる。 Furthermore, it can be seen that the communication path when transmitting a communication command and the communication path indicating the processing result may be different.
発明の効果
本発明には、以上説明した様に、プロセツサに
て通信経路を選択できる様なプロセツサ間通信方
式をとることにより、障害や負荷分散などによる
通信経路の選択が容易に行なえ、さらに応答経路
も自由に選択できるという効果がある。Effects of the Invention As explained above, the present invention has an inter-processor communication system in which a communication path can be selected by the processor. This has the effect of allowing you to freely choose your route.
第1図は本発明の一実施例を示す全体ブロツク
構成図、第2図は第1図に示したプロセツサ10及
び30とプロセツサ間通信制御装置20及びそれら
を結ぶ通信経路100及び300を示す部分ブロツク
図である。
10,11,30,31…プロセツサ、20,2
1,22…プロセツサ間通信制御装置、100〜10
5,300〜305…通信線、110,310…識別子付
与部、120,320…構成テーブル、200〜
203…ポート、210…対応表記憶部、220…
コマンドバツフア。
FIG. 1 is an overall block configuration diagram showing one embodiment of the present invention, and FIG. 2 is a portion showing the processors 10 and 30 shown in FIG. 1, the interprocessor communication control device 20, and the communication paths 100 and 300 connecting them. It is a block diagram. 10, 11, 30, 31...Processor, 20, 2
1, 22...Interprocessor communication control device, 100 to 10
5,300-305...Communication line, 110,310...Identifier assigning unit, 120,320...Configuration table, 200-
203... Port, 210... Correspondence table storage unit, 220...
Command batshua.
Claims (1)
な複数のプロセツサ間でデータ交換等のプロセツ
サ間通信を行う情報処理システムにおいて、プロ
セツサ間通信コマンドに発信元プロセツサ及び受
信元プロセツサを示すプロセツサ毎にユニークな
プロセツサ識別子を付与する手段を有するプロセ
ツサと、該プロセツサを接続可能なプロセツサポ
ートを複数個有し前記プロセツサポートの一つを
選択することが可能なプロセツサ間通信制御装置
と、前記プロセツサが自由に選択でき該プロセツ
サと前記プロセツサ間通信制御装置とを接続する
通信経路とを具備することを特徴としたプロセツ
サ間通信方式。1. In an information processing system that performs inter-processor communications such as data exchange between multiple processors that can be connected to multiple processor-to-processor communication control devices, the processor-to-processor communication command has a unique code for each processor that indicates the source processor and the receiving processor. a processor having a means for assigning a processor identifier; a processor-to-processor communication control device having a plurality of processor supports to which the processor can be connected and capable of selecting one of the processor supports; An inter-processor communication method, comprising: a communication path that connects the processor and the inter-processor communication control device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58242582A JPS60134369A (en) | 1983-12-21 | 1983-12-21 | Communication system between processors |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58242582A JPS60134369A (en) | 1983-12-21 | 1983-12-21 | Communication system between processors |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60134369A JPS60134369A (en) | 1985-07-17 |
| JPH0139141B2 true JPH0139141B2 (en) | 1989-08-18 |
Family
ID=17091202
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58242582A Granted JPS60134369A (en) | 1983-12-21 | 1983-12-21 | Communication system between processors |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60134369A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6371763A (en) * | 1986-09-16 | 1988-04-01 | Michio Araki | Adjusting device |
| JP2738338B2 (en) * | 1995-04-24 | 1998-04-08 | 日本電気株式会社 | Fault tolerant system |
-
1983
- 1983-12-21 JP JP58242582A patent/JPS60134369A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60134369A (en) | 1985-07-17 |
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