JPH0139219B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION This invention relates to improvements in analog integrated circuit devices.

Analog integrated circuit device (hereinafter referred to as “analog IC”)
That's what it means. ), and in particular for high-frequency applications, gallium arsenide (GaAs) substrates are widely used because their carrier mobility is large and suitable for high-frequency operation. Therefore, the explanation will be given below using a GaAs analog IC as an example. FIG. 1 shows an example of a conventional GaAs analog IC, FIG. 1a is a plan view thereof, and FIG. 1b is a sectional view taken along line B--B in FIG. 1a.

In the figure, 1 is a semi-insulating GaAs substrate, 2 is an n
3 is a source ohmic electrode, 4 is a drain ohmic electrode, 5 is a gate shot electrode, 6 is an input matching circuit, 7 is an output matching circuit, 8 is an input terminal, and 9 is an output terminal.

Next, the manufacturing method will be explained. Figure 2 a-c
FIG. 2 is a cross-sectional view showing the main process steps for explaining the conventional manufacturing method. First, as shown in FIG. 2a, silicon (Si) or the like is ion-implanted into a part of one main surface of the semi-insulating GaAs substrate 1 to form the n-type operating layer 2. As shown in FIG. Next, as shown in FIG. 2b, a source ohmic electrode 3, a drain ohmic electrode 4, and a gate shot electrode 5 are formed thereon to form a GaAs FET. (However, since FIG. 2b is a cross-sectional view, only the gate shot electrode 5 is shown.). Next, the second
As shown in FIG. It has an input terminal 8 and an output terminal 9.
GaAs analog IC is completed.

In such a conventional GaAs analog IC, the dielectric constant ε of the semi-insulating GaAs substrate 1 is about 12. If a transmission line corresponding to the wavelength λ _air in free space is formed as a distributed constant line on the GaAs substrate 1, its length, that is, the wavelength λ _g on the GaAs substrate 1, is approximately λ _air /√, In other words, it becomes approximately λ _air /3.5.
Therefore, the patterns of the input matching circuit 6 and output matching circuit 7 of the GaAs analog IC are designed based on this value, and the size of the GaAs analog IC chip is controlled by the size of this input/output matching circuit. I often put it away. In an actual GaAs analog IC that includes such a complex combination of matching circuits, in order to reduce the chip area for the purpose of high-density integration, it is desirable to reduce the size of the matching circuit section, which occupies a large portion of the area. Also, such GaAs
In analog ICs, it is desirable to maintain the planar structure of the main surface of the substrate in order to maintain good pattern accuracy of the matching circuit section.

The present invention has been made in view of the above points, and provides an analog integrated circuit that can maintain the planar structure of the substrate, maintain good pattern accuracy of an input/output matching circuit, and reduce the substrate area required for the matching circuit. The purpose is to provide a device.

An analog integrated circuit device according to the present invention is an analog integrated circuit device in which a semiconductor element is formed in the center of a main surface of a substrate, and input/output matching circuits are formed on both sides of the semiconductor element on the main surface. A recess is formed in the substrate below the matching circuit, an underlay metal layer is provided on the bottom of the recess, and a dielectric layer having a higher dielectric constant than the substrate is provided on the underlay metal layer to fill the recess, thereby increasing the capacitance. It is composed of

FIG. 3a is a plan view showing an embodiment of the present invention;
FIG. 3b is a cross-sectional view taken along line B-B, and its circuit configuration is the same as the conventional example shown in FIG.
Components equivalent to those of the conventional example shown in FIG. 1 are designated by the same reference numerals. In the figure, 10 and 11 are a high dielectric constant dielectric layer and a metal layer, respectively, which are provided by removing a portion of the semi-insulating GaAs substrate 1 below the input matching circuit 6 and the output matching circuit 7.

The manufacturing method will be explained below. Figure 4 a-g
FIG. 2 is a cross-sectional view showing the main process steps for explaining the manufacturing method of this embodiment. The steps shown in FIGS. 4a and 4b are exactly the same as those shown in FIGS. An ohmic electrode 3, a drain ohmic electrode 4, and a gate shot electrode 5 are formed to
A FET is configured (only the gate shot electrode 5 is shown in FIG. 4). Next, Figure 4c
As shown in the figure, a resist film 12 with a thickness of several μm is formed on the GaAs FET and its surrounding area.
Using this as a mask, the rest of the semi-insulating GaAs
A recess 13 is formed by etching the main surface of the substrate 1 to a depth of several μm. Next, as shown in FIG. 4d, the resist film 12 is removed from the bottom of the recess 13.
Chromium-gold (Cr-Au) alloy layer 1
1 and a barium titanate (BaTiO ₃ ) layer 10 are formed by continuous sputtering so that the total thickness of both layers 11 and 10 is approximately equal to the depth of the recess 13. Next, as shown in FIG. 4e, the resist film 1
2 and the Cr/Au alloy layer 11 and BaTiO ₃ thereon.
The resist film 14 is removed together with the layer 10, and a resist film 14 is formed on the surface after the removal, leaving both ends thereof.
Next, as shown in _FIG . (including)
A metal layer 16 is formed by plating a nickel-gold (Ni-Au) alloy or gold (Au). This metal layer 1
6 is electrically connected to the Cr-Au alloy layer 11. Finally, as shown in FIG. 4g, after removing the resist film 14, the input matching circuit 6 and the output matching circuit 7 are formed in the same manner as in the step of FIG. 2c in the conventional example. The example device is completed. In addition, in FIG. 3, the metal layer 16 is omitted for simplicity.

In this embodiment formed in this way, the input matching circuit 6 and the output matching circuit 7 are formed on the BaTiO ₃ layer 10 having a high dielectric constant, and the base layer 10 is made of Cr.
By keeping the Au alloy layer 11 at ground potential,
The BaTiO ₃ layer 10 can be considered as the substrate for this part. Since the dielectric constant ε of this substrate is a high value of about 37, the pattern shape of both matching circuits 6 and 7 having a distributed constant circuit configuration can be made small. .
As mentioned earlier, the size is inversely proportional to √, so the size can be reduced to about half that of the conventional case where it is formed on a GaAs substrate.

In the above embodiment, BaTiO ₃ is used as a dielectric having a high dielectric constant, but the present invention is not limited to this. Further, although the case where a GaAs FET is formed on the active layer is shown, this may be a Schottky diode or other semiconductor element. The substrate is not limited to GaAs either. Furthermore, the explanation has been made with the aim of reducing the pattern area of an input/output matching circuit with a distributed constant circuit configuration, but even when forming a lumped constant capacitive element such as a parallel plate capacitor, it is possible to reduce the electrode area of the capacitive element. It can be applied to

As detailed above, according to the analog integrated circuit device of the present invention, a recess is formed in the substrate at least below the input/output matching circuit, an underlay metal layer is provided on the bottom surface of the recess, and the recess is formed on the underlay metal layer. A dielectric layer having a higher dielectric constant than the substrate is provided to fill up the capacitance, so that the pattern accuracy of the matching circuit can be maintained well, and the substrate area required for the matching circuit can be reduced. This has the effect of reducing the area of the IC chip and improving the degree of integration.

[Brief explanation of drawings]

Figure 1a is a plan view showing an example of a conventional GaAs analog IC, Figure 1b is a sectional view taken along line B-B in Figure 1a, and Figures 2a to c illustrate the manufacturing method of this conventional example. 3A is a plan view showing an embodiment of the present invention; FIG. 3B is a sectional view taken along line B-B in FIG. 3A; Figures 4a to 4g are cross-sectional views showing the main process steps for explaining the manufacturing method of the above embodiment. In the figure, 1 is a semi-insulating GaAs substrate (substrate),
2 is an n-type active layer (semiconductor element forming part), 4 is a drain ohmic electrode, 5 is a gate shot electrode, 6 and 7 are matching circuits (passive elements), 10 is a barium titanate layer (dielectric layer), 11 is a Cr-Au alloy layer (underlying metal layer), 13 is a recessed portion. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Scope of Claims] 1. An analog integrated circuit device in which a semiconductor element is formed in the center of one main surface of one substrate, and input/output matching circuits are formed on both sides of the semiconductor element on the main surface, A recess is formed in the substrate below the input/output matching circuit, an underlay metal layer is provided on the bottom of the recess, a dielectric layer having a higher dielectric constant than the substrate is provided on the underlay metal layer to fill the recess, and electrical An analog integrated circuit device comprising a capacitor. 2. The analog integrated circuit device according to claim 1, wherein the substrate is made of semi-insulating gallium arsenide, and the dielectric layer is made of barium titanate. 3. The semiconductor element is a gallium arsenide field effect transistor, and the input/output matching circuit is connected to the gate and drain of the transistor, respectively. The analog integrated circuit device described in Section 1.