JPH0140504B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a semiconductor memory device in which charges are accumulated by a charge pump action, and the resulting change in threshold voltage of a transistor corresponds to information "1" or "0". .

The present inventor has previously discovered that charge pumping
A semiconductor storage device called a memory as shown in FIG. 1 was provided.

In the figure, 1 is a single-crystal insulating substrate such as sapphire, 2 is an n ⁺ type silicon semiconductor layer that acts as a buffer layer for good epitaxial growth, 3 is a p-type silicon semiconductor layer, and 4 is carbon dioxide. A silicon insulation separation layer, 5 a gate insulating film, 6 an n ⁺ type polycrystalline silicon gate electrode, 7 and 8 a p ⁺ type shielding region, 9 an n ⁺ type source region, and 10 an n ⁺ type drain region, respectively. show.

In this device, a voltage is applied between the source region 9 and the drain region 10, and when a voltage is also applied to the gate electrode 6, a channel is formed and a current flows. Then, when the potential of the gate electrode 6 is suddenly reduced to zero, electrons are injected into the p-type silicon semiconductor layer 3 and negative charges are accumulated therein. As a result, the threshold voltage in the current path from source region 9 to drain region 10 changes. Therefore, by sensing the change in this threshold voltage, it is possible to read whether information has been written.

By the way, since the substrate 1 of the device is made of sapphire, it is extremely expensive compared to a silicon substrate, and the silicon semiconductor layer epitaxially grown thereon is also of insufficient quality.

Therefore, an improved device as shown in FIG. 2 was provided.

In the figure, 11 is an n-type silicon semiconductor substrate;
12 is a silicon dioxide insulating film for the field, 13
14 is a p-type well, 14 is a recombination center region, 15 is a gate insulating film, 16 is an n ⁺ type polycrystalline silicon gate electrode, 17 is an n ⁺ type source region, and 18 is an n ⁺ type drain region.

The difference between this device and the device shown in FIG. 1 is that the substrate 1
1 is a silicon semiconductor, and p is in the substrate 11.
The type well 13 is formed and charge is accumulated therein. This charge accumulation is caused by the charge pumping effect when electrons injected into the p-type well 13 become holes in the recombination center region 14. As a result, the number of holes in the p-type well 13 decreases, and as a result, charges are accumulated. However, when the recombination center region 14 is formed in this way, the p-type well 13
This also leads to the possibility that the charges accumulated within the capacitor tend to leak, making it impossible to accumulate charges for a long period of time.

The present invention uses a silicon semiconductor substrate, which is cheaper than a single crystal insulating substrate such as sapphire, and has good charge storage properties, and will be described in detail below.

FIG. 3 is an explanatory sectional view of a main part of an embodiment of the present invention.

In the figure, 21 is an n-type silicon semiconductor substrate;
22 is a silicon dioxide insulating film for the field, 23
is a p ⁺ type shielding region, 24 is an n-type charge trapping region, 2
5 is a p-type well, 26 is a gate insulating film, and 27 is a p-type well.
n ⁺ type polycrystalline silicon gate electrode, 28, 29
is a p ⁺ type shielding region, 30 is an n ⁺ type source region, 31
3 is an n ⁺ type drain region, 32 is a phosphosilicate glass insulating film, 33 is a source electrode, and 34 is a drain electrode.

In this embodiment, there is no recombination center region as seen in FIG. 2, but instead an n-type charge trapping region 24 is formed that covers the bottom surface of the p-type well 25. Therefore, electrons injected into the p-type well 25 due to the charge pumping effect are trapped in the n-type charge trapping region 24, and leakage is extremely reduced.
That is, by applying a voltage to the gate electrode 27, electrons charge-pumped into the p-type well 25 from the inversion layer generated between the source region 30 and the drain region 31 are transferred to a low-potential n-type charge trapping region. 24, and as a result,
Since the n-type charge trapping region 24 and the p-type well 25 are biased in the forward direction, they have the same potential if the rise of the p-n junction diode is ignored. This means that not only the n-type charge trapping region 24 but also the p-well 25 will be negatively biased, and therefore the threshold voltage in the current path between the source region 30 and the drain region 31 will change. . Therefore, this change should be made to correspond to the information "1" and "0" as in the conventional device.

The manufacturing of the above embodiment is easy; for example, the p ⁺ type shielding region 23, the n-type charge trapping region 24, and the p-type well 25 are formed by forming the silicon dioxide insulating film 22 for the field.
It can be formed by ion implantation and diffusion using a mask, and the other parts are almost the same as the process for forming a normal MIS field effect transistor. Next, specific numerical examples of this example will be given.

Thickness of insulating film 22: 6000 [Å] Thickness of region 23: 3000 [Å] Impurity concentration of region 23: 2×10 ¹⁶ [cm ^-3 ] Thickness of region 24: 3000 [Å] Impurity of region 24 Concentration: 4×10 ¹⁵ [cm ^-3 ] Region depth: 1 [μm] Impurity concentration in region 25: 1×10 ¹⁶ [cm ^-3 ] Thickness of insulating film 26: 400 [Å] Thickness of electrode 27 Thickness of regions 28 and 29: 3000 [Å] Impurity concentration of regions 28 and 29: 2×10 ¹⁶ [cm ^-3 ] Depth of regions 30 and 31: 3000 [Å] Region 30, Impurity concentration of 31: 1×10 ^{20 to 21} [cm ^-3 ] As can be seen from the above explanation, according to the present invention, the well where charges are injected from the channel generated between the source region and the drain region. A charge trapping region of the opposite conductivity type to that of the well is formed on the lower surface, and the lower surface is further covered with a shielding region of the same conductivity type as the well, so that even though an inexpensive semiconductor is used as the substrate, accumulated charges can be prevented. leakage can be extremely reduced.

[Brief explanation of drawings]

Figures 1 and 2 are cross-sectional explanatory diagrams of main parts of the conventional example;
FIG. 3 is an explanatory sectional view of a main part of an embodiment of the present invention. In the figure, 21 is a substrate, 22 is an insulating film, and 23
24 is a shielding region, 24 is a charge trapping region, 25 is a well, 26 is a gate insulating film, 27 is a gate electrode, 2
8 and 29 are shield regions, 30 is a source region, and 31 is a drain region.

Claims (1)

[Claims] 1. An electrically floating well of an opposite conductivity type is formed in a semiconductor substrate of one conductivity type, and charge is generated from an inversion layer generated between regions of one conductivity type formed oppositely in the well. In a semiconductor memory device of the type in which charges are injected into a well by a pump action and a threshold voltage is varied to generate an inversion layer between the regions of one conductivity type, charge trapping of one conductivity type covers the bottom surface of the well. What is claimed is: 1. A semiconductor memory device comprising a region and a shielding region of an opposite conductivity type covering a lower surface of the charge trapping region.