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JPH0140515B2 - - Google Patents
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JPH0140515B2 - - Google Patents

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Publication number
JPH0140515B2
JPH0140515B2 JP55110095A JP11009580A JPH0140515B2 JP H0140515 B2 JPH0140515 B2 JP H0140515B2 JP 55110095 A JP55110095 A JP 55110095A JP 11009580 A JP11009580 A JP 11009580A JP H0140515 B2 JPH0140515 B2 JP H0140515B2
Authority
JP
Japan
Prior art keywords
layer
thickness
resistor
hybrid integrated
resistance value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55110095A
Other languages
Japanese (ja)
Other versions
JPS5735364A (en
Inventor
Shinji Yoshida
Giichi Saito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP11009580A priority Critical patent/JPS5735364A/en
Publication of JPS5735364A publication Critical patent/JPS5735364A/en
Publication of JPH0140515B2 publication Critical patent/JPH0140515B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/80Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple passive components, e.g. resistors, capacitors or inductors
    • H10D86/85Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple passive components, e.g. resistors, capacitors or inductors characterised by only passive components

Landscapes

  • Parts Printed On Printed Circuit Boards (AREA)
  • Apparatuses And Processes For Manufacturing Resistors (AREA)

Description

【発明の詳細な説明】 本発明は薄膜混成集積回路、特に膜形成された
抵抗体の化成電圧を一定化させる手段に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a thin film hybrid integrated circuit, and more particularly to means for making constant the formation voltage of a film-formed resistor.

セラミツク等よりなる薄膜混成集積回路基板に
形成された抵抗体の低抗値は、膜形成技術のみに
よつて高精度に制御することが困難であるため、
回路内で正確な抵抗値が要求されるときは抵抗膜
の一部を除去する物理的方法、又はパターン形状
を変えることなく有効厚さを調整する電気化学的
方法によるトリミングが施されている。特にタン
タル系混成集積回路では化成トリミング、即ち、
例えば回路基板上に被着した窒化タンタル(Ta
−N)膜を選択的にエツチングして抵抗体パター
ンを形成し、該パターン表面に所定厚さの酸化タ
ンタル(Ta2O3)膜を化成形成せしめて、Ta−
N膜の厚さを減少させることにより所要の抵抗値
を得る方法が広く用いられている。しかし、前記
化成トリミングにおいて1つ回路基板上に形成さ
れる複数のタンタル系抵抗体、特に海底中継器等
に使用される混成集積回路の如く、大型基板に数
10個〜数100個形成される高信頼・高精度の抵抗
体は、回路設計上のパターン形状及び抵抗値がそ
れぞれ多種類となり、かつ、Ta−N膜厚の製造
ロツト間ばらつきをも考慮する必要がある。その
ため、従来は抵抗体抵抗値に対してほぼ一定率に
設計された各抵抗体パターンの抵抗値を計測した
のち、該計測値に基づく所要厚さのTa2O5膜が形
成される化成電圧(例えば15Å/V)をそれぞれ
負荷するようにしていた。従つて、多種類の化成
電圧を要するのみならず、化成長さの短かい低抗
抗体パターン化成電圧は高められて約130V以上
になると、Ta2O5(誘導体)膜が破壊されること
があつた。
It is difficult to control the low resistance value of resistors formed on thin film hybrid integrated circuit boards made of ceramics etc. with high precision using only film formation technology.
When an accurate resistance value is required in a circuit, trimming is performed by a physical method that removes a portion of the resistive film, or by an electrochemical method that adjusts the effective thickness without changing the pattern shape. Particularly in tantalum-based hybrid integrated circuits, chemical trimming, that is,
For example, tantalum nitride (Ta) deposited on a circuit board.
-N) film is selectively etched to form a resistor pattern, and a tantalum oxide (Ta 2 O 3 ) film of a predetermined thickness is chemically formed on the surface of the pattern.
A method of obtaining a desired resistance value by reducing the thickness of the N film is widely used. However, in the chemical trimming process, a plurality of tantalum-based resistors are formed on one circuit board, and in particular, a large number of tantalum resistors are formed on a large board, such as a hybrid integrated circuit used in submarine repeaters.
Highly reliable, high-precision resistors that are formed in numbers of 10 to several 100 pieces have a wide variety of pattern shapes and resistance values in circuit design, and also take into account variations in Ta-N film thickness between manufacturing lots. There is a need. Therefore, in the past, after measuring the resistance value of each resistor pattern, which was designed to be approximately constant with respect to the resistor resistance value, the formation voltage at which a Ta 2 O 5 film of the required thickness was formed was determined based on the measured value. (for example, 15 Å/V). Therefore, not only many types of formation voltages are required, but also the Ta 2 O 5 (derivative) film may be destroyed if the formation voltage for low anti-antibody patterns with short chemical growth is increased to about 130V or higher. It was hot.

本発明の目的は上記問題点を除去することであ
り、この目的は化成トリミング手段により複数の
抵抗体を形成してなる薄膜混成集積回路におい
て、各抵抗体パターンの従来幅wと従来長さl及
びその被着厚さtのうち、少なくとも何れか1つ
を調整し、各種定数の前記各抵抗体パターン化成
電圧を一定化せしめてなることを特徴とした薄膜
混成集積回路を提供して達成される。
An object of the present invention is to eliminate the above-mentioned problems, and the object is to provide a thin film hybrid integrated circuit in which a plurality of resistors are formed by chemical trimming means, in which each resistor pattern has a conventional width w and a conventional length l. The present invention is achieved by providing a thin film hybrid integrated circuit characterized in that at least one of the above and the adhesion thickness t is adjusted to make the resistor pattern formation voltages of various constants constant. Ru.

以下図面を用いて本発明を説明する。 The present invention will be explained below using the drawings.

第1図は薄膜混成集積回路基板上に膜形成され
た抵抗体の一例を示す平面図aとその断面図bで
あり、図中において1はセラミツク等よりなる回
路基板、2は基板1の上に被着形成された窒化タ
ンタル(Ta−N)層、3はタンタル化成
(Ta2O5)層、4はTa−N層2の両端部にそれぞ
れ積層形成されたニクロム(NiCr)層、5は各
NiCr層4の上に積層形成された金(Au)電極層
を示す。ただし、NiCr層4はTa−N層2とAu
電極層5との接着媒体として設けたものである。
このように構成された抵抗体6の抵抗値Rは、対
向する電極層5間のTa−N層2長さlと幅wと
厚t、及び通常は前記Ta−N層2の全幅wにわ
たつて形成されるTa2O5層3の長さl′と、Ta2O5
層3によつて減じられた部分のTa−N層厚さ
t′によつて決定される。なお、一般にTa2O5層長
さl′はTa−N層長さlより少し短く、かつ、両端
部が電極層5から少し離れるようにして、化成レ
ジスト形成用マスクの位置が多少ずらされるよう
なことがあつても、正確なTa2O5層長さl′が得ら
れるようにしてある。また、化成電圧Vによつて
厚さ制御されるTa2O5層3は、その厚さの約1/3
量だけTa−N層2の厚tを減じて、Ta2O5層3
のTa−N層厚さt′が構成される。
FIG. 1 is a plan view (a) and a cross-sectional view (b) showing an example of a resistor film formed on a thin film hybrid integrated circuit board. 3 is a tantalum chemical (Ta 2 O 5 ) layer; 4 is a nichrome (NiCr) layer laminated on both ends of the Ta-N layer 2; is each
A gold (Au) electrode layer laminated on the NiCr layer 4 is shown. However, NiCr layer 4 is Ta-N layer 2 and Au
It is provided as an adhesive medium with the electrode layer 5.
The resistance value R of the resistor 6 configured in this way is determined by the length l, width w, and thickness t of the Ta-N layer 2 between the opposing electrode layers 5, and usually the total width w of the Ta-N layer 2. The length l′ of the Ta 2 O 5 layer 3 formed across the Ta 2 O 5
Ta-N layer thickness reduced by layer 3
determined by t′. In general, the Ta 2 O 5 layer length l' is slightly shorter than the Ta-N layer length l, and the position of the chemical resist forming mask is shifted slightly so that both ends are slightly separated from the electrode layer 5. Even if such a situation occurs, it is possible to obtain an accurate Ta 2 O 5 layer length l'. Furthermore, the Ta 2 O 5 layer 3 whose thickness is controlled by the formation voltage V has a thickness of about 1/3 of that thickness.
By reducing the thickness t of Ta-N layer 2 by the amount, Ta 2 O 5 layer 3
A Ta-N layer thickness t' is formed.

即ち、Ta−N層の比低抗をρとした抵抗値R
は広く知られているように R=ρ・(l−l′)/w・t+ρ・l′/
w・t′=ρ/w・{(l−l′)/t+l′/t′} となる。そして、抵抗値Rに対する厚さt′は、従
来化成電圧Vで調整する1つの変数として取扱つ
ていたのに対し、本発明に係わる1つの手段は従
来の抵抗値R設定寸法に基づき厚さt′を定数化し
て、抵抗値Rを幅wと長さlで補正することであ
る。即ち、基板1の上にTa−N層を一様厚さt
で被着したのち、エツチング手段で複数の各種形
状を有する各抵抗体パターンを形成するのに際
し、パターン幅wとパターン長さlは、何れか一
方又は相方を従来寸法より多少増減させて補正調
整することにより厚さt′が定数化し、各抵抗体パ
ターンの化成電圧Vは一定化されるようになる。
ただし、この場合において抵抗体パターン抵抗値
と化成後の抵抗体値との比率は抵抗体形体によつ
て異なるようになる。
That is, the resistance value R with the specific resistance of the Ta-N layer as ρ
As is widely known, R=ρ・(l−l′)/w・t+ρ・l′/
w・t′=ρ/w・{(l−l′)/t+l′/t′}. While the thickness t' with respect to the resistance value R has conventionally been treated as one variable that is adjusted by the formation voltage V, one means related to the present invention is to adjust the thickness t' based on the conventional resistance value R setting dimension. The purpose is to make t' a constant and correct the resistance value R by the width w and length l. That is, a Ta-N layer is formed on the substrate 1 to a uniform thickness t.
When forming each resistor pattern having a plurality of various shapes using etching means, the pattern width w and the pattern length l are corrected and adjusted by slightly increasing or decreasing one or the other from the conventional dimensions. By doing so, the thickness t' becomes constant, and the formation voltage V of each resistor pattern becomes constant.
However, in this case, the ratio between the resistance value of the resistor pattern and the value of the resistor after chemical formation differs depending on the shape of the resistor.

他方、各抵抗パターン抵抗値を化成トリミング
前に計測した結果、製造ロツト間ばらつき等によ
りパターン厚さtが所期値より大きいことがあ
る。その場合、化成後の抵抗体厚さt′を変数とす
る従来の考え方では、化成電圧Vが誘電体
(Ta2O5)層破壊電圧(約130V)近くなるものを
主対象としたところの本発明に係わる他の手段
を、第2図a〜dの一実施例における主要工程説
明図に示す。
On the other hand, as a result of measuring the resistance value of each resistor pattern before chemical trimming, the pattern thickness t may be larger than the expected value due to variations between manufacturing lots. In that case, the conventional concept of using the resistor thickness t' after formation as a variable is that the formation voltage V is close to the dielectric (Ta 2 O 5 ) layer breakdown voltage (approximately 130 V). Other means related to the present invention are shown in the main process explanatory diagrams in one embodiment of FIGS. 2a to 2d.

第2図aにおいて、薄膜混成集積回路基板11
の上には従来手段により窒化タンタル(Ta−N)
層12とニクロム(NiCr)層13と金(Au)電
極層14とが所定に積層形成される。次にで第2
図bに示す如く、少なくとも電極層14を被覆、
かつ、対向する電極層14間のTa−N層12が
露出するように、レジスト層15を被着したのち
該露出するTa−N層12の表面を弗化水素
(HF)水溶液等にてエツチングする。ただし、
前記エツチング量はその部分を化成する時の負荷
電圧が、130V以下となる値とする。次いで第2
図cに示す如く、前記エツチング部分に化成処理
を施して化成(Ta2O5)層16を形成したのち、
レジスト層15を除去して第2図dに示す抵抗体
17が完成する。
In FIG. 2a, a thin film hybrid integrated circuit board 11
Tantalum nitride (Ta-N) is deposited on top by conventional means.
A layer 12, a nichrome (NiCr) layer 13, and a gold (Au) electrode layer 14 are laminated in a predetermined manner. Next in the second
As shown in FIG. b, covering at least the electrode layer 14,
After depositing a resist layer 15 so that the Ta-N layer 12 between the opposing electrode layers 14 is exposed, the surface of the exposed Ta-N layer 12 is etched with a hydrogen fluoride (HF) aqueous solution or the like. do. however,
The amount of etching is such that the load voltage when forming the part is 130V or less. Then the second
As shown in FIG .
The resist layer 15 is removed to complete the resistor 17 shown in FIG. 2d.

なお、上記本発明の説明において、本発明に係
わる1つの手段と他の手段に分けてあるが、該手
段はそれぞれ断立してのみ適用されるものではな
く、前記1つの手段と前記他の手段の相方を1つ
薄膜混成集積回路の作成に適用することができ
る。また、前記他の手段は、1つ回路基板上に形
成された複数の抵抗体パターンのうちの一部の
み、又は一部を残して適用できることは明白であ
る。
In the above description of the present invention, the present invention is divided into one means and other means, but each means is not applied exclusively to each other, and the one means and the other means are not applied exclusively to each other. One companion of the means can be applied to the creation of thin film hybrid integrated circuits. Furthermore, it is obvious that the other means described above can be applied to only some of the plurality of resistor patterns formed on one circuit board, or to all remaining parts.

以上説明した本発明によれば、膜抵抗体を化成
トリミングするのに際し、負荷電圧を誘電体層破
壊電圧以下にすることを可能ならしめるため、そ
の製造歩留りを向上させるのみならず、前記誘電
体層の信頼性を高め得た実用上の効果が顕著であ
る。
According to the present invention as described above, when chemically trimming a film resistor, it is possible to reduce the load voltage to below the breakdown voltage of the dielectric layer, which not only improves the manufacturing yield but also The practical effect of increasing the reliability of the layer is remarkable.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明に係れる1つの手段を説明する
ための膜抵抗体を示す平面図aとその断面図b、
第2図は本発明に係わる他の手段を説明するため
の主要工程図である。 なお、図において2,12は窒化タンタル(抵
抗)層、3,12は化成(Ta2O5)層、5,14
は金(Au)電極層、6,17は抵抗体を示す。
FIG. 1 is a plan view a showing a membrane resistor and a cross-sectional view b thereof for explaining one means according to the present invention.
FIG. 2 is a main process diagram for explaining another means related to the present invention. In the figure, 2 and 12 are tantalum nitride (resistance) layers, 3 and 12 are chemical conversion (Ta 2 O 5 ) layers, and 5 and 14 are tantalum nitride (resistance) layers.
indicates a gold (Au) electrode layer, and 6 and 17 indicate resistors.

Claims (1)

【特許請求の範囲】[Claims] 1 化成トリミング手段により複数の抵抗体を形
成してなる薄膜混成集積回路において、各抵抗体
パターンの従来幅wと従来長さl及びその被着厚
さtのうち、少なくとも何れか1つを調整し、各
種定数の前記各抵抗体パターン化成電圧を一定化
せしめてなることを特徴とした薄膜混成集積回
路。
1. In a thin film hybrid integrated circuit in which a plurality of resistors are formed by chemical trimming means, at least one of the conventional width w, conventional length l, and deposition thickness t of each resistor pattern is adjusted. A thin film hybrid integrated circuit characterized in that the resistor pattern forming voltages of various constants are made constant.
JP11009580A 1980-08-11 1980-08-11 Thin film hybrid integrated circuit Granted JPS5735364A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11009580A JPS5735364A (en) 1980-08-11 1980-08-11 Thin film hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11009580A JPS5735364A (en) 1980-08-11 1980-08-11 Thin film hybrid integrated circuit

Publications (2)

Publication Number Publication Date
JPS5735364A JPS5735364A (en) 1982-02-25
JPH0140515B2 true JPH0140515B2 (en) 1989-08-29

Family

ID=14526896

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11009580A Granted JPS5735364A (en) 1980-08-11 1980-08-11 Thin film hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPS5735364A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02324A (en) * 1987-12-18 1990-01-05 Mitsui Mining & Smelting Co Ltd Conducting film circuit and its manufacture
JPH05109925A (en) * 1991-10-18 1993-04-30 Kyocera Corp Thin-film wiring board

Also Published As

Publication number Publication date
JPS5735364A (en) 1982-02-25

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