JPH0141243B2 - - Google Patents
Info
- Publication number
- JPH0141243B2 JPH0141243B2 JP58101076A JP10107683A JPH0141243B2 JP H0141243 B2 JPH0141243 B2 JP H0141243B2 JP 58101076 A JP58101076 A JP 58101076A JP 10107683 A JP10107683 A JP 10107683A JP H0141243 B2 JPH0141243 B2 JP H0141243B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- chips
- solder layer
- electronic component
- solder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Description
【発明の詳細な説明】
(a) 発明の技術分野
本発明はプリント板等にフエースボンデイング
で搭載する電子部品、特にアルミニウム固体電解
コンデンサやタンタル固体電解コンデンサの製造
方法に関し、具体的にはチツプ型電子部品の電極
パツド面に外部に外部接続用の金属層をはんだ付
けし、この金属層を除く電子部品外周面を絶縁性
樹脂で被覆する方法に関する。[Detailed Description of the Invention] (a) Technical Field of the Invention The present invention relates to a method for manufacturing electronic components mounted on printed boards etc. by face bonding, particularly aluminum solid electrolytic capacitors and tantalum solid electrolytic capacitors. The present invention relates to a method of soldering a metal layer for external connection to the electrode pad surface of an electronic component and covering the outer peripheral surface of the electronic component except for this metal layer with an insulating resin.
(b) 技術の背景
この種の製造方法には、基板にはんだ層を一面
に形成し、そのはんだ層にはチツプ型電子部品素
子を配置してその陽極パツド面と陰極パツド面と
をはんだ層の面に接触せしめ、次いではんだ層の
加熱溶融により各パツド面を半田層に固着せし
め、次いでこの固着状態においてモールド成形に
より絶縁性樹脂を固着部を除く電子部品素子の外
面に被覆し、最後にはんだ層を加熱溶融して電子
部品素子を基板から分離し、それによつてパツド
面にはんだ層が形成されるとともにパツド面を除
く部分が樹脂被覆された電子部品を完成する方法
があつた。(b) Background of the technology This type of manufacturing method involves forming a solder layer all over the board, placing a chip-type electronic component element on the solder layer, and connecting the anode pad surface and cathode pad surface with the solder layer. Then, each pad surface is fixed to the solder layer by heating and melting the solder layer. Then, in this fixed state, insulating resin is coated on the outer surface of the electronic component element except the fixed part by molding, and finally, There was a method of heating and melting the solder layer to separate the electronic component element from the substrate, thereby forming a solder layer on the pad surface and completing an electronic component in which the parts other than the pad surface were coated with resin.
しかし、この方法にて一度に多数個の電子部品
を完成させる場合、モールド金型との関係から基
板に電子部品を配置する際の位置合せが要求さ
れ、該位置合せは技術的及び作業的に厄介であつ
た。 However, when completing a large number of electronic components at once using this method, alignment is required when placing the electronic components on the board due to the relationship with the mold, and this alignment is technically and operationally difficult. It was troublesome and hot.
そこで本出願人は、昭和49年3月4日に出願し
昭和56年8月14日に公告された「電子部品の製造
方法」(特公昭56―35020)を実施するようになつ
た。 Therefore, the present applicant began implementing the "Method for Manufacturing Electronic Components" (Japanese Patent Publication No. 1983-35020), which was filed on March 4, 1972 and published on August 14, 1981.
(c) 従来技術と問題点
上記公告された「電子部品の製造方法」は、基
板に電子部品素子を多数個配置する位置決めを容
易化した方法であり、電子部品素子の陽極パツド
及び陰極パツドにそれぞれ対応する凹所を基板に
複数組配設し、各凹所にはんだチツプを配置した
のち、各1対の半田チツプに各電子部品素子の陽
極パツドと陰極パツドとが着座するように基板の
表面の電子部品素子群を載置する。次いで、前記
はんだチツプを一時的に加熱溶融して基板と電子
部品素子とをはんだ付け固定し、その状態でモー
ルドイン成形により各電子部品素子に絶縁樹脂の
外装体を被覆したのち、はんだチツプを再加熱し
て外装電子部品素子群を基板から引離す方法であ
る。(c) Prior art and problems The above-announced "method for manufacturing electronic components" is a method that facilitates the positioning of a large number of electronic component elements on a board. After arranging multiple sets of corresponding recesses on the board and placing solder chips in each recess, the board is adjusted so that the anode pad and cathode pad of each electronic component element are seated on each pair of solder chips. A group of electronic component elements on the front surface is placed. Next, the solder chips are temporarily heated and melted to solder and fix the board and electronic component elements, and in this state, each electronic component element is covered with an insulating resin exterior by mold-in molding, and then the solder chips are This is a method of reheating and separating the packaged electronic component element group from the board.
しかし、このような方法及び技術の背景で説明
した旧来の方法にて完成された電子部品に共通す
る欠点は、陽極パツド及び陰極パツドに被着形成
された層の表面が凹凸であり、該電子部品をプリ
ント板等に搭載するに先立つて、該凹凸を平滑化
する処理が必要になる場合があつたことである。 However, a common drawback of electronic components completed using the traditional methods explained in the background of these methods and techniques is that the surfaces of the layers deposited on the anode and cathode pads are uneven, and the electronic components There have been cases where it has been necessary to smooth out the unevenness before mounting the component on a printed board or the like.
(d) 発明の目的
本発明の目的は、上記問題点を改良した電子部
品の製造方法を提供することである。(d) Object of the invention An object of the invention is to provide a method for manufacturing electronic components that improves the above-mentioned problems.
(e) 発明の構成
上記目的は、1対の凹所が表面に複数組配設さ
れている基板の該凹所にはんだ付け可能な金属層
とはんだ層を積層したチツプを該はんだ層が上に
なるように配置し、各該1対のチツプに各電子部
品素子のはんだ付け可能な陽極パツド面と陰極パ
ツド面とがそれぞれ着座するように該基板の表面
に該素子群を載置し、該はんだ層を一時的に加熱
溶融して該素子に該チツプを融着したのちモール
ドイン成形により各該素子に電気絶縁樹脂の外装
体を被覆し、該チツプが融着された該外装素子群
を該基板から引離すことを特徴とする電子部品の
製造方法により達成される。(e) Structure of the Invention The above object is to produce a chip in which a metal layer and a solder layer that can be soldered to the recesses of a board having a plurality of pairs of recesses arranged on the surface thereof are laminated with the solder layer on top of the chip. placing the elements on the surface of the substrate so that the solderable anode pad surface and cathode pad surface of each electronic component element are respectively seated on each pair of chips; The solder layer is temporarily heated and melted to fuse the chip to the element, and then each element is covered with an electrically insulating resin exterior body by mold-in molding, and the group of exterior elements to which the chip is fused is formed. This is achieved by a method of manufacturing an electronic component, which is characterized by separating the substrate from the substrate.
(f) 発明の実施例
以下、図面を用いて本発明方法の実施例を説明
する。(f) Examples of the invention Examples of the method of the present invention will be described below with reference to the drawings.
第1図は電子部品素子例えばアルミニウム固体
電解コンデンサ素子と本発明に係わるチツプを示
す斜視図、第2図は本発明の一実施例に係わる基
板の平面図、第3図は第2図の―線の斜視断
面図、第4図は前記基板を用いて前記素子に外装
を被覆した断面図、第5図は前記素子に外装を被
覆したコンデンサの完成品を示す斜視図である。 FIG. 1 is a perspective view showing an electronic component element such as an aluminum solid electrolytic capacitor element and a chip according to the present invention, FIG. 2 is a plan view of a substrate according to an embodiment of the present invention, and FIG. FIG. 4 is a cross-sectional view of the element covered with an exterior using the substrate, and FIG. 5 is a perspective view of a completed capacitor in which the element is coated with an exterior.
第1図において、11はコンデンサ素子10の
本体から延長した陽極線であり、その尖端にはは
んだ付け可能な金属片12が溶接され、この金属
片12の図示下面が陽極パツド面12aを提供
し、素子10の前記本体には、はんだ層13が被
覆されており、このはんだ層13の図示下面が陰
極パツド面13aを提供している。 In FIG. 1, 11 is an anode wire extending from the main body of the capacitor element 10, and a solderable metal piece 12 is welded to the tip of the anode wire, and the lower surface of this metal piece 12 in the drawing provides an anode pad surface 12a. The main body of the element 10 is coated with a solder layer 13, and the lower surface of the solder layer 13 in the drawing provides a cathode pad surface 13a.
第2図及び第3図において、基板20は平担面
を有する金属基台21とその上に固着された孔付
き板22から構成されており、基台21と孔付き
板22ははんだ付け性のよくない金属、又ははん
だ付け性のよくない表面処理を施してある方がよ
い。また基板20は基台21と孔付き板22の2
層構造である必要はなく、初めから一体物として
形成されてもよい。 In FIGS. 2 and 3, the board 20 is composed of a metal base 21 having a flat surface and a plate 22 with holes fixed thereon, and the base 21 and the plate 22 with holes are solderable. It is better to use a metal with poor solderability or a surface treatment with poor solderability. Moreover, the substrate 20 consists of a base 21 and a plate with holes 22.
It does not need to be a layered structure and may be formed as a single piece from the beginning.
そして基板20の表面には、1対の凹所A,B
が多数組配設されているが、これらの凹所A,B
は基台21の表面と孔付き板22の透孔a,bと
の組合せによつて提供されている。ただし、該基
板が一体物の場合には凹所A,Bをその表面に穿
設する必要がある。 A pair of recesses A and B are provided on the surface of the substrate 20.
There are many sets of recesses A and B.
is provided by a combination of the surface of the base 21 and the through holes a and b of the perforated plate 22. However, if the substrate is an integral piece, it is necessary to provide recesses A and B in its surface.
このように構成された基板20において、各1
対の凹所A,Bには第1図に示すチツプ15A及
び15B、即ちはんだ付け可能な金属板、例えば
一方の面にはんだめつきした厚さ0.35mmの洋白板
を適当な大きさに切断した金属層16A及び16
Bの前記めつき面に、例えば厚さ10μmのはんだ
層17A又は17Bが被着されたチツプ15A及
び15Bを、はんだ層17A,17Bが上向きに
なるように嵌合挿置する。なお、チツプ15A及
び15Bは、大形の前記金属板の上面全体にはん
だ層を被着したものを所定寸法の多数の個片に切
り刻むことにより量産される。 In the substrate 20 configured in this way, each one
In the pair of recesses A and B, chips 15A and 15B shown in FIG. Cut metal layers 16A and 16
Chips 15A and 15B each having a solder layer 17A or 17B with a thickness of 10 μm, for example, are fitted onto the plating surface of B so that the solder layers 17A and 17B face upward. Note that the chips 15A and 15B are mass-produced by cutting a large metal plate with a solder layer coated over the entire upper surface into a large number of pieces having predetermined dimensions.
次いで、第1図に示した素子10を、パツド面
13aが前記挿置されたチツプ15Aの上に接触
し、パツド面12aが前記挿置されたチツプ15
Bの上に接触するように載置する。そしてこのよ
うな作業は、所定数の素子10についてそれぞれ
行なう。 Next, the element 10 shown in FIG.
Place it on top of B so that it is in contact with it. Such operations are performed for each of a predetermined number of elements 10.
次いで、基板20とチツプ15A,15Bと素
子10の3者を一時的(例えば245℃で10秒間)
に加熱し、はんだ層17A,17Bを一時的に溶
融させ、それによつて素子10とチツプ15A,
15Bとを接合させる。その際、厚さ10μmの如
き適当量にされたはんだ層17A,17Bは、溶
融してもその表面張力により流出さず、従つて溶
融はんだが透孔A,Bとチツプ15A,15Bと
の隙間を埋め尽すようにはならない。 Next, the substrate 20, chips 15A, 15B, and element 10 are temporarily heated (for example, at 245° C. for 10 seconds).
to temporarily melt the solder layers 17A, 17B, thereby bonding the element 10 and the chip 15A,
15B. At this time, even if the solder layers 17A and 17B, which have a suitable amount of thickness such as 10 μm, melt, they do not flow out due to their surface tension, so that the molten solder flows between the holes A and B and the chips 15A and 15B. It will not be possible to fill up all the space.
さらに次いで、基板20をモールドイン金型に
セツトし、絶縁性樹脂を該金型に注入・硬化させ
ると第4図に示す如く、同一基板20に搭載され
た各素子10の4側及び上面を覆う樹脂外装30
が成形される。 Furthermore, the substrate 20 is set in a mold-in mold, and insulating resin is injected into the mold and cured. As shown in FIG. Covering resin exterior 30
is formed.
そこで、モールドイン金型から基板20を取出
すと、第5図に示す如く素子10の陰極パツド1
3aと陽極パツド12aにそれぞれ固着されたチ
ツプ15A,15Bの金属層16A,16Bが露
呈するように完成されたコンデンサ100は、基
板20から容易に取出される。そして金属層16
A,16Bの露呈平面は、コンデンサ100をプ
リント板等に搭載するためのバツド面になる。 Then, when the substrate 20 is removed from the mold-in mold, the cathode pad 1 of the device 10 is removed as shown in FIG.
The completed capacitor 100 is easily removed from the substrate 20 so that the metal layers 16A, 16B of the chips 15A, 15B fixed to the anode pad 12a and the anode pad 12a, respectively, are exposed. and metal layer 16
The exposed planes A and 16B serve as butt surfaces for mounting the capacitor 100 on a printed board or the like.
(g) 発明の効果
以明した如く本発明方法によれば、完成された
電子部品のパツドはその完成後に平坦化させる必
要がないため、従来の平坦化工程が不要となりプ
リント板等への搭載が容易となつた効果は大き
い。(g) Effects of the invention As explained above, according to the method of the present invention, there is no need to flatten the pad of a completed electronic component after completion, so the conventional flattening process is unnecessary and mounting on a printed board etc. The effect of making it easier is significant.
なお、本発明方法は上記実施例の固体電解コン
デンサに適用して有利であるだけでなく、その他
のフエースボンデイング可能な電子部品の製造に
適用して有利であることを付記する。 It should be noted that the method of the present invention is not only advantageous when applied to the solid electrolytic capacitor of the above embodiment, but also advantageous when applied to the manufacture of other face-bondable electronic components.
第1図は本発明の一実施例において使用した固
体電解コンデンサ素子とチツプを示す斜視図、第
2図は前記実施例に係わる基板の平面図、第3図
は第2図の―線の斜視断面図、第4図は前記
基板を用いて前記素子に外装を被覆した断面図、
第5図は前記素子に外装を被覆したコンデンサの
完成品を示す斜視図である。
図中において、10はアルミニウム固体電解コ
ンデンサ素子、12ははんだ付可能な金属片、1
2aは素子10の陽極パツド面、13ははんだ
層、13aは素子10の陰極パツド面、15A,
15Bはチツプ、16A,16Bははんだ付け可
能な金属層(金属板)、17A,17Bははんだ
層、20は基板、21は基台、22は孔付き板、
A,Bは基板20の凹所、30は樹脂外装、10
0はアルミニウム固体電解コンデンサを示す。
Fig. 1 is a perspective view showing a solid electrolytic capacitor element and chip used in an embodiment of the present invention, Fig. 2 is a plan view of a board related to the embodiment, and Fig. 3 is a perspective view taken along the line - in Fig. 2. A sectional view, FIG. 4 is a sectional view in which the element is coated with an exterior using the substrate,
FIG. 5 is a perspective view showing a completed capacitor in which the element is covered with an exterior. In the figure, 10 is an aluminum solid electrolytic capacitor element, 12 is a solderable metal piece, 1
2a is the anode pad surface of the element 10, 13 is the solder layer, 13a is the cathode pad surface of the element 10, 15A,
15B is a chip, 16A and 16B are solderable metal layers (metal plates), 17A and 17B are solder layers, 20 is a substrate, 21 is a base, 22 is a plate with holes,
A and B are recesses of the substrate 20, 30 is a resin exterior, and 10
0 indicates an aluminum solid electrolytic capacitor.
Claims (1)
板の該凹所にはんだ付け可能な金属層とはんだ層
が積層されたチツプを該はんだ層が上になるよう
に配置し、各該1対のチツプに各電子部品素子の
はんだ付け可能な陽極パツド面と陰極パツド面と
がそれぞれ着座するように該基板の表面に該素子
群を載置し、該はんだ層を一時的に加熱溶融して
該素子に該チツプを融着したのちモールドイン成
形により各該素子に電気絶縁樹脂の外装体を被覆
し、該チツプが融着された該外装素子群を該基板
から引離すことを特徴とする電子部品の製造方
法。1 Place a chip on which a solderable metal layer and a solder layer are laminated in the recesses of a board having multiple pairs of recesses arranged on its surface, with the solder layer facing upward, and The group of elements is placed on the surface of the substrate so that the solderable anode pad surface and cathode pad surface of each electronic component element are respectively seated on the pair of chips, and the solder layer is temporarily heated. After the chips are melted and fused to the elements, each element is covered with an exterior body made of electrically insulating resin by mold-in molding, and the exterior elements to which the chips are fused are separated from the substrate. Characteristic manufacturing method for electronic components.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58101076A JPS59225514A (en) | 1983-06-07 | 1983-06-07 | Method of producing electronic part |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58101076A JPS59225514A (en) | 1983-06-07 | 1983-06-07 | Method of producing electronic part |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59225514A JPS59225514A (en) | 1984-12-18 |
| JPH0141243B2 true JPH0141243B2 (en) | 1989-09-04 |
Family
ID=14291005
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58101076A Granted JPS59225514A (en) | 1983-06-07 | 1983-06-07 | Method of producing electronic part |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59225514A (en) |
-
1983
- 1983-06-07 JP JP58101076A patent/JPS59225514A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59225514A (en) | 1984-12-18 |
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