JPH0142080B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory device using a field effect transistor, particularly a so-called nonvolatile memory transistor that can change a threshold voltage depending on information and retain information for a long time. The purpose of this is to ensure that information is written into memory.

A non-volatile memory using a field effect transistor has a drain 2 as shown in Figure 1a.
Information is written by causing avalanche and breakdown phenomena in the vicinity of 1, and injecting hot electrons generated thereby into the floating gate 24 formed between the control gate 22 and the substrate 23 to change its threshold voltage.
FAMOS (Floating gate Avalanche
injectionMOS) and ultra-thin gate oxide film,
MNOS (Metal Nitride Oxide) uses tunneling to inject charge into the trap between the gate oxide film and the silicon nitride film formed on it.
Semiconductor) structure.

Figure 1a above shows a cross-sectional view of the FAMOS structure,
Further, FIG. 1b shows an example of the write characteristics of a FAMOS transistor. In FIG. 1b, the vertical axis shows the threshold value of the memory transistor, and the horizontal axis shows the cumulative width of applied pulses for writing. In this example, the memory threshold before writing is 1.5V, but if you apply 15V to the drain and 25V to the gate,
The threshold voltage increases as the write pulse cumulative width increases. The degree of increase is greater the closer to the initial stage;
It tends to saturate over time.

By the way, memory retention in FAMOS memory is achieved by keeping electrons injected into the floating gate there, so in order to obtain sufficient memory retention time, a sufficient amount of charge must be injected into the floating gate. It is necessary to change the threshold voltage sufficiently. Therefore, in the case of the example shown in Figure 1b,
Assuming that 5V is applied to the control gate during reading, writing requires at least a program pulse width (5 ms) that will bring the threshold voltage to 5V. Furthermore, memory devices usually have a mode called write verification. This is the mode used when writing is performed after setting an address, and then checking by reading whether writing has been performed without changing the address. Writing and reading checks usually use something called a writer, and after applying a write pulse, a read check is performed.
Automatically applies write pulses until written.

Next, FIG. 2 shows an example of a write algorithm using the write verify mode described above. In the figure, 41 is a step for setting an address;
2 is a step for applying a write pulse; 43 is a step for determining whether writing has been performed, that is, whether the read result is OK; 44 is a step for determining whether it is the final address; 45 is a step for incrementing the address. 46 is a step for determining that writing has been completed.

Here, if one write pulse is 1ms,
The threshold value reaches 5V after 5 pulses are applied, and it is determined that the data has been written. However, as mentioned above, if the control gate voltage during reading in the read mode actually used is 5V, there is no margin at all, and even a small amount of attenuation will cause it to be determined that information has disappeared.

Therefore, conventionally, there is a method of making use of this algorithm to make a determination with a sufficient margin. This algorithm is shown in FIG. This is done in step 43 by setting the control gate voltage to 5V or higher (for example, when reading during write verification).
7V). In this way, pulse application will continue until the cumulative pulse width reaches 10ms,
When writing is completed, the threshold value rises to 7V, making it possible to provide a margin with respect to the control gate voltage of 5V when only reading in normal read mode.

Setting the control gate voltage high only when reading in such a write verify mode is achieved by connecting the control gate to the circuit operation power supply 5 through the resistor formed by the transistor 2, as shown in FIG. This is possible by increasing the voltage of the power supply 5.

Next, using FIG. 3, a method of setting the voltage of the control gate to be high only in the write verify mode will be explained. Transistors 1, 2,
3, a depletion type transistor is usually used. Transistor 1 has a sufficiently longer channel length than transistor 2, and therefore, when viewed as a resistance component, transistor 1≫transistor 2 is established. The transistor 3 is a transistor for switching between writing and reading. 4 is a memory transistor array, the memory control gate of which is common.

Next, to explain the operation, when writing,
A high voltage (for example, 25V) is applied to the write power supply 6, and a write signal (Low input) is applied to the transistor 3. In this case, when the row decoder output 7 is Low, the transistor 3 remains ON and has no blocking effect, and the memory transistor array 4
A voltage close to ground is output to the control gate of , and when it is High, a voltage close to the write power supply 6 is output due to the blocking effect of the transistor 3. Further, when reading in read mode, the memory control gate is set to the voltage of the write power supply 6 or the circuit operation power supply 5, so the potential of the memory control gate is 5V.
Become a neighborhood. Reading during write verification is normally performed by applying a high level to transistor 3 while the voltage of write power supply 6 is applied, but at this time, the resistance of transistor 1 is large, and therefore the memory control gate is Even if the row decoder output 7 is High, the potential remains near the voltage of the circuit operation power supply 5 (near 5V). If you follow me,
By setting the voltage of the circuit operating power supply 5 high, the memory control gate voltage for reading during write verification can be increased.

However, there are drawbacks to this conventional method. The first drawback is that the power supply voltage for circuit operation must be increased for reading during write verification.
This takes a value different from the power supply voltage for circuit operation in the read mode, and this becomes a heavy load when creating a writer. Yet another drawback is that peripheral circuits within the memory device (for example, input buffers, decoders, sense amplifiers, data output buffers, etc.) must be able to operate sufficiently even if the power supply voltage for circuit operation is increased. In recent years, memory devices have strict requirements such as speed.
Various improvements have been made to manufacturing methods, and there is a high possibility that difficulties will arise when it comes to pressure resistance.

The present invention includes a write verify eye mode detection circuit,
To provide a semiconductor memory device which is capable of reliably writing with a margin until the threshold voltage fluctuates while compensating for the above drawbacks by providing a control voltage raising circuit which raises the control gate voltage by the output of the circuit. It has been done.

In order to facilitate understanding of the present invention, the present invention will be explained in comparison with a conventional memory device. FIGS. 5a and 5b are a block diagram of a conventional memory device and a circuit diagram of a decoder and a memory section.

In the figure, 25 is a row address input, 26 is a row address input buffer that receives a row address signal, 27 is a row decoder, 27a is a row decoder output, 28 is a column address input, and 29 is a column that receives a column address signal as an input. Address input buffer, 30 is a column decoder, 30a is a column decoder output, 31 is a sense amplifier, 32, 33 are outputs, input buffers,
34 is a data input/output.

First, the selected row decoder output 27a is input to the control gate of the memory transistor 4, which turns the transistor 4 ON or OFF according to the threshold value of the transistor 4. Next, the selected column decoder output 30a transmits the drain potential of the memory transistor 4 to the sense amplifier 31, thereby performing reading.

An embodiment of the present invention is shown in FIG. Figure a is a block diagram, and figure b is an example of a specific circuit.
In the block diagram, a write verification mode detection circuit 8 and a control gate voltage increase circuit 12 linked thereto are added compared to the conventional one. In the circuit of this embodiment, the detection circuit 8 detects that the write verification mode is in effect, and uses this detection signal and a high voltage for writing during writing to perform circuit operation only during reading during verification. It automatically increases only the control gate voltage of the memory while leaving the power supply unchanged.

FIG. 6b shows one example of a specific circuit of the above embodiment. Block 8 is a write verification mode detection circuit, and the dimensions of each transistor are determined so that the circuit outputs a high level to terminal 10 only when the write power supply 6 becomes high voltage (for example, 25V). . Terminal 9 originally has a write or read switching signal, and each is Low.
Or it has reached a high level.

Since reading in the write verification mode is performed while a high voltage is applied to the write power supply 6, a high level is output to the terminal 10, and this high level causes the transistor 11 to
becomes ON, and the level of terminal 9 decreases. If the output level of the terminal 10 and the dimensions of the transistor 11 are properly set, the terminal 9 can take an intermediate level different from the original High level. As explained in the explanation of Fig. 3, when reading in the read mode, the input to transistor 3 (in this case, the input to terminal 9 is High, so the resistance of transistor 1 >> the effect of the resistance of transistor 2) , a value close to the power supply voltage for circuit operation was output to the control gate of the memory, but in write verification mode, the input to transistor 3 takes an intermediate level, and the control gate of the memory has a value close to the power supply voltage for circuit operation. It becomes possible to output an intermediate value (for example, 7V) between the operating power supplies 6 and 5.

In the above embodiment, an example using a floating gate type memory transistor was explained, but it is possible to use it in general memory devices using non-volatile memory transistors whose threshold values are changed by writing and erasing. Needless to say.

As described above, according to the semiconductor memory device according to the present invention, since the write verify mode detection circuit and the control gate voltage increase circuit linked with the output of the write verify mode detection circuit are provided in the memory device, the power supply voltage for circuit operation can be changed. The memory control gate potential for reading during write verification can be set higher than the memory control gate potential for reading during read mode without changing the voltage.
This has the effect of realizing a memory device that can automatically write with a margin.

[Brief explanation of drawings]

Figure 1a is a cross-sectional view of a floating gate type memory transistor, Figure 1b is a characteristic diagram showing an example of the write characteristics of the floating gate type memory transistor, and Figure 2 is an example of an algorithm used for memory writing. Figure 3 is an explanatory diagram of memory control of a conventional memory device, Figure 4 is a diagram illustrating an example of an algorithm for reliably performing a write operation, and Figure 5a is a diagram of a conventional semiconductor memory device. FIG. 5B is a block diagram of the memory device, FIG. 5B is a circuit diagram thereof, FIG. 6A is a block diagram of a semiconductor memory device according to an embodiment of the present invention, and FIG. 6B is a circuit diagram of the above embodiment. 4...Nonvolatile memory transistor, 8...Write verification mode detection circuit, 12...Control gate voltage increase circuit. In the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A field-effect non-volatile memory transistor capable of changing the threshold voltage by accumulating charge by writing and discharging charge by erasing and maintaining a charge accumulation state or discharge state without a power supply, and operates. In a semiconductor memory device that has at least a write-verify mode in which writing and reading are performed continuously for each address and a read mode in which only reading is performed for each address, the write-verify mode is detected. a write verification mode detection circuit; and a control gate voltage raising circuit that sets the control gate potential of the nonvolatile memory transistor to be higher than the control gate potential in a read mode when receiving a detection signal from the write verification mode detection circuit. A semiconductor memory device comprising: 2. The field effect nonvolatile memory transistor is a floating gate memory transistor having a floating gate that stores charge and a control gate provided on the floating gate with an insulating film interposed therebetween. A semiconductor memory device according to claim 1.