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JPH0143484B2 - - Google Patents
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JPH0143484B2 - - Google Patents

Info

Publication number
JPH0143484B2
JPH0143484B2 JP55135632A JP13563280A JPH0143484B2 JP H0143484 B2 JPH0143484 B2 JP H0143484B2 JP 55135632 A JP55135632 A JP 55135632A JP 13563280 A JP13563280 A JP 13563280A JP H0143484 B2 JPH0143484 B2 JP H0143484B2
Authority
JP
Japan
Prior art keywords
transistor
constant current
current source
power supply
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55135632A
Other languages
Japanese (ja)
Other versions
JPS5760711A (en
Inventor
Tatsuji Asakawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP55135632A priority Critical patent/JPS5760711A/en
Publication of JPS5760711A publication Critical patent/JPS5760711A/en
Publication of JPH0143484B2 publication Critical patent/JPH0143484B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F3/00Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45Differential amplifiers
    • H03F3/45071Differential amplifiers with semiconductor devices only
    • H03F3/45076Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Description

【発明の詳細な説明】 本発明は絶縁ゲート型電界効果トランジスタに
よつて構成される差動増幅器に関するものであ
る。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a differential amplifier composed of insulated gate field effect transistors.

従来の絶縁ゲート型電界効果トランジスタによ
つて構成される差動増幅器を第1図に示す。Pチ
ヤネルトランジスタ(以下PTと称する)11と
Nチヤネルトランジスタ(以下NTと称する)1
2はバイアス回路を形成し、11は12に対し
て、トランジスタとして同一のバイアス条件での
コンダクタンスが高く設計されるので、その出力
VGはNT12の閾値電圧近傍の値になり、差動
増幅段及び出力段の定電流源トランジスタ13,
19に対する定電圧バイアスになる。NT13,
14,15及びPT16,17からなる差動増幅
段において、14,15は差動入力トランジスタ
対、16,17は負荷トランジスタ対であり、1
4,16;15,17は共に相補対であるため高
増幅率が達成される。16は自己バイアスされる
ようにゲート・ドレインが共通接続されるととも
に17のゲートに入力される。出力トランジスタ
PT18及び定電流源トランジスタNT19は出
力段を構成し、差動増幅段の出力VDは18のゲ
ート入力となる。18,19は相補対であるため
高増幅率を有し、差動増幅段及び出力段によつ
て、差動入力は効果的に増幅される。
FIG. 1 shows a differential amplifier constructed from conventional insulated gate field effect transistors. P channel transistor (hereinafter referred to as PT) 11 and N channel transistor (hereinafter referred to as NT) 1
2 forms a bias circuit, and 11 is designed to have a higher conductance than 12 under the same bias conditions as a transistor, so its output
VG has a value near the threshold voltage of NT12, and the constant current source transistor 13 of the differential amplification stage and output stage
This becomes a constant voltage bias for 19. NT13,
In the differential amplifier stage consisting of PTs 14 and 15 and PTs 16 and 17, 14 and 15 are a differential input transistor pair, 16 and 17 are a load transistor pair, and 1
4, 16; 15, 17 are both complementary pairs, so a high amplification factor is achieved. 16 has its gate and drain commonly connected so that it is self-biased, and is input to the gate of 17. output transistor
PT18 and constant current source transistor NT19 constitute an output stage, and the output V D of the differential amplification stage becomes the gate input of 18. Since 18 and 19 are a complementary pair, they have a high amplification factor, and the differential input is effectively amplified by the differential amplification stage and the output stage.

この従来の差動増幅回路は、差動増幅段及び出
力段の定電流源トランジスタのバイアス電圧が閾
値電圧近傍の値であるため、トランジスタサイズ
を大きくして電流が流れるようにすることから、
トランジスタの寄生容量も大きく、電流を流すこ
とにより有効に周波数特性を伸ばすことができな
い。
In this conventional differential amplifier circuit, the bias voltage of the constant current source transistors in the differential amplifier stage and the output stage is close to the threshold voltage, so the transistor size is increased to allow current to flow.
The parasitic capacitance of the transistor is also large, and the frequency characteristics cannot be effectively extended by flowing current.

本発明の目的は、周波数特性を伸ばせる構造の
差動増幅器を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a differential amplifier having a structure in which frequency characteristics can be extended.

寄生容量を増加させることなく、電流を流して
周波数特性を伸ばすには、差動増幅段及び出力段
にある定電流源トランジスタのゲートに大きい定
電圧を入力する必要があるが、差動増幅器全体と
しての特性を安定させるためには、その定電流源
トランジスタの実効ゲート電圧が電源電圧依存性
のないことが要請される。
In order to extend the frequency characteristics by flowing current without increasing parasitic capacitance, it is necessary to input a large constant voltage to the gates of the constant current source transistors in the differential amplifier stage and output stage. In order to stabilize the characteristics of the constant current source transistor, it is required that the effective gate voltage of the constant current source transistor be independent of the power supply voltage.

本発明の差動増幅器はこのために、差動入力ト
ランジスタ対及び出力トランジスタに直列接続さ
れる各定電流源トランジスタのゲートに、定電流
源トランジスタより高い閾値電圧を有し、ゲー
ト・ドレインの共通接続されたトランジスタのソ
ース・ドレイン間電圧を入力している。
For this purpose, the differential amplifier of the present invention has a threshold voltage higher than that of the constant current source transistors at the gate of each constant current source transistor connected in series with the differential input transistor pair and the output transistor, and has a common gate and drain. The source-drain voltage of the connected transistor is input.

本発明の実施例を第2図に示す。第2図は第1
図の構成の差動増幅器を基本にし、バイアス回路
を改良している。21,23乃至29は第1図1
1,13乃至19に対応し、22が12と異なる
点はその閾値電圧が高いことである。これを図示
するために22はゲートに波線をそえて表わして
いる。PT21はNT22に対して、トランジス
タとして同一のバイアス条件でのコンダクタンス
が高く設計されるのでバイアス回路出力VGはNT
22の閾値電圧近傍の値となり、差動増幅段及び
出力段の定電流源トランジスタ23,29の実効
ゲート電圧は、22及び23、或いは22及び2
9の閾値電圧の差で与えられる。この閾値電圧差
が、電源電圧依存性をもたないこと、更には適当
な大きさにこの差電圧を設定し、トランジスタサ
イズを電流値に合わせて選択することにより、優
れた特性の差動増幅器を達成することができる。
An embodiment of the invention is shown in FIG. Figure 2 is the first
It is based on a differential amplifier with the configuration shown in the figure, and the bias circuit has been improved. 21, 23 to 29 are shown in Fig. 1
1, 13 to 19, and 22 differs from 12 in that its threshold voltage is higher. To illustrate this, 22 is shown with a wavy line attached to the gate. PT21 is designed to have higher conductance than NT22 under the same bias conditions as a transistor, so the bias circuit output V G is NT22.
The effective gate voltage of the constant current source transistors 23 and 29 in the differential amplification stage and the output stage is 22 and 23, or 22 and 2.
It is given by the difference in threshold voltage of 9. By ensuring that this threshold voltage difference has no power supply voltage dependence, and by setting this difference voltage to an appropriate size and selecting the transistor size according to the current value, a differential amplifier with excellent characteristics can be achieved. can be achieved.

この高い閾値電圧を持つトランジスタ22は、 (i)チヤネルドーピング (ii)ゲート材料の選択 のいずれかの方法を用いて行なわれる。 The transistor 22 with this high threshold voltage is (i) Channel doping (ii) Gate material selection This is done using one of the following methods.

(i)については、そもそも22,23,29とも
同一基板濃度のトランジスタとして形成し、2
3,29にドナーイオン例えば 31P+をチヤネル
ドーピングして閾値電圧を下げるか、或いは22
にアクセプターイオン例えば 11B+をチヤネルド
ーピングして閾値電圧を上げる。
Regarding (i), 22, 23, and 29 are originally formed as transistors with the same substrate concentration, and 2
3, 29 can be channel-doped with donor ions such as 31 P + to lower the threshold voltage, or 22
Increase the threshold voltage by channel doping with acceptor ions, e.g. 11B + .

(ii)については特に多結晶シリコンをゲート材料
とするものでは22はP型、23,29にN型の
不純物を導入したゲートを選択する。
Regarding (ii), in particular, in the case where polycrystalline silicon is used as the gate material, a gate in which 22 is a P-type impurity and 23 and 29 are N-type impurities is selected.

いずれの場合においても、差動入力トランジス
タ対24,25は、23,29と同閾値電圧のト
ランジスタとすることも、また22と同閾値電圧
のトランジスタとすることも可能である。
In either case, the differential input transistor pair 24, 25 can be transistors with the same threshold voltage as 23, 29, or can be transistors with the same threshold voltage as 22.

以上述べた本発明の差動増幅器は、差動増幅段
及び出力段の定電流源トランジスタに、同極性で
閾値電圧が高く、ゲート・ドレインの共通接続さ
れたトランジスタのソース・ドレイン電圧をバイ
アスすることにより、定電流源トランジスタの実
効ゲート電圧を大きくし、電流が流せる構成にし
て周波数特性を改善したものであつて、簡単な構
成で優れた特性を得ることができるものである。
The differential amplifier of the present invention described above biases the source-drain voltage of the constant current source transistors in the differential amplification stage and the output stage of transistors having the same polarity, high threshold voltage, and whose gates and drains are commonly connected. As a result, the effective gate voltage of the constant current source transistor is increased, and the frequency characteristics are improved by creating a configuration that allows current to flow, and excellent characteristics can be obtained with a simple configuration.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の差動増幅器である。第2図は本
発明の差動増幅器である。
FIG. 1 shows a conventional differential amplifier. FIG. 2 shows a differential amplifier of the present invention.

Claims (1)

【特許請求の範囲】[Claims] 1 第1の電源電位にソース電極を接続する第1
の定電流源トランジスタと、該定電流源トランジ
スタに直列接続される差動入力トランジスタ対
と、該差動入力トランジスタと第2の電源電位の
間に接続される負荷素子と、前記第1の電源電位
にソース電極を接続する第2の定電流源トランジ
スタと、該第2の定電流源トランジスタと前記第
2の電源電位の間に接続され且つゲート電極を前
記差動入力トランジスタと前記負荷素子の接続点
に接続する出力トランジスタとを備える差動増幅
器において、前記第1の電源電位にソース電極を
接続すると共にゲート電極とドレイン電極を共通
接続し且つ前記第1及び第2の定電流源トランジ
スタの閾値電圧よりも高い閾値電圧を有するバイ
アス用トランジスタと、該バイアス用トランジス
タのドレイン電極と前記第2の電源電位の間に接
続されるバイアス用負荷素子とを具備し、前記第
1及び第2の定電流源トランジスタと前記バイア
ス用トランジスタを同極性のトランジスタとし、
前記第1及び第2の定電流源トランジスタの各ゲ
ート電極を前記バイアス用トランジスタのドレイ
ン電極に接続して成ることを特徴とする差動増幅
器。
1. A first electrode that connects the source electrode to the first power supply potential.
a constant current source transistor, a differential input transistor pair connected in series to the constant current source transistor, a load element connected between the differential input transistor and a second power supply potential, and the first power supply a second constant current source transistor having a source electrode connected to the potential; and a second constant current source transistor connected between the second constant current source transistor and the second power supply potential and having a gate electrode connected to the differential input transistor and the load element. In a differential amplifier comprising an output transistor connected to a connection point, a source electrode is connected to the first power supply potential, a gate electrode and a drain electrode are commonly connected, and the first and second constant current source transistors are connected to the first power supply potential. a bias transistor having a threshold voltage higher than a threshold voltage; and a bias load element connected between a drain electrode of the bias transistor and the second power supply potential, The constant current source transistor and the bias transistor are transistors of the same polarity,
A differential amplifier characterized in that each gate electrode of the first and second constant current source transistors is connected to the drain electrode of the bias transistor.
JP55135632A 1980-09-29 1980-09-29 Differential amplifier Granted JPS5760711A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55135632A JPS5760711A (en) 1980-09-29 1980-09-29 Differential amplifier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55135632A JPS5760711A (en) 1980-09-29 1980-09-29 Differential amplifier

Publications (2)

Publication Number Publication Date
JPS5760711A JPS5760711A (en) 1982-04-12
JPH0143484B2 true JPH0143484B2 (en) 1989-09-21

Family

ID=15156338

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55135632A Granted JPS5760711A (en) 1980-09-29 1980-09-29 Differential amplifier

Country Status (1)

Country Link
JP (1) JPS5760711A (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2545374B2 (en) * 1986-11-29 1996-10-16 富士通株式会社 Differential amplifier circuit having constant current source circuit
DE69325810T2 (en) * 1993-11-30 1999-11-18 Stmicroelectronics S.R.L., Agrate Brianza CMOS-integrated high-performance transconductance operational amplifier
DE69312305T2 (en) * 1993-12-28 1998-01-15 Sgs Thomson Microelectronics Voltage boosters, especially for non-volatile memories
JP3713324B2 (en) * 1996-02-26 2005-11-09 三菱電機株式会社 Current mirror circuit and signal processing circuit

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5539411A (en) * 1978-09-13 1980-03-19 Hitachi Ltd Reference voltage generator

Also Published As

Publication number Publication date
JPS5760711A (en) 1982-04-12

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