JPH0143489B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a synchronous pulse generator that generates a timing pulse synchronized with a clock pulse near the leading edge of an input signal, and is capable of generating an output signal of a constant pulse width with a simpler configuration. This provides a possible circuit configuration.

FIG. 1 shows a circuit diagram of a conventional synchronous pulse generator. The problems of the prior art will be explained below with reference to FIG.

In FIG. 1, when the levels of the signal input terminal Since the output level of the flip-flop circuit 100 is set to "1" in advance,
The output level of NAND gate 3 is from “1” to “0”
, thereby connecting NAND gate 4 and
The output level of the second RS flip-flop 200 configured by cross-coupling the input and output terminals of the NAND gate 5 shifts to "1".

When the output level of the RS flip-flop circuit 200 shifts to "1", when the output level of the inverter 6 shifts to "1" at the trailing edge of the clock pulse, the output level of the NAND gate 7 shifts to "0"; As a result, the above
The outputs of RS flip-flop circuits 100 and 200 transition to "1".

Since the output of the RS flip-flop circuit 100 does not become "1" until the trailing edge of the input signal applied to the signal input terminal X arrives, the RS flip-flop circuit 100 does not become "1" until the leading edge of the input signal arrives again. The output level of the flip-flop circuit 200, ie, the level of the signal output terminal Z, never becomes "1" again.

In this way, the circuit of FIG. 1 generates a timing pulse synchronized with the clock pulse near the leading edge of the input signal, but the pulse width of the output pulse appearing at the signal output terminal Z is equal to the leading edge of the input signal and the leading edge of the clock pulse. The problem arises that it becomes wider or narrower depending on the phase relationship between the two.

For example, when the leading edge of the input signal arrives immediately after the trailing edge of the clock pulse, the RS flip-flop circuit 2
00 transitions to "1" and the RS
The output level of the flip-flop circuit 200 returns to "0" again, and an output pulse width equivalent to half-lock is obtained. However, if the leading edge of the input signal arrives just before the trailing edge of the clock pulse, the RS flip-flop circuit 200
Even if the output level of 0 shifts to "1", the output level of the RS flip-flop circuit 200 immediately returns to "0", so that only an output pulse with an extremely narrow pulse width can be obtained.

If the output pulse width becomes extremely narrow, problems arise in that the output pulse cannot drive (trigger) other circuits or disappear due to transmission loss or the like.

As a way to solve these problems, a circuit configuration as shown in FIG. 2 can be considered.

In the circuit shown in FIG. 2, when the level of the signal input terminal X is "1" and the level of the clock pulse input terminal Y is "0", the second RS flip-flop circuit 2
When the output level of 00 shifts to "1" and the level of the clock pulse input terminal Y becomes "1",
The output level of NAND gate 8 shifts to "0", the output level of NAND gate 9 shifts to "1",
Since the output level of the NAND gate 10 shifts to "0" and the output level of the NAND gate 11 shifts to "0" at the trailing edge of the clock pulse, the output levels of the NAND gates 9 and 10 are again "0", respectively. ”, returns to “1”.

Therefore, in the circuit of FIG. 2, the pulse width of the output signal is reliably obtained by the half clock, and the pulse width is constant regardless of the phase relationship between the leading edge of the input signal and the leading edge of the clock pulse. Compared to the circuit in Figure 1, the number of NAND gates has increased by three, and since many sets of this type of circuit are used especially in digital LSIs, the overall number of gates and power consumption can be increased. There were many problems such as confusion.

The synchronous pulse generator of the present invention solves the above problems.

FIG. 3 shows a circuit configuration of a synchronous pulse generator according to an embodiment of the present invention. In FIG. 3, the respective input/output terminals of NAND gate 1 and NAND gate 2 are cross-coupled to each other to form a first RS flip-flop circuit 10.
0 is configured and its RS flip-flop circuit 1
The set terminal 00 is connected to the signal input terminal X.

Furthermore, input terminals of a 4-input NAND gate 12 are connected to the output terminal 100c, the signal input terminal X, the first clock pulse input terminal _Y1 , and the second clock pulse input terminal _Y2 of the RS flip-flop circuit 100, respectively. The output terminal of the NAND gate 12 has the NAND gate 4 and the NAND
A set terminal 200a of a second RS flip-flop circuit 200 in which the input and output terminals of the gate 5 are cross-coupled to each other.
is connected, and its RS flip-flop circuit 20
The output terminal 200c of 0 is connected to the signal output terminal Z.

Further, the input terminal of the inverter 6 is connected to the second clock pulse input terminal _Y2 , and the input terminal of the inverter 6 is connected to the second clock pulse input terminal Y2.
Output terminal 200 of flip-flop circuit 200
c. The output terminal of the inverter 6 and the first clock pulse input terminal _Y1 each have three inputs.
The input terminal of the NAND gate 13 is connected to the
The output terminal of the NAND gate 13 is connected to the reset terminal 100b of the RS flip-flop circuit 100 and the reset terminal 200b of the RS flip-flop circuit 200.

Now, in Fig. 3, the first clock pulse input terminal _Y1 is connected to the second clock pulse input terminal Y1.
A clock pulse is applied having twice the frequency of the clock pulse applied to _Y2 .

Note that in digital systems where this type of circuit is frequently used, clock pulses are often created by frequency-dividing the output signal of a crystal oscillator, etc., so the first and second clock pulses with a frequency ratio of 2:1 are easily obtained.

Figure 4 shows a signal waveform diagram of each part in Figure 3, and Figure 4 a, b, and c represent the first clock pulse input terminal Y ₁ , the second clock pulse input terminal Y ₂ , and the signal input terminal, respectively. Figure 4 d, e, f, g, h, i, and j are the signal waveforms applied to
This is the output signal waveform of the inverter 6 and the NAND gate 13.

At time _t1 , when the level of the first clock pulse input terminal _Y1 changes from "0" to "1",
Before that, the output level of NAND gate 1, the level of signal input terminal
Since the level of Y ₂ is all “1”,
The output level of NAND gate 12 shifts to "0", and then the output level of NAND gate 4 shifts to "1"
Then, the output level of the NAND gate 5 shifts to "0".

At time _t2 , when the level of the first clock pulse input terminal _Y1 shifts to "0", the output level of the NAND gate 12 subsequently returns to "1", but the output levels of the other gates do not change.

At time _t3 , when the level of the first clock pulse input terminal _Y1 shifts to "1", the output level of the NAND gate 4 and the inverter 6 have both become "1" before then, so the NAND gate 13 The output level of NAND gate 2 and NAND gate 5 shifts to "0", thereby shifting the output levels of NAND gate 2 and NAND gate 5 to "1".

When the output level of the NAND gate 2 shifts to "1", the output level of the NAND gate 1 shifts to "0"
On the other hand, due to the transition of the output level of the NAND gate 5 to "1", the NAND gate 4
As a result, the output level of
The output level of the NAND gate 13 returns to "1".

At time _t4 , the level of the first clock pulse input terminal _Y1 shifts to "1", but at this point the output level of NAND gate 1 has already reached "0".
Therefore, the output level of the NAND gate 12 does not change, and the output levels of the other gates also do not change.

At time _t5 , when the level of the signal input terminal Shift to pulse generation cycle.

At time _t6 , with the levels of the first clock pulse input terminal _Y1 and the second clock pulse input terminal _Y2 already set to "1", the level of the signal input terminal X becomes "1". When the transition occurs, the output level of the NAND gate 12 becomes “0”
, and the output levels of NAND gate 4 and NAND gate 5 change one after another in the same way as at time _t1 .

At time _t7 , when the level of the first clock pulse input terminal _Y1 becomes "1" again, as at time _t3 , NAND gate 13, NAND gate 2, NAND gate 5, NAND gate 1,
The output level of the NAND gate 4 changes one after another.

As a result, the first clock pulse input terminal Y ₁ , the second clock pulse input terminal Y ₂ , and
When signals as shown in FIG. 4a, b, and c are applied to the signal input terminals X, output signals as shown in FIG. 4g appear at the signal output terminal Z.

Now, as is clear from FIG. 4, in the synchronous pulse generator of the present invention shown in FIG. Since the NAND gate 13 is configured to generate an output signal, and when the level of the first clock pulse signal is "1" and the level of the second clock pulse signal is "0", the NAND gate 13 generates the output signal. After the NAND gate 12 generates an output signal, the NAND
There will be a time interval of at least half the first clock pulse before gate 13 generates an output signal.

That is, the pulse width of the output signal appearing at the signal output terminal Z is at least half a clock pulse of the first clock pulse, or more precisely, it is at the "0" level of the signal applied to the first clock pulse input terminal _Y1. This will give you a range of time.

As described above, the synchronous pulse generation circuit of the present invention can reliably obtain an output signal of a certain width or more with an extremely simple configuration, but the embodiments of the present invention are not necessarily limited to the configuration shown in FIG. not,
Other matching gates such as NOR gates can be used instead of NAND gates, and the first RS
Reset terminal 10 of flip-flop circuit 100
0b may be connected to the output terminal of the NAND gate 12 or the output terminal of the NAND gate 5. For example, the fifth
The figure shows the circuit configuration of another embodiment of the present invention. In this figure, an AND gate whose input terminals are respectively connected to the first clock pulse input terminal _Y1 and the second clock pulse input terminal _Y2 is shown. 14 and
The NAND gate 3 whose input terminal is connected to the output terminal of the AND gate 14 causes the
It has the same function as NAND gate 12.

Also, the first RS flip-flop circuit 100
The reset terminal 100b of the NAND gate 3
is connected to the output terminal of the

In yet another embodiment shown in FIG. 6, the reset terminal 1 of the first RS flip-flop circuit
00b is connected to the output terminal 200d of the NAND gate 5 constituting the second RS flip-flop circuit.

Needless to say, these circuits also exhibit the same effect as the embodiment shown in FIG.

As described above, the synchronous pulse generator of the present invention includes a first RS flip-flop circuit (corresponding to 100 in the same embodiment) to which an input signal is applied to the set terminal (corresponding to 100a in the above embodiment), the input signal to the input terminal, A first coincidence gate (NAND gate 12 or NAND gate 3) to which the output signal of the first RS flip-flop circuit, a first clock pulse, and a second clock pulse having a frequency half that of the first clock pulse is applied.
(equivalent to a gate circuit using AND gate 14),
A second RS flip-flop circuit (corresponding to 200) whose set terminal (corresponding to 200a) is given the output signal of the first coincidence gate; a second coincidence gate (corresponding to NAND gate 13), which is supplied with the first clock pulse and an inverted signal of the second clock pulse, and whose output terminal is connected to the reset terminal (corresponding to 200b) of the second RS flip-flop circuit; ),
The output signal is taken out from the second RS flip-flop circuit, and the reset terminal (corresponding to 100b) of the first RS flip-flop circuit is
the output signal of the first coincidence gate; and the output signal of the second coincidence gate.
The circuit is configured to provide either the output signal of the coincidence gate of the circuit or the output signal of the second RS flip-flop circuit, and is configured to provide either the output signal of the coincidence gate of Since the generation timing of the output pulse is controlled, a pulse signal of a certain width or more can be reliably obtained with a simple circuit configuration, which is a great effect.

[Brief explanation of drawings]

1 and 2 are circuit configuration diagrams showing a conventional example, FIG. 3 is a circuit configuration diagram of an embodiment of the present invention, and FIG. 4 a, b, c, d, e, f, g, h, i and j are signal waveform diagrams of each part in FIG. 3, and FIGS. 5 and 6 are circuit configuration diagrams of other embodiments of the present invention. 1, 2, 4, 5...NAND gate, 100...
...first RS flip-flop circuit, 200...
Second RS flip-flop circuit, X...signal input terminal, _Y1 ...first clock pulse input terminal,
Y ₂ ...Second clock pulse input terminal, Z...
Signal output terminal.

Claims (1)

[Claims] 1. A first set terminal to which an input signal is applied.
an RS flip-flop circuit; a second RS flip-flop circuit whose set terminal receives the output signal of the first logic gate; and whose input terminal receives the output signal of the second RS flip-flop circuit, the first clock pulse, and the first clock pulse. a second logic gate to which an inverted signal of the second clock pulse is applied and whose output terminal is connected to the reset terminal of the second RS flip-flop circuit, and extracts an output signal from the second RS flip-flop circuit; A synchronous pulse generator configured to apply an output signal of the first logic gate to a reset terminal of the first RS flip-flop circuit. 2 The first terminal to which the input signal is applied to the set terminal
an RS flip-flop circuit; a second RS flip-flop circuit whose set terminal receives the output signal of the first logic gate; and whose input terminal receives the output signal of the second RS flip-flop circuit, the first clock pulse, and the first clock pulse. a second logic gate to which an inverted signal of the second clock pulse is applied and whose output terminal is connected to the reset terminal of the second RS flip-flop circuit, and extracts an output signal from the second RS flip-flop circuit; A synchronous pulse generator configured to apply an output signal of the second logic gate to a reset terminal of the first RS flip-flop circuit. 3 The first terminal to which the input signal is applied to the set terminal
an RS flip-flop circuit; a second RS flip-flop circuit whose set terminal is supplied with the output signal of the first logic gate; and whose input terminals are supplied with the output signal of the second RS flip-flop circuit, the first clock pulse, and the first a second logic gate to which an inverted signal of the second clock pulse is applied and whose output terminal is connected to the reset terminal of the second RS flip-flop circuit, and extracts an output signal from the second RS flip-flop circuit; The second RS flip-flop circuit is connected to the reset terminal of the first RS flip-flop circuit.
A synchronous pulse generator configured to provide an inverted output signal of an RS flip-flop circuit.