JPH0144629B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an elevator data recording device that is connected to an elevator control device and collects, processes, and records various data during elevator operation.

Modern elevators have adopted control circuits made up of integrated circuits such as microcomputers for group management, which aims to efficiently operate multiple elevators and allow passengers to arrive at their destination floors quickly. It instantly processes large amounts of information such as call information and the number of passengers boarding and alighting, making the group management described above even more detailed.

In addition, even in individual elevators, large amounts of information are processed at high speed using control circuits made up of integrated circuits such as the above-mentioned microcomputers, from drive control to operation management, and the control itself is becoming more sophisticated. .

On the other hand, in the performance evaluation and failure analysis of these elevator control devices, it is necessary to process a large amount of information in the same way as in the control. Nowadays, large amounts of data can be recorded over long periods of time.

However, these recording devices are equipped with devices such as printers, magnetic tapes, and magnetic disks as data output devices, but during data recording, printers may run out of recording paper or paper jams, and magnetic tape may run out or rotate. Abnormal conditions such as anomalies may occur, and since data recording is generally performed unattended, valuable data resulting from data collection and statistical processing has sometimes been wasted.

This invention was made in order to eliminate the above-mentioned conventional drawbacks, and when an abnormality occurs in the data output device during operation, processing results are not output to the data output device, processing continues, and the collected data of the elevator is To provide an elevator data recording device that does not waste data.

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of an elevator data recording device according to the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of one embodiment. 1 in FIG. 1 is a processing device consisting of an electronic computer such as a microcomputer, and an input circuit 6 of this processing device receives operations from an elevator control device 2, a data input device 3, a clock circuit 4, and a switch circuit 5. The command signal 5a and the output of the abnormality detection circuit 18 are respectively inputted.

The data input device 3 is used to generate necessary data by operating a keyboard or the like. Also,
The clock circuit 4 outputs the current time every moment, and the input circuit 6 includes a conversion circuit for receiving each of the inputs.

The processing device 1 includes this input circuit 6, a central processing unit (hereinafter referred to as CPU) 7 that processes each signal taken in from the input circuit 6, and a RAM as a read/write memory that stores data such as the calculation results of the CPU 7. -A8, RAM-B9, a ROM10 as a read-only memory that stores programs and constant value data, and an output circuit 11 consisting of a converter that outputs signals from the CPU7.

On the other hand, 12 is a data output device such as a printer or magnetic tape that records the data processed by the processing device 1 from the output circuit 11 through the output signal line 11a. This is a signal line that outputs data for setting the time.

Further, 13 is the first unit excluding the elevator control device 2.
This is a power supply device that supplies power to the circuit in the figure (the power supply line is omitted), and 14 monitors the output of the power supply device 13, and when it reaches a normal output value, interrupts the interrupt input INT of the CPU 7. This is a power supply monitoring circuit that outputs a signal 14a.

Further, the uninterruptible power supply device 15 is composed of a rechargeable battery or the like, and its output is supplied to the clock circuit 4 and RAM-A8 through a diode 16. And clock circuit 4 and RAM-A8
Power is also supplied from the power supply device 13 via the diode 17.

Furthermore, the abnormality detection circuit 18 is a data detection device 12 that detects paper jams, paper cuts in the case of printers, rotational abnormalities in the case of magnetic disks or magnetic tapes, etc.
It detects an abnormality in the circuit and generates an output to the input circuit 6.

FIG. 2 shows the contents of RAM-A8, which is data obtained from the data input device 3.
0 is a memory in which the output sampling time TS of statistical processing results is stored; 31 is a memory in which selection data SPRO of a plurality of statistical processing programs is stored; 3
2 is a memory that stores the output time value of the clock circuit 4;
It is TIME1.

FIG. 3 shows the contents of RAM-B9, and 37 in the figure is an operation ready flag that becomes "1" when necessary data is input from the data input device 3, and becomes "0" otherwise. The memory 38 in which FLAG1 is stored stores an operation stop detection flag FLAG2 that becomes "1" when it detects that the statistical processing operation has stopped, and becomes "0" when the stop information is output to the data output device 12. The memory 39 outputs the statistical processing results to the data output device 12.
This memory stores a sampling output time detection flag FLAG3 which becomes "1" at the time when the data should be output and becomes "0" when the data is output.

Further, 40 is an abnormality detection flag of the data output device 12 which becomes “1” when an abnormality is detected in the data output device 12 and becomes “0” when the data output device 12 returns to normal.
A memory 41 in which FLAG4 is stored is set by the data input device 3, and a memory TIME2, 42 in which the initial setting time of the clock circuit 4 obtained through the input circuit 6 is stored is input from the clock circuit 4 through the input circuit 6. Memory TIME that stores the obtained current time
3 and 44 are memories TSTOP1 and 43 that store the time when the operation of the processing circuit 1 stopped; memories TSTART1 and 46 that store the time when the operation resumed;
TSTOP2, 45 is a memory that stores the time when an abnormality occurred in the data output device 12. TSTOP2, 45 is a memory that stores the time when the data output device 12 returns to normal.
TSTART2 and 47 are memories that store the sampling output time of the arithmetic processing results of CPU7.
TSAMP, 48 are memories DIN ₁ to DINm that store a plurality of data groups collected from the elevator control device 2 via the input circuit 6, and 49 is a memory that stores data groups resulting from arithmetic processing.
_DOUT1 to DOUTn.

FIG. 4 shows the overall program configuration of the elevator data recording device stored in the ROM 10. In the figure, 50 is an initial value setting program for setting the initial value of each data, and 51 is the data input device 3. 52 is a clock initial setting program that sets the output time of the clock circuit 4 to the current time. 53 is a clock initial setting program that writes data to the RAM-A8 through the input circuit 6. 53 is a clock initial setting program that writes data to the RAM-A8 through the input circuit 6. 53 is a clock initial setting program that sets the output time of the clock circuit 4 to the current time. An operation stop detection program that detects the time when the operation resumes and returns.
54 is a program for selecting a program to be executed from among a plurality of statistical calculation processing programs, and a selection and execution program for the calculation processing program to be executed; 55 is a program for outputting the data of the calculation processing results to the data output device 12 through the output circuit 11; This is a data output program that detects and outputs the time.

Next, the operation of the elevator data recording apparatus of the present invention configured as described above will be explained.

First, when the power switch (not shown) is turned on while the switch 5 of this data recording device is off, power starts to be supplied from the power supply 13, and the power supply monitoring circuit 14 determines that the output voltage value of the supplied power is set to a predetermined value. When the value of is reached, through the signal line 14a,
A pulse signal is supplied to the interrupt input INT of CPU7,
Execution of the program shown in FIG. 4 is started.

In the first initial setting program 50, RAM-B
The contents of 9 are all cleared to "0", and the next operation preparation program 51 is activated.

That is, as detailed in FIG. 5, step 60
The operation command signal 5a of the switch 5 is input through the input circuit 6, and it is determined whether the switch 5 is in the on state. If YES, the next program 5 is input.
2 is activated.

If NO, the process proceeds to step 61, where it is determined whether FLAG1 is "0". At this time,
In the initial value setting program 50, RAM-B
Since the contents of 9 are all set to "0",
FLAG=0, and the following steps 62, 63, 64,
Proceed to 65.

In steps 62, 63, and 64, data set by the data input device 3 passes through the input circuit 6,
This is the procedure for writing to RAM-A8.

In step 62, the initial setting time in the clock circuit 4, for example, the value of X hours, Y minutes, and Z seconds, is written to TIME2 of the memory 41 of RAM-B9, and in Step 63, the output time interval of the arithmetic processing result, that is, the sampling time S Minutes RAM - A8 memory 30
Assuming that there are multiple arithmetic processing programs, here two types, program A and program B, in step 64, the specified value, A or B, is written to the memory 31 of RAM-A8.
Written to SPRO. Then, in step 65, a flag FLAG1 indicating the passage of this program 51 is set.
is set to "1" and the process returns to step 60.

Next, if the switch 5 is still in the OFF state, a negative determination is made in step 61, and the process returns to step 60.
Steps 60 and 6 until switch 5 is on
1 is repeated.

That is, steps 62 to 65 are passed only once when the power is turned on, and the operation preparation state is reached, and the state is in a waiting state until the switch 5 is turned on.

Next, switch 5 is turned on at the time set in step 62.
is input, step 60 advances to YES,
The next clock initial setting program 52 operates.

That is, as shown in detail in FIG.
1 is set to "1", so steps 67 and 6
Proceed to 8,69.

In step 67, the initial setting time value TIME2 of the clock circuit 4 set in step 62 is output to the clock circuit 4 through the output circuit 11 and the signal line 11b, and the clock circuit 4 is time-adjusted to the current time.

In step 68, the time value for time adjustment, that is, the contents of TIME2 in memory 41, is transferred to memory 32.
Written and saved on TIME1. Then, in step 69, the flag FLAG1 is set to "0", and the program proceeds to the next operation stop detection program 53.

Therefore, in step 66 in the next program cycle, FLAG1=0, so step 6
7, 68, and 69 are not executed, and are executed only once when the power is turned on.

In the next operation stop detection program 53, as shown in detail in FIG. 7, first, in step 70, the current time value TCLK, which is the output of the clock circuit 4, is read via the input circuit 6 and written to TIME3 of the memory 42. .

In step 71, the difference between the saved time value and the current time value, which are the contents of TIME1 in the memory 32 and TIME3 in the memory 42, is smaller than a predetermined minute time TD (a time value that is at least larger than the program cycle time). It is determined whether or not the time TD is greater than the time TD, the process proceeds to steps 72, 73, and 74. Since |TIME3−TIME1|≦TD, normally, the program proceeds to the next program 54.

If |TIME3−TIME1|>TD,
This means that the execution of the program has stopped due to a power outage or other cause, and the TIME of the memory 42 at this time is
The content of 3 is the time when the program was restarted, and in step 72 the operation restart time is stored in the memory 43.
Written to TSTART1 and saved time memory 3
The content of TIME1 in step 2 is the program stop time, and in step 73 the operation stop time is stored in the memory 44.
Written to TSTOP1.

Further, in step 74, an operation stop detection flag of the memory 38 indicating that an operation stop has been detected is set.
FLAG2 is set to "1" and program 54
Proceed to.

The next program 54 is an arithmetic processing program selection and execution program, and as shown in detail in FIG. 8, in step 75 it is determined whether the contents of SPRO in the memory 31 specify program A. If YES, proceed to step 76 to process program A; if NO, proceed to step 77 to determine whether program B is specified; if YES, proceed to step 78 to process program B. and proceed. Here, if NO, the process proceeds to the next program 55.

The processing in steps 76 and 78 is data recording and statistical processing of the elevator, for example, each landing,
This includes counting the number of calls, calculating the registration time of calls, and calculating the average time. It can be obtained by dividing by the count value of , and the same method can be used for car calls.

That is, in this process, signals such as calls from the elevator control device are collected via the input circuit 6, stored in DIN ₁ to DINm of the memory 48, and the processing is performed using these data. The data is held in DOUT ₁ to DOUTn of the memory 49.

Although this program 54 is the main operation of the elevator data recording device of the present invention, it is a well-known technique and is not the purpose of the present invention, so a detailed explanation thereof will be omitted.

In the next program 55, as shown in detail in FIG. 9, first, in step 79, it is determined whether the sampling output time has been set, and the detection flag of FLAG3 in the memory 39 is checked, and the flag is set to "0". That is, if it is not set, the process goes to steps 80 and 81; if it is "1", that is, it is set, the process goes to the next step 82.

In step 80, the next sampling output time is determined by the sum of the current time value, which is the content of TIME3 in the memory 42, and the sampling time TS in the memory 30,
It is written to TSAMP in memory 47. Step 81
Then, the detection flag FLAG3 indicating that the sampling time has been set is set to "1", and the process proceeds to the next step 82.

In step 82, the input circuit 6 is connected to the abnormality detection circuit 1.
If the output of step 8 is read and an error has occurred in the data output device 12, follow step 83 in the NO direction.
If the process is normal, proceed to step 87 in the YES direction.

In step 83, the sampling output time that is the content of the memory TSAM is replaced with the current time of TIME3, and in the next step 84, the abnormality detection flag FLAG4 is replaced.
is checked, and if it is "1", this data output program 55 ends, and if it is "0", in step 85, the memory TSTOP2 of the abnormality occurrence time is stored.
The current time of TIME3 is written to , and the abnormality detection flag FLAG4 is set to "1" in step 86.
The data output program 55 is ended.

That is, if there is an abnormality in the data output device, the sampling output time is rewritten to the current time in each program cycle in step 83, and step 85 is passed only once when an abnormality occurs.

If there is no problem with the data output device,
In step 87, it is determined whether or not it is the sampling output time, that is, it is determined whether or not it is the sampling output time.
It is determined whether the contents of TIME3 match or have become larger than the contents of TSAMP in memory 47, and NO
If so, exit this data output program and
If YES, proceed to steps 88 and 89.

In step 88, the sampling detection flag FLAG
3 is set to ``0'' so that a new next sampling output time is set in step 80 of the next program cycle.

Step 89 is data output processing, which is the processing result of the program 54, that is, the data output processing of the memory 49.
Data from DOUT ₁ to DOUTm is sent to the data output device 1 through the output circuit 11 and the output signal line 11a.
2, and when the output is completed, DOUT ₁ to DOUT of the memory 49 is output for the next sampling process.
All DOUTm are cleared to "0".

In the next step 90, the operation stop detection flag is
When FLAG2 is checked and there is no stoppage of operation, that is, if FLAG=0, the process advances to the next step 93.

When there is an operation stoppage, that is, when FLAG=1, steps 91 and 92 are executed and the data output program 55 is ended.

Step 91 is data output processing, in which the contents of TSTOP1 in the memory 44 for the operation stop time and TSTART2 in the memory 43 for the operation restart time are output to the output circuit 11.
and is output to the data output device 12 through the output signal line 11a.

In step 92, the operation stop detection flag FLAG2 is set.
is set to "0", so the data output processing in steps 91 and 92 will not be performed from the next program cycle.

In other words, steps 91 and 92 are executed only when program execution is stopped due to a power outage or the like and then resumed.

Step 93 is to check the abnormality detection flag FLAG4 in the data output device 12 and if it is normal,
Proceed in the direction of YES and end the data output program 55, but if it is "1", steps 94, 95, 9
Proceed to step 6.

Step 94 writes the current time, which is the content of TIME3 in the memory 42, to TSTART2 in the memory 45, which stores the time when the data output device 12 returns to normal.

Step 95 is TSTOP2 of memory 46 and memory 4
This is an output process 3 in which the contents of TSTART2 in step 5, that is, the time when an abnormality occurred in the data output device 12 and the time when it returned to normal, are output to the data output device 12 and stored.In the next step 95, the abnormality detection flag FLAG4 is output. is set to "0", and the data output program 55 is ended.

Therefore, step 9 of the next program cycle
3, FLAG4=0 and steps 94, 95,
96 is not executed, and next data output device 1
Even if an abnormality occurs in step 2, the storage operation of the abnormality occurrence time in step 85 becomes possible.

When the data output program 55 ends, the operation returns to the operation preparation program 51 again, and the next program cycle begins, where the operations from the operation preparation program 51 to the data output program 55 are repeatedly executed.

Even if a power outage occurs while the program is running and the operation of the processing device 1 is stopped, the RAM-A is
Since power continues to be supplied to 8 and clock circuit 4,
The sampling time set from the data input device 3 in the operation preparation program 51, the processing program selection command, and the time immediately before the power outage continue to be held in the RAM-A8, and the clock circuit can also continue to operate. .

Therefore, when the power outage returns next time, when the output voltage of the power supply device 13 reaches a predetermined value, an interrupt pulse is supplied from the power supply monitoring device 14 to the CPU 7 through the signal line 14a, and the program returns to the initial value. The setting program 54 automatically restarts.

At this time, since the switch 5 is already in the on state, step 6 of the operation preparation program 51 in FIG.
0 goes in the direction of YES, the operation preparation procedures of steps 62 to 65 are not performed, the clock initial setting program 52 in FIG. TIME1｜>TD, progresses in the direction of NO, and the time when the power outage occurred and the time when the power outage was restored are respectively TSTOP1 in memory 44 and TSTOP1 in memory 4.
In the arithmetic processing program 54 shown in FIG. 8, the contents of SPRO in the memory 31 for process selection instruction data held during the power outage are used even after the power outage is restored, and normal arithmetic processing is performed.

Next, in the output program 55 of FIG. 9, the sampling time TS that is similarly maintained during the power outage is used, and the data resulting from the arithmetic processing is output at the sampling output time in the output processing 1 of step 89. In the output process 2 of step 91, the time of operation stop, that is, the start of a power outage, and the time of operation restoration, that is, the time of power outage recovery, are output.

On the other hand, if an abnormality occurs in the data output device 12, it is immediately detected in step 82 of FIG. 9, and the sampling output time is rewritten to the current time in step 83.

In addition, the time when the abnormality occurred in step 85 is held in TSTOP2 of the memory 46, and the output processing 1 of the arithmetic processing result of step 89 of the data output program 55 by the data output device 12 is not performed in the next program cycle. There is.

That is, until the abnormal state of the data output device 12 is recovered, sampling output will not be performed and calculation processing such as statistics will continue.

In addition, since the sampling output time is rewritten to the current time in step 83 for each program cycle, when the data output device 12 returns to normal, it is immediately determined to be the sampling output time in step 87, and the calculation The results are output to the data output device 12.

Furthermore, in step 95, the data output device 1
In the first program cycle when 2 returns, TSTOP2 of the memory 46 and TSTOP2 of the memory 45, which store the abnormality occurrence time and return time of the data output device 12, are
The contents of TSTART2 are output to the data output device.

In this embodiment as described above, when the processing device 1 determines that an abnormality has occurred in the data output device 12, the sampling output time detection flag FLAG is set.
3 is "1", that is, output to the data output device 12 is prohibited even if the time when the statistical processing results should be output to the data output device 12 is reached, and while the data output device 12 is in an abnormal state. , Continuing the collection and statistical processing of data regarding elevator operation within the processing device 1, and changing or updating the data value in a predetermined memory area of the memory 9 to the statistical processing data each time an elevator operation signal is collected. Because of this structure, valuable data regarding elevator operation collected and statistically processed while an abnormality occurs in the data output device can be effectively used without wasting it, and it can be continued even in the event of an abnormality in the data output device 12. The memory area that stores this data is rewritten every time an elevator operation signal is collected, and the contents of the same memory area are changed or updated, so data related to elevator operation such as calls can be stored. There is no need to prepare special memory for storing memory 9, and you can use only the capacity of the existing memory 9.
There is no need to increase the capacity.

Furthermore, by storing the abnormality occurrence time and the recovery time of the data output device 12, effective statistical processing data can be immediately output to the data output device when the data output device returns to normal.

In the above embodiment, the sampling output time is determined by adding the sampling time to the current time output of the clock circuit 4, but it is possible to determine the sampling output time by adding the sampling time to the current time output of the clock circuit 4. In the timer circuit, CPU7
Alternatively, a direct interrupt may be applied to the data output device 12 to perform sampling output processing, and this interrupt may be blocked when an abnormality occurs in the data output device 12.

In addition, in a method in which a program is activated by an interrupt signal at predetermined time intervals, when the output value of a program counter that counts every program cycle reaches a predetermined value, the sampling output time is detected, and the data output device 12 It goes without saying that the same effect can be obtained even if this counting operation is stopped when an abnormality occurs.

As described above, according to the elevator data recording device of the present invention, even if a power failure such as a power failure occurs during the elevator data recording operation, the program is automatically started at the time of recovery. Not only is it possible to continue the data recording operation, but when an abnormality is detected in the data output device that stores the results of calculation processing such as statistics, the calculation processing results can be output at the time when they should be output to the data output device. Even if the output device is in an abnormal state, the data output to the data output device is prohibited, and while the output device is in an abnormal state, the collection and statistical processing of data related to elevator operation is continued in the processing device, and the results of the calculation processing are stored. Since the configuration allows the memory area to be rewritten, valuable data collected from the elevator control device can be effectively used without having to secure a new memory area for the collection signal when the data output device stops operating. , calculation results such as statistics output at sampling times are not wasted.

Furthermore, since it is equipped with automatic storage means for the time when an abnormality occurred in the data output device and the time when it returned, it also has the advantage of making post-analysis of recorded data easier.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the elevator data recording device of the present invention, and FIG. 2 is a block diagram showing the configuration of an embodiment of the elevator data recording device of the present invention.
Memory map diagram of RAM-A, Figure 3 is RAM-B in the data recording device of the elevator shown in Figure 1.
4 is an overview of the program stored in the ROM in the data recording device of the elevator shown in FIG. 1, FIG. 5 is a flowchart of the operation preparation program in FIG. 4, and FIG. 4 is a flowchart of the clock initial setting program, FIG. 7 is a flowchart of the operation stop detection program in FIG. 4, FIG. 8 is a flowchart of the arithmetic processing execution program in FIG. 4, 9th
The figure is a flowchart of the data output program in FIG. 4. 1... Processing device, 2... Elevator control device,
3...Data input device, 4...Clock circuit, 5...
Switch circuit, 6...Input circuit, 7...CPU,
8...RAM-A, 9...RAM-B, 10...
ROM, 11...output circuit, 12...data output circuit, 13...power supply device, 14...power supply monitoring circuit, 15...uninterruptible power supply device. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] 1. In a data recording device that is located in an elevator control device and displays or stores the results of collecting and processing various data from the elevator control device, the above-mentioned collection processing or statistical processing is performed every time the above-mentioned data is collected. data processing means for executing and changing or updating data in a predetermined memory area;
A data output means for displaying or storing the output of the data processing means, a detection means for detecting an abnormal operation of the data output means and outputting an output, and the data processing means at predetermined time intervals or arbitrarily settable time intervals. data output control means for outputting data in a predetermined memory area of the data output means to the data output means and for inhibiting output from the data processing means to the data output means while the detection means detects an abnormality in the data output means; The data processing means detects the abnormality occurrence time and abnormality recovery time of the data output means and outputs the detection results to the data output means, and the data processing means detects the abnormality occurrence time and the abnormal recovery time of the data output means, and the data processing means The statistical processing data in the predetermined memory area is set to an initial value, and data regarding the operation of the elevator is continuously collected and processed until the abnormal state of the data output means is recovered. Elevator data recording device.