JPH0145257B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a line setting monitoring device used in a time division multiplex communication device used in earth station equipment for satellite communications.

Communication satellites are generally equipped with multiple transponders (relays), and a single communication frequency band is frequency-wise divided into multiple communication systems, and these are shared among multiple transponders for communication. Although each of these transponders can be used for an independent communication system, it is possible to use multiple transponders simultaneously in one communication system to increase the flexibility of the circuit. , Multi-transponder operation, which improves operational efficiency, is being developed as a new satellite communication technology.

Furthermore, with recent advances in integrated circuit technology, it has become possible to adopt advanced digital communication methods for satellite communication systems, and PCM (Pulse Code
Modulation) – Time division multiplexing equipment using PSK (Phase Shift Keying), or TDMA (Time
Division Multiple Access) is an example of this.
Development is currently underway.

FIG. 1 shows the basic configuration of the above-mentioned TDMA device to which the present invention is applied, and in the same figure, A, B,
C,...N are N low-speed signal inputs, SW is a switching matrix circuit, TR is a transformation circuit, CONT is a demultiplexing control circuit, ,...M are M high-speed multiplexed signal outputs, respectively. are sent to different transponders.

Note that in this specification, "low speed" and "high speed" are relative terms; an example of a low speed signal is a PCM-24ch multiplexed signal (1544MBPS), and an example of a high speed signal is 60MBPS.
The multiplexed signal can be mentioned.

FIG _. 2 shows a typical configuration example of _the transformation circuit TR in FIG. RW is a read/write control circuit, and under the control of this circuit, two switches SW ₁ and SW ₂ are alternately connected to these storage circuits MEM ₁ and MEM ₂ .
They are configured to provide a write input to one and obtain a read output from the other. Each memory circuit MEM ₁ ,
Writing to MEM ₂ is performed at low speed according to the low-speed signal clock CL, but each memory circuit MEM ₁ ,
Reading from the MEM ₂ is performed in a burst manner and at high speed according to the control signal CT. Note that the reverse operation is performed on the receiving side.

Now, if we go back to Figure 1, we can see that this
The TDMA device is for obtaining M high-speed signal outputs from N low-speed signal inputs, and the N low-speed signal inputs are coupled to respective transformation circuits TR, and these storage circuits are connected every frame. while the demultiplex control circuit is configured to be written to
CONT sequentially sends control signals CT to the transformer circuits TR to which they belong, reads out the stored contents, arranges them into high-speed signals, and sends them out.This sent out high-speed signal is made up of
A conventional example of a TDMA frame is as shown in FIG.

In Figure 3, the signal consisting of S, A, and B is
One frame of a low-speed signal is temporally compressed, and is generally called a sub-burst. In other words, a high-speed signal transmitted by one station is called a burst, which usually consists of multiple sub-bursts, and the bursts transmitted by each station are time-division multiplexed to form a TDMA frame. ing.

Therefore, the first earth station temporally compresses and transmits the synchronization signal S and the low-speed signal sequences A, B, ..., and the second earth station similarly transmits S', A', ...Z'. , the third earth station transmits S'', A'', etc. in the same way, and if these are transmitted at timings that do not overlap with each other in the satellite transponder, the result will be a TDMA frame with the configuration shown in FIG. 3.

Figure 4 shows an example of a high-speed signal configuration for multi-transponder operation.
Although TDMA frames are configured, the mutual time relationship may be synchronized or asynchronous.

In addition, each earth station is equipped with a demultiplexing control circuit CONT in 1:1 correspondence with each transponder, . . . M.

On the other hand, the output of the transformation circuit TR is connected to the demultiplexing control circuit CONT via the switching matrix circuit SW, and this connection state can be freely selected by control from the demultiplexing control circuit CONT. It's summery. However, the number N of low-speed signal trains and the number M of high-speed signal trains may have different values for each station.

However, line setting control in a conventional TDMA device uses a transmission control memory and a reception control memory provided in the demultiplexing control circuit CONT, and uses the transmission control memory and reception control memory provided in the demultiplexing control circuit CONT to control the transmission of the While transmitting bursts, the sub-bursts are separated from the bursts sent by each station according to the timing specified by the reception control memory, and controlled to be sent to the designated transformation circuit. There is no monitoring to determine whether or not the error occurred, so even if an incorrect connection is made due to a malfunction of the transmission control memory or reception control memory, or an error in inputting information to the transmission control memory or reception control memory, this error will not occur. This results in serious defects that cannot be detected at all.

The present invention has the purpose of fundamentally eliminating such drawbacks, and adds a first identification code unique to each of the N transformer circuits to the subburst transmitted by that transformer circuit, and In the demultiplex control circuit,
When combining these sub-bursts into a burst, a unique second identification code is added to the multiplexing circuit, and each demultiplexing control circuit is equipped with the conventional transmission control memory and reception control memory. In addition, a line matching memory is provided to store first and second identification codes corresponding to each received subburst, and the first and second identification codes included in the received burst and subburst are separated. The contents of the line verification memory shall be compared with the contents of the line verification memory, and if they do not match, an alarm shall be sent out.If an incorrect connection is made due to circuit malfunction or human error, this error shall be detected and corrected. The present invention provides an extremely effective line setting monitoring device that can prevent connections and dramatically improve communication reliability.

The details of the present invention will be explained below with reference to FIG. 5 and subsequent figures showing embodiments.

Figure 5 is a block diagram showing the transmitting side of the transformer circuit.
Figure 6 is a block diagram of the demultiplexing control circuit, Figure 7 is a block diagram showing the receiving side of the transformation circuit, Figure 8 is a configuration diagram of the high-speed signal frame sent out by the transmitting side of the transformation circuit, and Figure 9 is the demultiplexing circuit. FIG. 10 is a configuration diagram of a high-speed signal frame sent out by the control circuit, and is an explanatory diagram of a state in which bursts transmitted by each station are time-division multiplexed.

Here, the transformation circuit TR in FIG.
The multiplexing/demultiplexing control circuit CONT shown in the figure is also connected via the switching matrix circuit SW as shown in Fig. 1, and in Fig. 5,
MEM ₁ and MEM ₂ are storage circuits, each of which has a capacity to store information for one TDMA frame of low-speed input signals, and RW is a read/write control circuit, which controls two switches. _SW1 ,
SW ₂ is alternately connected to the memory circuits MEM ₁ and MEM ₂ , and the circuit is configured such that a write input from the input Ain is given to one, and a read output is obtained from the other. Further, writing to each memory circuit MEM ₁ and MEM ₂ is performed at low speed according to the clock CL of the low speed symbol, but reading from each memory circuit MEM ₁ and MEM ₂ is performed in a burst manner and according to the control signal CT. It is done by high speed. Switch SW ₂ is a memory circuit
After reading the contents of MEM ₁ and MEM ₂ at high speed, connect the output of the parallel-serial transformation circuit PS to the output A _put , and read the first identification code P _A given as a parallel signal at the same speed as the high-speed signal train. Add as serial data.

FIG. 8 is an explanatory diagram of the sub-burst sent out from the output A _put , where A is the memory circuit MEM ₁ ,
The part where the contents of MEM ₂ were read at high speed, P _A
indicates the part to which the first identification code is added as high-speed serial data, and P _A is, for example, a transformer circuit.
A binary number corresponding to the position on the communication system where TR is performed is given, and the sub-burst constituted by these is sent to the multiplexing/demultiplexing control circuit CONT via the switching matrix circuit SW shown in Fig. 1.
given to.

In Figure 6, the aforementioned sub-burst is given as input 1 to the demultiplexing control circuit CONT, where MUX is the multiplex control circuit, SCR is the scrambler, MOD is the modulation circuit,
TX TMG is the transmission timing generation circuit, TX
MEM transmission control memory, SYNC GEN is a synchronization signal generation circuit, CNT is a control circuit, BST SYNC is a burst synchronization control circuit, ACQ is an initial connection control circuit,
DEM is the demodulation circuit, SYNC DET is the synchronization signal detection circuit, FRM SYNC is the frame synchronization control circuit,
DSCR is a descrambler, RX MEM is a reception control memory, RX TMG is a reception timing generation circuit,
DEMUX is a separation control circuit, and STN MEM is a line matching memory.

Here, the transmission timing generation circuit TX
The TMG is a multiplex control circuit based on the transmission line connection information stored in the transmission control memory TX MEM.
Sends control signal 2 via MUX and accepts sub-burst 1 from designated transformer circuit TR. Further, the synchronization signal generation circuit SYNC GEN generates a synchronization signal generated based on the timing signal 3 sent by the transmission timing generation circuit TX TMG and a second identification code S set in each demultiplexing control circuit CONT. _N to the multiplex control circuit MUX at a high speed signal rate. multiple control circuit
The MUX combines the sub-bursts received from the plurality of transformation circuits TR with the synchronization signal and second identification code S _N given from the synchronization signal generation circuit SYNC GEN, and sends the synthesized signal to the scrambler SCR. The scrambler SCR performs necessary scrambling, which is modulated by the modulation circuit MOD and sent out as burst 4.

Figure 9 shows an example of burst 4, A, P _A
is the sub-burst sent out by the transformer circuit TR _A in Figure 1, B and P _B are the sub-bursts sent out by the similar transformer circuit TR _B , S is the synchronization signal, S _N is the second identification code, and each station The bursts to be transmitted are controlled so that they do not overlap each other in the satellite transponders, and are time-division multiplexed as shown in FIG.

In Figure 10, S, A, P _A , B, P _B , S _N
are the bursts transmitted by the first earth station, S′, A′,
P _A ′…Z′, P _Z ′, S _N ′ are the bursts transmitted by the second earth station, and S″, A″, P _A ″, S _N ″ are the bursts transmitted by the third earth station. , the signals shown in the same figure are applied to the multiplexing/demultiplexing control circuit CONT at each station as the received signal 5 in FIG.

After this received signal is demodulated by the demodulation circuit DEM, it is given to the synchronization signal detection circuit SYNC DET and the descrambler DSCR. Detects the burst synchronization signal, works with the frame synchronization control circuit FRM SYNC and the burst synchronization control circuit BST SYNC, establishes the reception timing as a frame synchronization state, sets the burst synchronization state, and synchronizes the burst transmitted by the own station. The timing is controlled so that the bursts transmitted by other stations and the bursts on the satellite do not overlap with each other.

The initial connection control circuit ACQ controls the initial connection, and the control circuit CNT controls the disconnection,
It controls overall operations such as frame synchronization and burst synchronization, but since the synchronization operations are not particularly related to the present invention, detailed description thereof will be omitted.

On the other hand, the reception timing generation circuit RX TMG is
Based on the reception line connection information stored by the reception control memory RX MEM, the separation control circuit DEMUX
The control signal 8 is sent from the specified transformation circuit.
Control is performed so that the received signal 7 is sent to the TR. In addition, the received signal 9 is transmitted to the line matching memory STN MEM.
In the same memory STN MEM, the second
In response to the control signal 10 specifying the timing of the identification signals S _N , S _N ′, S _N ″, the same memory
The second identification code corresponding to each burst stored in the STM MEM is compared with the second identification code S _N , S _N ′, S _N ″ in the received signal 9, and it is determined that they match. If not, an alarm ALMS is sent to the outside.

Note that the line matching memory STN MEM checks the demultiplexing control circuit CONT to which it belongs when setting up the line.
For the transformation circuit TR connected to
The first identification code P to be received by the TR is sent out and set in the corresponding transformation circuit TR.

In FIG. 7, MEM ₁ and MEM ₂ are memory circuits, each having a capacity to store information for one TDMA frame of a low-speed input signal, and RW is a read/write control circuit. , received sub-bursts A, B, shown in FIG.
A specified one from A'...Z', A'' is written to the memory circuits MEM ₁ , MEM ₂ in a high-speed burst, and the first identification signal following this sub-burst is written. is written to the latch circuit LAT2. That is, for example, when A' is written to the memory circuits MEM ₁ and MEM ₂ , P _A ' is written to the latch circuit LAT2.

Note that the memory circuits MEM ₁ and MEM ₂ are controlled so that when one is in the write state, the other is in the read state, and reading from each memory circuit MEM ₁ and MEM ₂ is controlled by the low-speed signal clock CL. , and at a correspondingly low speed.

In addition, the latch circuit LAT1 has a
Line matching memory STM of demultiplexing control circuit CONT
From MEM, the first signal to be received by this transformation circuit TR
The identification code P is given and written,
This code and the first identification code based on the received signal written in the latch circuit LAT2 are connected to the comparison circuit.
COMP compares and verifies, and if there is a mismatch, an alarm ALMP is sent to the outside.

As is clear from the above explanation, according to the present invention, when the contents of the transmission control memory or the reception control memory and the contents of the line verification memory are inconsistent due to circuit malfunction or human error, in other words, the wrong line If a connection is made, an alarm is sent out, which makes it possible to detect incorrect connections, completely preventing incorrect connections from being left unattended, and dramatically improving communication reliability. This provides a significant effect in TDMA devices.

[Brief explanation of drawings]

Fig. 1 is a basic configuration diagram of a TDMA device to which the present invention is applied, Fig. 2 is a block diagram showing a conventional example of a transformer circuit, Fig. 3 is an explanatory diagram showing a conventional example of a TDMA frame, and Fig. 4 is a multi-channel diagram. An explanatory diagram showing a TDMA frame of transponder operation. Figures 5 and after show embodiments of the present invention. Figure 5 is a block diagram showing the transmitting side of the transformer circuit. Figure 6 is a block diagram of the demultiplexing control circuit. , FIG. 7 is a block diagram showing the receiving side of the transformation circuit, FIG. 8 is a configuration diagram of a high-speed signal frame sent out by the transmission side of the transformation circuit, and FIG. 9 is a configuration diagram of a high-speed signal frame sent out by the demultiplexing control circuit. , FIG. 10 is an explanatory diagram of a state in which bursts transmitted by each station are time-division multiplexed. TR...transformer circuit, CONT...multiplex control circuit, SW ₁ , SW ₂ ...switch, RW...read/write control circuit, PS...parallel-serial conversion circuit, MUX...multiple control circuit, SYNC GEN... ...Synchronization signal generation circuit, DEMUX...Separation control circuit, STN MEM...
...Line verification memory, LAT ₁ , LAT ₂ ...Latch circuit, COMP...Comparison circuit.

Claims (1)

[Claims] 1 Consists of N transformer circuits in which low-speed signals are coupled one-to-one, and M demultiplexing control circuits in which high-speed signals are coupled one-to-one. N) high-speed signals, time division multiplexing, decomposition,
In a multiplex communication device that performs synchronous control, means for adding a first identification code unique to each of the N transformation circuits to subbursts transmitted by the N transformation circuits;
means for adding a second identification code unique to each demultiplexing control circuit to the subbursts transmitted by the M demultiplexing control circuits; a storage circuit for storing two identification codes; a means for separating the first and second identification codes included in each received sub-burst; and the first and second identification codes stored in the storage circuit; A line setting monitoring device comprising means for comparing first and second identification codes separated from a received signal and sending out an alarm if they do not match.