JPH0145765B2 - - Google Patents
Info
- Publication number
- JPH0145765B2 JPH0145765B2 JP14506282A JP14506282A JPH0145765B2 JP H0145765 B2 JPH0145765 B2 JP H0145765B2 JP 14506282 A JP14506282 A JP 14506282A JP 14506282 A JP14506282 A JP 14506282A JP H0145765 B2 JPH0145765 B2 JP H0145765B2
- Authority
- JP
- Japan
- Prior art keywords
- output terminal
- side output
- operational amplifier
- integrated circuit
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000003990 capacitor Substances 0.000 claims description 8
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000002238 attenuated effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H11/00—Networks using active elements
- H03H11/02—Multiple-port networks
- H03H11/24—Frequency-independent attenuators
Landscapes
- Control Of Amplification And Gain Control (AREA)
- Analogue/Digital Conversion (AREA)
- Networks Using Active Elements (AREA)
Description
【発明の詳細な説明】
産業上の利用分野
本発明はＲ−2Rラダー抵抗回路網を用いた可
変減衰回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a variable attenuation circuit using an R-2R ladder resistance network.
従来例の構成とその問題点
第１図に、Ｒ−2Rラダー抵抗回路網を用いた
可変減衰回路の従来例を示す。Configuration of a conventional example and its problems FIG. 1 shows a conventional example of a variable attenuation circuit using an R-2R ladder resistance network.
第１図において、１は内部にＲ−2Rラダー抵
抗回路網および2R側抵抗の一端をホツト側出力
および接地側出力に切換えるためのスイツチ列S1
〜S7を含む集積回路、２，３，４はそれぞれ上記
集積回路１の入力端、ホツト側出力端および接地
側出力端、５は外付のオペアンプ、６は帰還抵
抗、７は上記オペアンプの出力端である。 In Figure 1, 1 is an internal R-2R ladder resistance network and a switch row S 1 for switching one end of the 2R side resistor to the hot side output and the ground side output.
An integrated circuit including ~ S7 , 2, 3, and 4 are the input terminal, hot side output terminal, and ground side output terminal of the above integrated circuit 1, respectively, 5 is an external operational amplifier, 6 is a feedback resistor, and 7 is the above operational amplifier's This is the output end.
次に第１図に示すＲ−2Rラダー抵抗回路網を
用いた可変減衰回路の動作を説明する。 Next, the operation of the variable attenuation circuit using the R-2R ladder resistance network shown in FIG. 1 will be explained.
まず、入力端２に加えられた入力信号の信号電
流は、スイツチS1，S2，……S7にそれぞれ1/2、
１／４、……1/27ずつ分流し、それらの電流はスイ
ツチS1〜S7の状態に応じて、ホツト側出力端３ま
たは接地側出力端４に流れる。そのうちのホツト
側出力端３に流れる電流の和を、外付けのオペア
ンプ５と帰還抵抗６で電圧に変換し、出力端７に
出力信号を出す。 First, the signal current of the input signal applied to input terminal 2 is 1/2 ,
The currents are divided by 1/4 , . The sum of the currents flowing through the hot side output terminal 3 is converted into a voltage by an external operational amplifier 5 and a feedback resistor 6, and an output signal is outputted to the output terminal 7.
そこで、第１図の場合、７ビツトのデイジタル
制御信号によつて、スイツチS1〜S7を制御するこ
とによつて、入力信号を所定の割合で減衰または
増強させて出力端７に出力させることができる。 Therefore, in the case of Fig. 1, by controlling the switches S 1 to S 7 with a 7-bit digital control signal, the input signal is attenuated or amplified at a predetermined rate and outputted to the output terminal 7. be able to.
ところで、外付のオペアンプ５は、一般に、入
力オフセツトによる影響は、オペアンプの入力抵
抗が変化する時に、スパイクノイズの形で現れ
る。 By the way, in the external operational amplifier 5, the influence of input offset generally appears in the form of spike noise when the input resistance of the operational amplifier changes.
特に、スイツチS1〜S7の動作が接後断動作をす
る場合には、切換り時のスイツチのON抵抗を介
して、オペアンプ６の正相、逆相入力間がシヨー
トされるため、入力オフセツト電圧が、スイツチ
のON抵抗と帰還抵抗６の比だけ増幅され、非常
に大きなスパイクノイズを発生させてしまうとい
う問題があつた。 In particular, when the switches S 1 to S 7 operate in a connect/disconnect mode, the positive-phase and negative-phase inputs of the operational amplifier 6 are switched through the ON resistance of the switches at the time of switching, so the input There was a problem in that the offset voltage was amplified by the ratio of the ON resistance of the switch and the feedback resistor 6, causing extremely large spike noise.
発明の目的
本発明は以上の問題を解決し、オペアンプに入
力オフセツトがある場合でも、スイツチの接後断
動作によるスパイクノイズの発生を防止すること
を目的とする。OBJECTS OF THE INVENTION It is an object of the present invention to solve the above problems and to prevent the generation of spike noise due to the connection/disconnection operation of a switch even when an operational amplifier has an input offset.
発明の構成
本発明は、集積回路のホツト側出力端と外付付
けのオペアンプの逆相入力端の帰還抵抗接続点と
の間にコンデンサを接続するとともに、スイツチ
が接地側になつている時に上記コンデンサの集積
回路側に直流電位を供給するためのリーク抵抗
を、集積回路のホツト側出力端と接地側出力端の
間に接続し、上記コンデンサの働きにより、スイ
ツチの変化による抵抗値の変化を阻止し、スパイ
クノイズが発生しないようにしたものである。Structure of the Invention The present invention connects a capacitor between the hot side output terminal of an integrated circuit and the feedback resistor connection point of the negative phase input terminal of an external operational amplifier, and when the switch is on the ground side, the A leakage resistor for supplying DC potential to the integrated circuit side of the capacitor is connected between the hot side output terminal and the ground side output terminal of the integrated circuit, and the function of the capacitor prevents changes in resistance due to changes in the switch. This prevents spike noise from occurring.
実施例の説明
第２図に本発明の一実施例を示す。第２図中で
第１図と同一の部分には同一の番号を付す。DESCRIPTION OF EMBODIMENTS FIG. 2 shows an embodiment of the present invention. The same parts in FIG. 2 as in FIG. 1 are given the same numbers.
第２図の実施例は、第１図の従来例に対し、集
積回路１のホツト側出力端３とオペアンプ５の逆
相入力端の帰還抵抗接続点との間にコンデンサ８
を挿入し、さらに、スイツチS1〜S7が接地側にな
つている時にコンデンサの集積回路１側に直流電
位を供給するためのリーク抵抗９を、集積回路１
のホツト側出力端３と接地側出力端４との間に接
続したものである。 The embodiment shown in FIG. 2 differs from the conventional example shown in FIG.
Furthermore, a leak resistor 9 is inserted between the integrated circuit 1 and the leak resistor 9 for supplying a DC potential to the integrated circuit 1 side of the capacitor when the switches S 1 to S 7 are on the ground side.
It is connected between the hot side output end 3 and the ground side output end 4 of.
第２図に示す実施例では、ホツト側出力端３よ
りIC側を見た抵抗値が、スイツチS1〜S7の動作
により変化した場合でも、オペアンプ５の逆相入
力回路の抵抗値の変化は、コンデンサ８の働きに
より生じないため、第１図に示す従来例のような
スパイクノイズは発生しないという効果がある。 In the embodiment shown in FIG. 2, even if the resistance value viewed from the hot side output terminal 3 to the IC side changes due to the operation of the switches S 1 to S 7 , the resistance value of the negative phase input circuit of the operational amplifier 5 changes. Since this does not occur due to the function of the capacitor 8, there is an effect that spike noise unlike the conventional example shown in FIG. 1 does not occur.
発明の効果
本発明によれば、わずか抵抗１本とコンデンサ
１個を付加するだけで、スイツチの変化による抵
抗値変化を阻止し、スパイクノイズを除去するこ
とができる。Effects of the Invention According to the present invention, by adding just one resistor and one capacitor, it is possible to prevent resistance value changes due to switch changes and eliminate spike noise.
第１図は従来の可変減衰回路の回路図、第２図
は本発明による可変減衰回路の一実施例の回路図
である。
１……集積回路、５……オペアンプ、８……コ
ンデンサ、９……リーク抵抗。
FIG. 1 is a circuit diagram of a conventional variable attenuation circuit, and FIG. 2 is a circuit diagram of an embodiment of the variable attenuation circuit according to the present invention. 1... integrated circuit, 5... operational amplifier, 8... capacitor, 9... leak resistance.
Claims (1)
2R側の各抵抗の一端をホツト側出力端および接
地側出力端に切換えるためのスイツチ列とを集積
回路で構成し、上記集積回路の接地側出力端を外
付けのオペアンプの正相入力端に接続し、上記ホ
ツト側出力端を、コンデンサを介して上記オペア
ンプの逆相入力端に接続すると共に、上記集積回
路内のホツト側出力端および接地側出力端間にリ
ーク抵抗を挿入したことを特徴とする可変減衰回
路。1 R-2R ladder resistance circuit network and the above circuit network
A row of switches for switching one end of each resistor on the 2R side to the hot side output terminal and the ground side output terminal is configured with an integrated circuit, and the ground side output terminal of the above integrated circuit is connected to the positive phase input terminal of an external operational amplifier. and the hot side output terminal is connected to the negative phase input terminal of the operational amplifier via a capacitor, and a leakage resistor is inserted between the hot side output terminal and the ground side output terminal in the integrated circuit. variable attenuation circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57145062A JPS5934718A (en) | 1982-08-20 | 1982-08-20 | Variable attenuating circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57145062A JPS5934718A (en) | 1982-08-20 | 1982-08-20 | Variable attenuating circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5934718A JPS5934718A (en) | 1984-02-25 |
| JPH0145765B2 true JPH0145765B2 (en) | 1989-10-04 |
Family
ID=15376494
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57145062A Granted JPS5934718A (en) | 1982-08-20 | 1982-08-20 | Variable attenuating circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5934718A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05315870A (en) * | 1992-05-07 | 1993-11-26 | Mitsubishi Electric Corp | Information processing unit |
-
1982
- 1982-08-20 JP JP57145062A patent/JPS5934718A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5934718A (en) | 1984-02-25 |
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