JPH0147770B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a camera having a distance measuring device.

Conventionally, various distance measuring devices for measuring the distance to a target object have been proposed.

Broadly speaking, these distance measuring devices can be divided into two types: they convert the incident light from the object into an electrical signal and detect the maximum value of the electrical signal output without using any irradiation light on the object to be ranged. There is a so-called passive method that measures distance, and a projector is installed on the camera side, and the object is scanned while being illuminated with a beam of light from the projector, and the maximum value of the beam reflected from the object is detected to measure the distance. It can be divided into the so-called active method.

For example, in the latter active type distance measuring device, the distance measuring operation is performed by aligning a so-called zone mark, which indicates the range to be irradiated with the beam from the above-mentioned projector provided in the viewfinder, with the subject.

With such conventional distance measuring devices, when using the self-timer, where the photographer is often the subject, it is difficult for the photographer to align the subject, that is, the photographer himself, with the zone mark, and it is difficult for the photographer to align the subject with the zone mark. The target direction of the zone mark was determined by predicting the location of the zone mark.

However, in this method, the subject often deviates from the expected direction, and the beam from the projector deviates from the subject to be distance-measured, making accurate distance-measuring impossible.

Further, even with the former passive type distance measuring device, when using a self-timer, it is difficult to accurately aim at the object to be measured, and a similar problem has occurred.

SUMMARY OF THE INVENTION An object of the present invention is to provide a distance measuring device that is capable of measuring distance with accuracy equivalent to that of normal photography even when photographing using a self-timer.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a configuration diagram of the main parts of a camera having a distance measuring device to which the present invention is applied, in which 1 is a light-receiving element that is normally used during photographing and has sensitivity in the infrared region, 22
5 is a light-receiving element that is used during self-timer photography and has sensitivity in the infrared region; light-receiving elements 1 and 2;
25 is selectively used depending on the shooting mode. 2
24 is a half mirror provided in the light receiving optical path of the light receiving elements 1 and 2; 201 is a light receiving lens disposed in front of the half mirror; 203 is pivotally supported by a shaft 205, and is guided by a cam (not shown) to swing; It is a movable bifurcated scanning lever, and one end of the lever 203 has a light emitting diode 103 shown in the second figure fixed thereto, and the other end has a roller 20 attached to the cam (not shown).
7 is provided. 209 is a spring that gives the scanning reher 203 a clockwise swinging habit; 211 is a light projecting lens disposed in front of the light emitting diode 103;
Reference numeral 213 denotes a photographic lens barrel having a photographic lens optical system therein, 215 a drive spring suspended on the lens barrel 213, 217 a locking claw attached to the outer circumference of the lens barrel 213, and 219 a claw at the tip. 223 is a shaft for the stop pawl 219, and 101 holds the stop pawl 219 in the state shown in the first figure in the initial state. It is a magnet for

FIG. 1A is a diagram for explaining the operation of the portion related to the light receiving element in FIG. 1.

FIG. 1B is an external view of the camera having the distance measuring mechanism shown in FIG.
Reference numeral 3 denotes an operation knob linked to switch _S1 , which will be described later, for switching between self-timer shooting mode and normal shooting mode. Knob 3 in the position shown in Figure 1B.
When set to 03, the camera is set to the Selma timer shooting mode, and when the knob is manually slid to the right, the normal shooting mode is set.
304 is a film winding lever, 309 is a release member, and 213 is the lens barrel shown in FIG.
307 is a finder; 308 is a light receiving window provided in the front of the light receiving lens 201 shown in FIG. 1;
06 is a light projection window provided in front of the light projection lens 211.

FIG. 1C shows a switch mechanism provided in the camera shown in FIG. 1B for switching between the normal shooting mode and the self-timer mode. Knob 303
When is in the position shown in FIG. 1C, the self-timer shooting mode is activated, and the click spring 302
The V-shaped tip falls into the click groove 303b, and the contact pieces S1c and S1a are in contact with each other.
Also, by manually sliding the knob 303 to the right, the normal shooting mode is set, and the V-shaped tip of the click spring 302 falls into the click groove 303c.
The contact piece S1c contacts S1b. That is, in the self-timer shooting mode, S1c and S1a are in contact and the light receiving element 225 is selected as shown in FIG. 1, and in the normal shooting mode, S1c and S1b are in contact and the first
The illustrated light receiving element 1 is selected. Matatsumami 303
There is a switch (not shown) linked to the
When the self-timer photographing mode is selected, a self-timer circuit (not shown) is selected and the circuit is configured to operate during photographing. Furthermore, the arrangement relationship between the light receiving element 225 and the light receiving element 1 described above will be explained in detail using FIG. 1A. The light receiving element 1 and the light receiving element 225 are constructed as shown in FIG. 1A. The light receiving element 1 is a light emitting diode 103 for projecting light.
The light receiving lens 201 and the half mirror 22
4, and the light receiving element 225 receives the reflected light from the light receiving lens 201 and the half mirror 224, respectively. Further, the distance from the center of the half mirror 224 to the light receiving element surface is D2 in the case of the light receiving element 1, and D1 in the case of the light receiving element 225, so that D1>D2. Therefore, the optical path length from the center of the light-receiving lens to the light-receiving element surface is longer up to the light-receiving element 1 than to the light-receiving element 225, and the object of the light-receiving element 225 is smaller than the angle at which the object of the light-receiving element 1 is viewed (solid line). The angle (dashed line) that looks at is larger. That is, in the self-timer shooting mode, the angle at which the light receiving element 225 looks at the subject (also referred to as the scanning area) is the same as the angle during normal shooting (also referred to as the scanning area).
It is designed to be larger.

FIG. 2 is an electrical circuit connection diagram of the camera distance measuring device used in FIG. The light receiving circuit A is connected between the input terminals of the operational amplifier 3, and the light receiving elements 1 and 225, which are provided at predetermined positions in the camera and selected by the switch _S1 , and the amplifier. 3, and a resistor 9, one end of which is connected to the connection point of the resistors, and the other end of which is connected to the capacitor 11. The resistance values of these resistors 5, 7, and 9 and the capacitance of the capacitor 11 are selected to increase the gain of the signal frequency near the blinking period of the light emitting diode 103, and suppress the gain of frequencies lower than this frequency. It will be done.

The part surrounded by the dotted line B is an amplification circuit that amplifies the input signal near the frequency, and the amplification circuit B is connected to a capacitor 13 and a resistor 15 that constitute a high-pass filter, as well as to the output terminal of the high-pass filter. It has an operational amplifier 17 having a non-inverting input terminal. Further, the amplifier circuit B further includes the amplifier 17.
A resistor 19 connected to the feedback path of the resistor 19 and the resistor 19
and a resistor 21 connected to a connection point with the inverting input terminal of the operational amplifier 17. The part surrounded by the dotted line C is a synchronous detection circuit for sampling and holding the output signal from the amplification circuit B in response to a synchronization signal, which will be described later. Analog switch 2 formed by analog switch
3, 25, two AND gates 27, 29 having output ends connected to the control electrodes of the analog switches 23, 25, resistors 31, 33, voltage holding capacitors 35, 37, and the capacitor 3.
5, a second follower circuit 41 connected to the output end of the capacitor 37, and an inverting input terminal connected to the output end of the follower circuit 41 via a resistor 43. and a resistor 47 connected to the feedback path of the amplifier 45. In addition, 43 above,
The circuit formed by 45 and 47 uses the level of the output signal of the follower circuit 41 as a calculation reference level.
It forms an inverter that inverts KVC with a gain of 1. The part surrounded by the dotted line D is a pseudo compression circuit that amplifies the low level output signal and compresses the high level output signal of the output signal of the synchronous detection circuit C, and the pseudo compression circuit D is a reference signal. Resistors 49, 51 for determining the potential, and the resistors 49,
an operational amplifier 53 having a non-inverting input terminal connected to the output terminal of the voltage dividing circuit formed by 51; and a resistor 5 connected between the output terminal and the inverting input terminal of the amplifier 53.
5, a PNP transistor 59 having an emitter connected to the output terminal of the amplifier 53 via a resistor 57, and resistors 61, 63, 65.

The part surrounded by the dotted line E is a low-pass filter connected to the output terminal of the pseudo compression circuit D in order to remove noise components asynchronous to the synchronization signal and remove the synchronization signal components. has a resistor 67 and a capacitor 69 connected between the resistor 67 and ground.

The part surrounded by the dotted line F is a peak detection prohibition circuit for prohibiting the operation of a peak detection circuit G, which will be described later, when the output signal of the low-pass filter E is below a predetermined value. a first input terminal connected to the output terminal of a voltage dividing circuit formed by the resistors 71 and 73, and a second input terminal connected to the output terminal of the low-pass filter E; The comparator 75 has a comparator 75 and a NAND gate 77. The part surrounded by the dotted line G is the peak detection circuit, and the detection circuit G includes an operational amplifier 79 having a non-inverting input terminal connected to the output terminal of the low-pass filter, and the amplifier 79.
a diode 81 having an anode connected to the output end of the diode 81 and a resistor 83 connected to the diode 81;
A capacitor 85 connected to the cathode of the amplifier 79 and an inverting input terminal of the amplifier 79, and a resistor 87
connected in parallel to the capacitor 85 via
It has an NPN transistor and a resistor 91 connected to the base of the transistor 89 and the output terminal of the NAND gate 77 of the inhibition circuit F.

The part surrounded by dotted line H is magnet 1, which will be described later.
The drive circuit H includes NAND gates 93 and 95 forming a latch circuit and an NPN transistor having a base connected to the output end of the latch circuit via a resistor 97. There is. Reference numeral 101 denotes a magnet that is linked to a distance measurement mechanism (not shown) in order to complete the distance measurement operation, and when the magnet 101 is de-energized, a locking claw (not shown) prevents the movement of the photographic lens barrel (not shown). It is configured to be stopped.

The part surrounded by the dotted line J is a counter having a binary ripple counter 102.
has an input terminal CK, a reset terminal R and an output terminal.

The part surrounded by the dotted line K is the light emitting diode 1
A drive circuit for driving 03, the drive circuit K
is a NAND gate 105, an NPN transistor 109 having a base connected to the output terminal of the NAND gate 105 via a resistor 107, a resistor 111,
an operational amplifier 113, a PNP transistor 115 connected to the light emitting diode 103, a variable resistor 117 and a low resistor 1 connected between the collector of the transistor 115 and the inverting input terminal of the amplifier 113;
It has 19.

The part surrounded by the dotted line L is a level detection circuit, and the detection circuit L has a NAND gate 121 having an input terminal connected to the output terminal of the comparator 75.

The part surrounded by a dotted line M is a frequency divider circuit connected to the output terminal of an oscillation circuit N, which will be described later, and a second D-type flip-flop circuit 12 constituting the frequency divider circuit M.
The output terminal of 5 is connected to one input terminal of the AND gate 27, and the output terminal Q thereof is connected to one input terminal of the AND gate 29. Further, the output terminal of the third D-type flip-flop circuit 127 constituting the frequency dividing circuit M is connected to the other input terminal of the AND gate 29, and the output terminal Q
is connected to the other input terminal of the AND gate 27.

The part surrounded by the dotted line N is an oscillation circuit including an oscillator 133 whose output terminal is connected to the clock input terminal CK of the D-type flip-flop circuit 123.

135 is a start switch whose one end is grounded and is opened at the start of the ranging operation; 137 is a switch interface circuit; 139 is an input terminal connected to the start switch 135 via the switch interface circuit 137; AND gate 1 connected to the output terminal Q of the D-type flip-flop circuit 131, which is the output terminal of the circuit M;
41 is a limit switch whose one end is grounded and which is switched from an open state to a closed state when the light emitting diode 103 scans an object present at a predetermined distance, for example, 5 [m]; 145 is a switch interface circuit 143; 147 is an inverter connected to the output of the switch interface circuit 143.

Next, the operation of the camera distance measuring device according to the above configuration will be explained using FIG. 1, FIGS. 1A to 1C, and FIG. Let me explain the case.

When the release member 309 shown in FIG. 1B is pressed, a self-timer circuit (not shown) is activated.
Start switch 135 after a predetermined time has elapsed since pressing
and limit switch 141 is closed. Start switch 135 is closed and limit switch 141 is closed.
When the power switch (not shown) of the ranging device is turned on in the initial state where the
A predetermined voltage is generated at the voltage supply end KVC which generates an output voltage that is more stable than VBAT and the output voltage of the supply VBAT.

When the power switch is turned on and the start switch 135 is closed as described above, the potential at the output terminal of the switch interface circuit 137 becomes a low level (hereinafter abbreviated as LL), so the output of the AND gate 139 The potential at the end is also LL,
Further, the potential at the output terminal of the NAND gate 105 becomes a high level (hereinafter abbreviated as HL), and the transistor 109 becomes conductive. Therefore, the transistor 115 remains non-conductive, and the light emitting diode 103 that generates infrared rays remains off.

As mentioned above, when the light emitting diode 103 does not light up, there is no reflected light from the subject (not shown), so the light receiving circuit A generates almost no signal, and as a result, the output terminal of the low pass filter E The potential of is also the DC level when there is no signal. The potential of the low-pass filter E at this time is the resistor 71, 7
3, the potential at the output end of the comparator 75 becomes LL, and the potential at the output end of the NAND gate 77 becomes HL. When the potential at the output end of the NAND gate 77 becomes HL, the transistor 89 becomes conductive, the operation of the peak detection circuit G is prohibited, and the potential at the output end of the operational amplifier 79 becomes HL. At this time, since the potential at the output end of the switch interface circuit 143 is HL, the potential at the output end of the NAND gate 145 becomes LL as soon as the potential at the output end of the amplifier 79 reaches HL as described above. Reset. Since the potential at the output end of the counter 102 becomes HL due to the above-mentioned reset, the potential at one input end 95a of the NAND gate 95 constituting the latch circuit also becomes HL. Meanwhile, at this time Nand Gate 12
The potential at the output end of the NAND gate 95 is at HL due to the open state of the limit switch 141, and the potential at the third input end 95c of the NAND gate 95 is at HL due to the power up clear signal generated by turning on the power switch. HL, the output state of the latch circuit is reliably held in response to the reset of counter 102, and transistor 99
remains conductive, and the excitation current continues to flow through the magnet 101 via the transistor 99. Therefore, the distance measuring mechanism of the camera is maintained in the initial state as shown in the first diagram.

When the start switch 135 is opened in such a state, the output terminal potential of the switch interface circuit 137 is inverted to HL, so that the AND gate 1
39 opens and closes in synchronization with a drive signal as shown at MA in the third figure (the drive signal indicates the output signal at the output terminal MA of the frequency dividing circuit M in the second figure). When the AND gate 139 opens and closes at the above-mentioned timing, one input terminal of the NAND gate 105 responds to the power-up clear signal.
Therefore, the NAND gate 105 opens and closes in response to changes in the output terminal potential of the AND gate 139, and the light emitting diode 103 opens and closes in response to changes in the output terminal potential of the AND gate 139.
It repeats blinking at a timing synchronized with the opening and closing of the AND gate 139 as shown in A.

Meanwhile, in synchronization with the opening of the start switch 135, the scanning lever 203 shown in the first figure begins to swing clockwise, the light emitting diode 103 blinks and scans the subject, and the lens barrel 213 is moved by the spring 21.
5, the light emitting diode 103 retreats from the close position to the position corresponding to the infinite position with a slight delay from the start of scanning of the light emitting diode 103. When the beam light from the light emitting diode 103 hits a subject (not shown) including the photographer through the scanning, the beam light reflected by the subject passes through the first illustrated light receiving lens 201 to the light receiving circuit A. It is incident on the light receiving element 225, and at the output terminal 3A of the light receiving circuit A, low frequency components related to light such as sunlight and electric lights are suppressed, and the level thereof gradually increases as shown in 3A of FIG. A waveform signal appears. Among the signals appearing at the output terminal 3A of the light receiving circuit A, signals mainly having frequency components near the blinking frequency of the light emitting diode 103 are amplified by the amplifying circuit B, and then supplied to the respective input terminals of the analog switches 23 and 25. Ru. The waveform of the signal appearing at the output terminal 17A of the width increasing circuit B is shown as 17A in FIG.

On the other hand, the control signal input terminal of the analog switch 23 is supplied with a synchronizing signal as shown at 29A in FIG. 3 from the frequency dividing circuit M via an AND gate 29, and the control signal input terminal of the analog switch is given a synchronizing signal as shown at 27A in FIG. , sampled by the analog switches 23 and 25, and held by the subsequent hold circuit. Therefore, in response to the scanning of the light emitting diode 103, the output terminal 39A of the follower circuit 39 has the output terminal 39A shown in FIG.
A signal with a waveform as shown in A appears, and the light emitting diode 1 appears at the output terminal 45A of the inverter 45.
In response to the scanning of 03, a signal with a waveform as shown at 45A in FIG. 4 appears. At the output terminals 39A and 45A of the synchronous detection circuit C, an output signal as described above appears in response to the scanning of the light emitting diode 103, but when the level of the output signal is low and the transistor 59 is cut off, the output terminal 39A
The output signal appearing on is -55R/61R times (however, 55R
indicates the resistance value of the resistor 55, and 61R indicates the resistance value of the resistor 61), and the output terminal 45
The output signal appearing at A is -55R/63R times (however,
63R indicates the resistance value of the resistor 63) and appears at the output terminal 53A of the compression circuit D.

Then, the input signal to the pseudo compression circuit D gradually increases as shown at 39A or 45A in FIG. Since the output current of the amplifier 53 begins to flow not only through the resistor 55 but also through the resistor 57 and the emitter and collector, which are the main electrodes of the transistor 59, as shown at 53A in FIG. The output of the compressor 53 is gradually compressed when the input signal level of the compression circuit D exceeds a predetermined value. The degree of compression can be adjusted by selecting the resistance ratio between the resistor 55 and the resistor 57. Of the signal appearing at the output terminal 53A of the pseudo compression circuit D, the sampling frequency component and the noise component asynchronous to the sampling frequency are removed by the low-pass filter E, and the signal of the other components, that is, the signal 69A in FIG. 4 is removed. A signal as shown by is supplied to the non-inverting input terminal of the amplifier 79, which is the input terminal of the peak detection circuit G.

By the way, when the output signal level of the low-pass filter E is lower than the divided voltage of the voltage dividing circuit connected to the input terminal (-) of the comparator 75, the potential of the output terminal 75A of the comparator 75 is as shown in FIG. As shown in 75A, since the LL state is maintained, the NAND gate 77 is opened in synchronization with the opening of the start switch 135.
Even if the potential at the input terminal 77a of is inverted to HL,
At this point, the output potential of NAND gate 77 is HL
, and the transistor 89 remains conductive. Then, in response to the above-described scanning of the light emitting diode 103, when the output potential of the low-pass filter E exceeds the divided voltage of the voltage dividing circuits 71 and 73, the potential of the output terminal 75A of the comparator 75 has the waveform shown in FIG. As shown at 75A, the state is suddenly reversed from LL to HL, and the transistor 89 is reversed to a non-conductive state, allowing the peak detection circuit G to perform the peak detection operation. When the peak detection operation becomes possible, the potential at the output end 79A of the amplifier 79 rises in accordance with the rise in the potential at its input end, and the terminal voltage of the capacitor 85 increases as the potential at the output end 79A rises. rises following. The potential at the output terminal 79A of the amplifier 79 rises even after the transistor 89 is inverted to a non-conducting state, but when the potential at the output terminal 69A of the low-pass filter E starts to fall as shown at 69A in FIG. , the capacitor 85 stores the peak value of the input signal due to the action of the diode 81 since the transistor 89 is in a non-conducting state. Therefore, the feedback path of the operational amplifier 79 is cut off, and the voltage difference between the potential at the non-inverting input terminal (+) and the potential at the inverting input terminal (-) becomes very large, which corresponds to the open loop gain of the amplifier 79. The signal is amplified at a large amplification rate, and the potential at the output terminal 79A of the amplifier 79 instantly drops to LL.
That is, the potential at the output terminal 79A of the amplifier 79 drops to LL as soon as the light emitting diode 103 scans the object at a predetermined position. By the way, at this point, the limit switch 141 remains open,
The potential of one input terminal of NAND gate 145 is HL
Therefore, as mentioned above, the peak detection circuit G
When the potential at the output terminal 79A of the NAND gate 145 becomes LL, the output potential of the NAND gate 145 is reversed from LL to HL, so the reset state of the counter 102 is released, and the counter 102 is supplied with the signal from the frequency dividing circuit M via the AND gate 139. Start counting pulses. If the output of the peak detection circuit G does not fall to LL due to noise, but falls to LL due to scanning of the light emitting diode 103, this falling state continues for a predetermined period of time. Therefore, the counter 102 continues to count during that time, and when a predetermined period of time has elapsed, the output terminal of the counter 102 is inverted from HL to LL, the latch circuit is reset, and the output potential of the NAND gate 93 changes from HL to LL.
The transistor 99 is inverted to a non-conducting state. Therefore, the magnet 101 is de-energized, and the stop pawl 219 is rotated to the right by the spring 221 and engages with the lock pawl 217. As a result, the photographing lens barrel 213 is stopped at an appropriate position corresponding to the position of the subject.

On the other hand, as mentioned above, the output of NAND gate 93 is
When inverted from HL to LL, the output of NAND gate 105 is held at HL, so light emitting diode 1
03 is turned off and the distance measuring operation is completely stopped. After the distance measuring operation is stopped, a known shutter control circuit (not shown) is activated, and the photographing operation is completed.

During normal shooting, the self-timer circuit is inactive, and the distance measuring circuit is activated by pressing the release member 309. The operation of the distance measuring circuit is based on the light receiving element 1.
is simply replaced with the light receiving element 225, and the operation is substantially the same as that during self-timer photography, so a description thereof will be omitted.

As described above, according to the present invention, the scanning area when using the self-timer is expanded compared to that during normal shooting, and the probability of accurately capturing the subject increases. It is now possible to improve the performance to a level comparable to that of the time.

[Brief explanation of drawings]

Fig. 1 is a configuration diagram of the main parts of a camera to which the present invention is applied, Fig. 1A is an explanatory diagram of the operation of the part related to the light receiving element shown in the first drawing, Fig. 1B is an external view of the camera shown in the first drawing, and Fig. 1C is Fig. 1B is a schematic diagram of the mode changeover switch mechanism provided in the camera shown in the camera, Fig. 2 is an electrical circuit connection diagram of the distance measuring device of the camera shown in the first drawing, and Figs. 3 and 4 are the circuit diagrams shown in the second drawing. It is a waveform diagram of each part. In the figure, 225... is a light receiving element for self-timer photography.

Claims (1)

[Claims] 1. In a camera that has a self-timer mode and is equipped with an automatic focus adjustment device that measures an image from a part of the screen with a sensor and performs automatic focus adjustment according to the measurement output, the automatic focus adjustment is performed in the self-timer mode. What is claimed is: 1. A camera characterized in that it is provided with a measurement range enlarging means for enlarging the measurement range of an image for image measurement, and that automatic focus adjustment is performed based on a measurement output after a predetermined period of time after a release operation.