JPH0147807B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic load device that can independently and variably control impedance between external connection terminals.

For example, in measuring the output characteristics of solar cells,
While the solar cell is irradiated with sunlight to generate an electromotive force, a load is connected between the output terminals of the solar cell, and the impedance of this load is changed to various values to correspond to each value. , voltage and current characteristics are determined by measuring voltage and current values. Since the illuminance of sunlight varies greatly depending on weather conditions, the above measurements must be carried out quickly in a short period of time, so the impedance of the load must be changed to various values in a short period of time. There is a need for something that can do this, and electronic loads are being used as loads that meet this demand.

In an example of a conventional electronic load device, as shown in FIG.
A large number of FETs 1 (5 in the illustrated example) have self-bias circuits made of bias resistors 2 connected to their sides.
are connected in parallel to form a field effect transistor parallel circuit (hereinafter simply referred to as "FET parallel circuit") 3, and the gate G side of each FET 1 in this FET parallel circuit 3 is connected to the gate voltage supply of the gate voltage control mechanism 4. The terminal 41 is connected to the gate voltage control mechanism 4 so that each bias resistor 2 side in the FET parallel circuit 3
Connect to the ground terminal 42 of the Then, the drain D side of each FET 1 in the FET parallel circuit 3 is connected to one external connection terminal 5, and the bias resistor 2 side is connected to the other external connection terminal 7 via a current detector 6. External connection terminals 5, 7
It is made up of connections between. The external connection terminal 5 and the external connection terminal 7 are respectively connected to output terminals of, for example, a solar cell related to measurement.

By the way, FETs do not necessarily exhibit the same characteristics even if they are of the same standard. For example, as shown by curves M1, M2, and M3 in Figure 2, there are differences in characteristics between elements, so-called variations. , this is remarkable in the low current region. That is, the gate-source voltage V _GS is, for example, V ₁
When , each of the curves M1, M2 and M3
The operating points of the FET are Q1, Q2, and Q3, and the magnitude of the variation in the source current I _S is ΔI _S , and this variation becomes larger as the source current I _S becomes smaller.

For this reason, in order to increase the current value that can flow between external connection terminals 5 and 7,
When a large number of FETs are connected in parallel to operate, the above-mentioned variations may cause certain
There is a risk that an excessive current exceeding the absolute maximum rating will flow through the FET and destroy the FET. To prevent this, bias resistor 2 is connected to the source side of each FET as shown in Figure 1. By using this voltage drop due to bias resistor 2 as a compensation bias voltage between the gate and source, the operating points of each FET shown by curves M1, M2, and M3 can be determined.
Q1', Q2', and Q3' are changed to suppress the variation in the source current I _S at the operating point of each FET to ΔI _S '. And this source current I _S
In order to reduce the variation in the operating curve P determined by the resistance value of the bias resistor 2
The inclination angle of the bias resistor 2 may be made small, and for this purpose, the resistance value of the bias resistor 2 may be made large.

However, the magnitude of the voltage drop due to the bias resistor 2 is determined by the gate voltage control mechanism 4 for each FET.
Since each FET 1 will not operate unless the gate voltage is lower than the gate voltage applied to the gate of FET 1, if the resistance value of bias resistor 2 is made large, the source current I _S that can flow becomes small, and eventually the external connection terminals 5, However, if the object to be measured is a solar cell, there are various voltage and current characteristics, and a wide range of current value tolerance is required. Therefore, it is not possible to measure the voltage-current characteristics of various solar cells with a single electronic load device. On the other hand, in order to increase the current value that can flow between external connection terminals 5 and 7, increase the number of FETs connected in parallel.
It may be possible to reduce the variation by dividing the source current I _S flowing through each FET into smaller parts and increasing the resistance value of bias resistor 2, but such a method would require a considerable number of FETs. This is not a good idea from the point of view of manufacturing costs.

The present invention eliminates the above-mentioned drawbacks, reduces the difference in the source current flowing through each FET, and increases the allowable range of the current value that can flow between external connection terminals while allowing each FET to operate stably. The purpose of this device is to provide an electronic load device that can perform a gate voltage control mechanism connected to the gate side of the effect transistor parallel circuit for controlling a voltage applied to the gate side; and a pair of external connection terminals connected to the self-bias circuit side and the drain side of the field effect transistor parallel circuit, respectively. each self-biasing circuit in the field-effect transistor parallel circuit comprises:
It consists of a bias resistor and a constant voltage characteristic element connected in parallel to the bias resistor and having constant voltage characteristics with respect to the source current.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 3 is a block circuit diagram showing the configuration of an embodiment of the present invention, and the same reference numerals as those shown in FIG. 1 represent the same elements, and the explanation thereof will be omitted. In this example, in the FET parallel circuit 3, a large number of constant voltage characteristic elements having constant voltage characteristics with respect to _the forward current of the source current I _S (for example, A diode group 9 connected in series is connected in parallel to the bias resistor 2 connected to the source S side of each FET 1, and an auxiliary bias resistor 21 is connected in series to the parallel connection of these bias resistors 2 and the diode group 9. Connect to configure a self-bias circuit.

Here, the resistance value of the bias resistor 2 is set to be relatively large, and the magnitude of the current value at the boundary where the diode group 9 exhibits constant voltage characteristics is such that the voltage drop caused by the bias resistor 2 is lower than that of the gate voltage control mechanism 4. The resistance value of the auxiliary bias resistor 21 is set to be within a range smaller than the gate voltage applied to the gate G of each FET 1, and the resistance value of the auxiliary bias resistor 21 is considerably smaller than the resistance value of the bias resistor 2.

According to the above configuration, when, for example, a solar cell is connected between the external connection terminals 5 and 7 and the voltage/current characteristics of the solar cell are measured, the gate voltage control mechanism 4 controls the voltage applied to the gate G of each FET 1. The source current I _S is controlled by changing the voltage, and the voltage value between the external connection terminals 5 and 7 and the current value flowing therebetween are detected by the current detector 8 and the current detector 6, respectively, and the voltage/current characteristics are determined. However, in the self-bias circuit connected to the source S side of each FET 1, a diode group 9 having constant voltage characteristics with respect to the source current I _S is connected in parallel with the bias resistor 2, so gate voltage control is possible. When the gate voltage applied to the gate G side of each FET 1 by mechanism 4 is small, the source current I _S is also small, and when this source current I _S is even smaller than the current value at the boundary where the diode group 9 exhibits constant voltage characteristics. , the voltage drop caused by the bias resistor 2 with a high resistance value becomes an effective bias voltage, and the actual voltage between the gate and source decreases by the magnitude of this bias voltage, thereby changing the operating point of each FET 1. The source current I _S flowing through each FET1
The difference between the two becomes small, and it is possible to prevent the current from flowing concentratedly in a specific element.After that, when the voltage applied to the gate G is increased by the gate voltage control mechanism 4, the source current I _S becomes smaller. grow bigger,
When this exceeds the boundary current value in the diode group 9, the voltage drop across the bias resistor 2 is maintained at a constant value due to the constant voltage effect of the diode group 9, so even if the source current I _S further increases, The increase in voltage drop caused by the bias resistor 2 can be suppressed, and each FET 1 can be operated stably. By providing the auxiliary bias resistor 21, as the source current I _S approaches the large current region, the voltage effect due to the auxiliary bias resistor 21, which could previously be ignored due to its small voltage effect, is reduced. , gradually increases to contribute as a substantial bias voltage, and at this time, the operating point of each FET 1 is determined by the voltage effect of this auxiliary bias resistor 21.
Variations in the source current I _S flowing through the FET 1 are suppressed to a small level, and each FET 1 can be operated stably even in this current region.

By the way, if the source current I _S is a large current, the second
As already shown in the figure, since the variations in each FET 1 are small, the current does not flow concentratedly in a particular FET 1, and therefore the phenomenon of destruction of the FET 1 hardly occurs.

In this way, the source current I _S flowing through each FET 1 in the same device can be varied over a wide range from a small current to a large current while allowing each FET 1 to operate stably. The permissible range of the current value of the measurement object that can be connected to becomes larger, and the selection range of the measurement object that can be measured becomes larger.

In the above description, a constant voltage diode may be used as the constant voltage characteristic element in the self-bias circuit of each FET 1, and in this case, it is sufficient to connect it in the opposite direction to the source current _IS . When the object to be measured is a solar cell, the solar cell usually has an output current of about 4 to 32A.
Since the output voltage is approximately 45 to 350V, approximately 40 FETs 1 are required to constitute the FET parallel circuit 3.

As described above, the electronic load device of the present invention includes a field effect transistor parallel circuit in which a large number of field effect transistors each having a self-bias circuit provided on the source side are connected in parallel, and a field effect transistor parallel circuit connected to the gate side of this field effect transistor parallel circuit. The field-effect transistor parallel circuit comprises a gate voltage control mechanism for controlling a voltage applied to the gate side, and a pair of external connection terminals connected to the self-bias circuit side and the drain side of the field-effect transistor parallel circuit, respectively. Each self-biasing circuit in
The configuration is characterized by consisting of a bias resistor and a constant voltage characteristic element that has constant voltage characteristics with respect to the source current, which is connected in parallel to the bias resistor, so that the difference in the source current flowing to each FET can be reduced. At the same time, it is possible to increase the permissible range of the current value that can be passed between the external connection terminals while stably operating each FET.

[Brief explanation of drawings]

FIG. 1 is an explanatory block circuit diagram showing an example of a conventional device, FIG. 2 is a characteristic curve diagram explaining variations in characteristics of field effect transistors, and FIG. 3 is an explanatory block circuit diagram showing an embodiment of the present invention. It is a diagram. 1... Field effect transistor, 2... Bias resistor, 3... Field effect transistor parallel circuit, 4
... Gate voltage control mechanism, 5, 7 ... External connection terminal, 6 ... Current detector, 8 ... Voltage detector, 9 ...
...Diode group, 21...Auxiliary bias resistor.

Claims (1)

[Claims] 1. A field-effect transistor parallel circuit in which a large number of field-effect transistors each having a self-bias circuit provided on its source side are connected in parallel, and a field-effect transistor parallel circuit connected to the gate side of the field-effect transistor parallel circuit in parallel. The gate voltage control mechanism controls the applied voltage, and a pair of external connection terminals are connected to the self-bias circuit side and the drain side of the field-effect transistor parallel circuit, respectively, and each self-biasing terminal in the field-effect transistor parallel circuit An electronic load device characterized in that the bias circuit includes a bias resistor and a constant voltage characteristic element connected in parallel to the bias resistor and having constant voltage characteristics with respect to a source current. 2. The electronic load device according to claim 1, wherein the self-bias circuit comprises an auxiliary bias resistor further added in series to a parallel circuit of the bias resistor and the constant voltage characteristic element.