JPH0147906B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a nonvolatile memory using an MIS transistor, and in particular, an offset region is provided between a drain diffusion layer and a region directly under a gate electrode to concentrate an electric field there. The present invention relates to a structure of a nonvolatile memory that stores information by injecting high-energy electrons generated by causing the offset region to rise into an electron storage region formed above the offset region.

Furthermore, the present invention arranges a drain electrode so as to cover the upper part of the electron accumulation region formed above the offset region, and utilizes the positive potential of the drain electrode to efficiently collect high-energy electrons generated in the offset region. It is often characterized by injection into the accumulation area.

Traditionally, non-volatile solid-state memory
Two types of MIS transistors have been mainly used: floating gate MIS transistors (FAMOS) and MNOS transistors that use nitride-oxide interface states.
The FAMOS type has a double gate structure, and its disadvantages are that because of the double gate, the conductance of the transistor cannot be improved and the access time cannot be improved, the step at the gate is large, and the Al wiring is easily disconnected. It is difficult to shorten the channel, and ultimately it is impossible to miniaturize it, so it is difficult to achieve large capacity.
Moreover, the manufacturing process was complicated and the yield was low. In addition, in the MNOS type, since the carrier passes through the oxide film through a tunnel, it is difficult to form a very thin oxide film, and at the same time, the retention characteristics are poor, making manufacturing difficult.

The present invention was made in view of the above situation, and an object of the present invention is to provide a method that enables a nonvolatile memory to have a larger capacity and faster speed, and is easy to manufacture.

The MIS transistor, which serves as a non-volatile memory used in the present invention, has an offset region between the drain diffusion layer and the gate electrode to cause electric field concentration there, and carriers accelerated by this strong electric field to the trap level above the offset. The ``0'' or ``1'' level of the transistor is determined by trapping it in an accumulation region such as a floating electrode or an equivalent floating electrode.

FIG. 1 shows a specific example of a MOS transistor exhibiting nonvolatile characteristics according to the present invention, in which a silicon nitride film-oxide film interface is used as a trap.
A source diffusion layer N ⁺ 2 and a drain diffusion layer N ⁺ 3 are formed on a P ^- silicon substrate 1, and then a silicon oxide film 5,
After forming the silicon nitride film 6 and the gate electrode 9, a relatively low concentration offset region 4 is formed in the offset portion by ion implantation. After that, an oxide film 7 is deposited, and holes are further opened.
The metal wiring 8 is arranged so as to cover the upper part of the offset. In this transistor, when an appropriate positive bias is applied to the gate electrode 9, the channel is inverted to N, and the carrier electrons flow from the source to the channel, and then to the drain via the offset region 4, as shown in FIG.
A very ordinary VI characteristic as shown in is shown as the initial characteristic. When the drain voltage V _D is increased in this state, the equivalent resistance of the offset region increases with respect to the channel portion, the electric field concentration there becomes intense, and high-energy electrons are finally generated. On the other hand, a drain electrode is arranged above the offset region, and since the drain is positively biased, some of the electrons accelerated in the offset region are accelerated upward and cross the barrier of the oxide film 5 to reach the oxide film 5. -Fill the interface levels of the nitride film 6. As a result, the upper part of the offset region becomes a negative bias, and the offset region inverts P to cut off the current, and only by applying a drain bias ΔV sufficient to cancel this, can the current flow. As a result, the characteristics change as shown in FIG. 5B. It is only when the injection voltage V _D0 is applied that the characteristics shift from A to B. Once shifted to B, the injected charge is retained semi-permanently unless erased by light and acts as a non-volatile memory transistor. I will do it. If ΔV is larger than the read voltage, the transistor is in the OFF state, and "0" and "1" can be detected. Naturally, the method for storing the injected charges is not limited to such interface traps, but may also include providing a rotating layer or using an oxide film with a high trap density (for example, a CVD film).

One key point in the present invention is how to generate electric field concentration in the offset region. Therefore, the offset length _L0 and the dose of ion implantation in the offset region become two major factors. Figure 6 shows this relationship. In order to lower the injection voltage V _D0 and inject efficiently, the offset length L ₀
Although it is better to shorten the distance and use a smaller dose, experimental results show that an effective offset length of 4 μm or less and a dose of 5×10 ¹² /cm ² or less are particularly effective. Also, the transition time of the characteristics is determined by applying the voltage to the drain.
It is fast, less than 50 msec, and to make it even faster, apply as much positive bias as possible to the metal electrode above the offset and thin the total film thickness from the silicon surface to the metal electrode above the offset, especially the oxide film 7. is valid. In this case, the oxide film 5 is 500 Å, the nitride film 6 is 400 Å, and the oxide film 7 is
was 2000 Å, but if the oxide film 7 is locally thinned or not used only above the offset, even higher speed writing becomes impossible.

FIG. 2 shows an example in which this nonvolatile transistor is arranged in a plane in an integrated circuit. gate line 1
0 and 11 are address lines, respectively, and drain extraction electrode lines 19 and 20 are offset parts 12, 13, and 1.
4 and 15 to form a bit line. The source diffusion layers 23, 24 are on the (-) side of the power supply, and the drain diffusion layers 21, 22 are on the contact hole 17,
It is connected to the bit line via 18. Each of the bits 25 and 26 within the dashed-dotted line constitutes one bit.

The non-volatile memory of the present invention has an offset structure, so it has a high punch-through voltage, and therefore can be easily formed into a short channel.As a result, the conductance of the transistor is improved, the access time is greatly improved, and the area can be reduced. Large capacity memory becomes possible.

It does not have a double gate structure like the FAMOS type, so there is no need to worry about the Al wiring breaking due to sudden steps, and the wiring above the gate can be made like the bit line in Figure 2. Moreover, it can be made thinner, so the channel width can be reduced. It is possible to reduce cell size and increase capacity. Furthermore, since the lead line from the drain is routed above the offset, the injection efficiency can be improved as described above.

The oxide film 5 forming the trap interface is MNOS.
The thickness does not need to be several tens of angstroms, but may be several hundred angstroms, so it is easy to manufacture, has few film defects, can improve yield, and has good retention characteristics. Also, since the gate is a single layer, there is no need for complicated processes like the double gate of FAMOS.

As described above, it is an extremely excellent device that allows for larger capacity and higher speed, simplifies manufacturing, improves yield, and has good retention characteristics.

FIG. 3 shows an example of manufacturing a nonvolatile transistor of the present invention. (a) Oxide film 30 on P ^-substrate 39,
A nitride film 31 and further polycrystalline silicon 32 are formed,
The entire surface is doped with phosphorus to form an N ⁺ layer. (b) Thereafter, a gate structure 33 is formed using polycrystalline silicon by a photolithography process, and phosphorus ions are implanted using the resist 34 as a mask to form relatively high concentration source and drain diffusions 35 and 36. (c) Thereafter, phosphorus ions are further implanted at a relatively low concentration over the entire surface to form an offset portion 37.

FIG. 4 shows an example of a step in which the offset region is made shorter. (a) After forming an oxide film 42, a nitride film 41, and a polycrystalline silicon 40 on a P ^- substrate 45, phosphorus is diffused over the entire surface to form source and drain diffusion layers 43 and 44. (b) After that, when thermally oxidized, the oxidation rate of polycrystalline silicon is about an order of magnitude faster in the horizontal direction than in the vertical direction, so an oxide film layer 46 is formed as shown in the figure. (c) After that, when only the oxide film is etched, the length of the polycrystalline silicon 40 is shortened as shown in the figure, and a gap is created between the polycrystalline silicon 40 and the source/drain diffusion layer. In this state, offset portions 47 and 48 can be formed by implanting phosphorus ions into the entire surface. The length of this offset does not depend on the photo process, so a value of around 1 μm can be achieved with good reproducibility.

As described above, the present invention uses a transistor provided with an offset region as a non-volatile memory to achieve larger memory capacity, higher speed, simpler process, and higher yield.
Using this device, 128K bits can be integrated on a 5mm x ¹² chip, and access at this time can be less than 100nsec with respect to the chip select input.

[Brief explanation of drawings]

FIG. 1 shows an example of a cross-sectional view of the non-volatile memory of the present invention, FIG. 2 shows an example of the planar layout of the memory of the present invention on an integrated circuit, and FIGS. Fig. 5 shows the VI characteristics of the device of the present invention, A shows the characteristics before injection, B shows the characteristics after injection, and Fig. 6 shows the dependence on the injection start voltage V _D0 . A graph is shown for each. 5, 7, 30, 42...Oxide film, 6, 31, 4
1... Nitride film, 9, 33, 40... Gate electrode,
8... Metal wiring, 4, 37, 47, 48... Offset region, 10, 11... Gate line (address line), 19, 20... Drain lead line (bit line), 17, 18... Contact hole , △V _D …
...Amount of voltage shift after injection.

Claims (1)

[Claims] 1. In a nonvolatile memory consisting of an MIS transistor, a drain diffusion layer formed in a substrate, a first insulating film formed on the substrate, a gate electrode formed on the insulating film, and a second insulating film formed on the first insulating film; an offset region formed in the substrate between the substrate region directly under the gate electrode and the drain diffusion layer; and a second insulating film formed on the offset region. is formed so as to cover the offset region and the upper part of the accumulation region,
A nonvolatile memory comprising a drain lead wiring for accelerating and injecting charges into the storage region extending to at least the periphery of the gate electrode via the second insulating film.