JPH0148515B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in an electronic watt-hour meter having no mechanical rotating parts.

FIG. 1 shows an example of a conventional electronic watt-hour meter.
The load voltage on the power supply line is reduced by the potential transformer PT to a proportional voltage e _v , and the load current is reduced by the current transformer CT to a voltage proportional to it, equal in absolute value and different in polarity ±e _i . Ru. The pulse width modulation circuit 1 modulates the pulse width using the voltage e _v and outputs the pulse output to the exclusive OR gate 2 . The duty ratio D ₁ of the pulse output is determined according to the formula below.

D ₁ =E _r −e _v /2Er (1) However, Er is the reference voltage.

The output of the exclusive OR gate 2 is applied to a switch driver 3 to control on/off of a changeover switch 4, and is also applied via an inverter 5 to a switch driver 6 to control on/off of a changeover switch 7. Set output terminal Q of RS flip-flop 8 which is one input of exclusive OR gate 2
If the output of is low level, the duty ratio D ₂ of the output of exclusive OR gate 2 is D ₂ = D ₁ , ₂ = 1
-D ₁ , the average value of the input to the integration circuit 9 is determined as the average value of the output of the pulse width modulation circuit 1 over one period.

= e _i ·D ₁ −e _i (1 − D ₁ ) = e _i (2D ₁ −1) If equation (1) is substituted into the above equation, equation (2) is obtained.

=−e _v・e _i /Er (2) Furthermore, if the output of the RS flip-flop 8 is at a high level, the duty ratio D ₂ of the output of the exclusive OR gate 2 is D ₂ =1−D ₁ , ₂ = D ₁ , the average input value of the integrating circuit 9 is expressed by equation (3).

= e _i (1-D ₁ )-e _i・D ₁ = e _i (1-2D ₁ ) = e _v・e _i /Er (3) In this way, the pulse width modulation circuit 1 and the changeover switches 4, 7 forms a multiplier circuit 10 that outputs a signal proportional to the product e _v ·e _i of the voltage e _v and the voltage e _i , and its output, that is, the input of the integrating circuit 9, is connected to the RS flip-flop 8 as shown in FIG. The polarity is reversed depending on the logic level of the output.

The integrating circuit 9 consists of a resistor R, a capacitor C, and an operational amplifier 11, and if the output or inverted output of the multiplier circuit 10 is negative, it integrates in the positive direction; For example, integrate in the negative direction. Comparators 12 and 13 output high-level signals when the output voltage of the integrating circuit 9 is greater than the reference voltage + _ES or less than the reference voltage _-ES , and the signals are passed through buffers 14 and 15 to the set input terminal S of the RS flip-flop 8. Or apply to reset input terminal R.

The output voltage of the integrating circuit 9 fluctuates between the positive and negative reference voltages + _ES and _-ES as shown in FIG _. becomes equation (5).

T=2CREs・Er/e _v・e _i (4) F _a =1/T=e _v・e _i /2CREs・Er (5) From equation (5), the output frequency of RS flip-flop 8
It can be seen that F _a is proportional to the product of voltage e _v and voltage e _i . The amount of power is measured by dividing this output frequency F _a and integrating it with a counter. In FIG. 1, a frequency conversion circuit 16 is formed from the integration circuit 9 to the RS flip-flop 8.
R _L is the secondary load resistance of the current transformer CT. As the changeover switches 4 and 7, field effect transistors or the like are used.

Next, consider the phase difference between voltage e _v and voltage e _i .

e _v = E _V sin ωt e _i = E _I sin (ωt+) where E _V is the maximum value of voltage e _v , E _I is the maximum value of voltage e _i , and is the phase difference between voltage e _v and voltage e _i .

P=e _v ·e _i =E _V ·E _I /2 [cos − cos (2ωt+)] In equation (6), it is the second term that changes with time t. Integrating equation (6), ∫Pdt=∫E _V・E _I /2cosdt −∫E _V・E _I /2cos (2ωt+)dt =E _V・E _I /2cos・t−E _V・E _I /4ω (cossin2ωt + sincos2ωt) (7), and from equation (7), the amplitude of the output of the integrating circuit 9 is
Since E _V・E _I /4ω, if this amplitude is smaller than the reference voltage E _S , the output of the integrating circuit 9 will be much larger than the period of the input of the integrating circuit 9, as shown in Figure 2. It is possible to perform highly accurate measurement even if there is a phase difference between the voltage e _v and the voltage e _i because the voltage is reversed periodically.

However, in the case shown in FIG. 1, the output frequency F _a becomes low as a natural result. Therefore,
It is unsuitable for applications requiring high resolution.
At the same time, it is necessary to increase the CR time constant of the integrating circuit 9, which makes it unsuitable for LSI implementation. The easiest way to solve these problems is to
The goal is to reduce the CR time constant. However,
When the CR time constant is made smaller, if there is a negative power component 17 in the product e _v · e _i as shown in Figure 3, due to the phase difference between voltage e _v and voltage e _i , the integral The output voltage of the circuit 9 rises and falls beyond the range of the reference voltage ± _ES , and the output of the integrating circuit 9 becomes saturated, causing an error. To explain in more detail, when the CR time constant is made smaller, the inversion period of the output of the integrating circuit 9 becomes smaller than the period of the product e _v · e _i , and as a result, the negative power component 17 of the product e _v · e _i Therefore, the output voltage of the integrating circuit 9 is
Even if the reference voltage reaches the same reference voltage again after being inverted at + _ES or _-ES , the output of the RS flip-flop 8 is not inverted, so the switches 4 and 7 are not switched, and the output voltage of the integrating circuit 9 is The voltage rises or falls beyond the reference voltage, and the integrating circuit 9 becomes saturated.
Therefore, the output voltage of the integrating circuit 9 should be shown as a dotted line in FIG. 4, but instead is shown as a solid line, resulting in an error.

In order to prevent the output voltage of the integrating circuit from further rising or falling beyond the reference voltage and becoming saturated as described above, Japanese Patent Application Laid-Open No. 15576/1984 proposes another standard whose absolute value is larger than the reference voltage. A power flow measuring device is disclosed in which the voltage is set and the polarity of the input to the integrating circuit is reversed when the output voltage of the integrating circuit exceeds another reference voltage. It has the disadvantage that the difference with another reference voltage causes an error. In the power flow measuring device described in the above-mentioned published patent publication, the input to the integrating circuit is the average power converted into direct current and does not include an instantaneous negative power component, so the output voltage of the integrating circuit exceeds another reference voltage. The time is only when switching between electricity sales and electricity purchases.
The number of times is small, so the error is tolerable. However, if the technology described in the above-mentioned patent publication is applied to an electronic watt-hour meter in which the input to the integrating circuit includes an instantaneous negative power component, the error described above will occur every time a negative power component occurs. ,
Since it is cumulative, the error becomes unacceptable.

An object of the present invention is to solve the above-mentioned problems, to reduce the CR time constant of an integrating circuit without causing errors, to make it suitable for LSI implementation, and to reduce errors. It is an object of the present invention to provide an electronic watt-hour meter that can determine the polarity of an instantaneous value of the product of load voltage and load current without causing a problem.

Another object of the present invention is to provide an electronic watt-hour meter capable of obtaining a serial pulse signal proportional to average power, that is, a serial pulse signal without polarity indication.

In order to achieve the above object, the present invention includes a frequency conversion circuit that includes a CR circuit, and an integration circuit that integrates the output of the multiplication circuit in a direction according to its polarity.
A first comparator that outputs a pulse signal every time the integral value in the positive direction of the integrating circuit exceeds a positive reference value, and a first comparator that outputs a pulse signal every time the integral value in the negative direction of the integrating circuit exceeds the negative reference value. A second comparator, a reset circuit that resets the integration circuit by the pulse signals of the first and second comparators, and the output level is inverted by inputting the pulse signals of the first and second comparators, and the output level is inverted by the input of the pulse signals of the first and second comparators. A T flip-flop that inverts the polarity of the output of the multiplier circuit in accordance with the inversion of the level, and an input side connected to the output sides of the first and second comparators and the output side of the T flip-flop, and receives a pulse from the first or second comparator. The polarity of the instantaneous value of the product of the load voltage and the load current is determined based on the output level state of the T flip-flop when the signal is output, and the determination result is output as a polarity determination signal to the integration circuit to calculate the negative electric energy. and a polarity discrimination circuit that subtracts the amount of power from the positive power amount, so that when the integration circuit integrates in the same direction as the previous time due to the negative power component, when the integrated value exceeds the same reference value as the previous time, the first or The present invention is characterized in that, at the same time as the second comparator resets the integrating circuit, the T flip-flop inverts the polarity of the output of the multiplier circuit and determines that the output is negative.

Further, an averaging circuit is provided between the frequency conversion circuit and the integration circuit, and when the polarity determination circuit of the frequency conversion circuit determines negative polarity,
A subtraction circuit that counts the pulse signals output by the second comparator, and then subtracts the pulse signals of the first and second comparators when the polarity determining circuit determines positive polarity by the count value when determining negative polarity. , an output control circuit that cuts off the pulse signals of the first and second comparators from the time when the subtraction circuit starts counting the pulse signals when determining negative polarity until the subtraction of the counted value is completed; The present invention is characterized in that the averaging circuit cancels out the pulse signal for negative polarity determination with the pulse signal for positive polarity determination.

Hereinafter, the present invention will be explained in detail based on illustrated embodiments.

FIG. 5 shows a circuit diagram of an embodiment of the present invention. Components similar to those in FIG. 1 are designated by the same reference numerals. A reset circuit consisting of a reset switch 18 and a reset switch driver 19 is provided for the integration circuit 9. Batsuhua 14 and 15 are or gate 20
and the polarity determination circuit 21. On the output side of the OR gate 20 is a reset switch driver 19.
and a single pulse generating circuit 22, and a T flip-flop 23 is connected to the output side of the single pulse generating circuit 22. The output terminal Q of the T flip-flop 23 is connected to one input terminal of the exclusive OR gate 2 and the polarity determining circuit 21. The clock input terminal C of the up-down counter 24 is connected to the single pulse generation circuit 22, and the up-down input terminal U/D is connected to the polarity discrimination circuit 21. A constant multiplication circuit 25 is connected to the output side of the up-down counter 24.

Next, the operation will be explained with reference to the time chart of FIG. When the output of the T flip-flop 23 is at a low level, the integrator circuit 9 receives an average value of -
Similar to the circuit shown in FIG. 1, an input voltage of e _v ·e _i /Er is applied, and if it is at a high level, an input terminal of e _v ·e _i /Er is applied. As long as the product e _v · e _i is positive, first of all, if the output of the T flip-flop 23 is at a low level, the integrating circuit 9 integrates the input voltage in the positive direction, and the integral value becomes the positive reference voltage + E _S When the value exceeds 0, the comparator 12 outputs a high level signal. This signal passes through buffer 14 and OR gate 20 to operate reset switch driver 19, turning reset switch 18 on.
As a result, the charge in the capacitor C is discharged, the integrating circuit 9 is reset, and its output voltage returns to zero potential. At the same time, the signal of the comparator 12 is shaped into a pulse signal of a predetermined pulse width by the single pulse generating circuit 22, and is inputted to the input terminal T of the T flip-flop 23, thereby setting the output level of the output terminal Q to the high level. Therefore, the changeover switches 4 and 7 are switched, and the average input voltage of the integrating circuit 9 becomes e _v ·e _i /Er. Since the output of the comparator 12 becomes low level due to the reset of the integrating circuit 9, the reset switch 18 is turned off again, and the integrating circuit 9 now integrates the input voltage in the negative direction.
When the integral value falls below the negative reference voltage _-ES , the comparator 13 outputs a high level signal, which operates the reset switch driver 19 via the buffer 15 and the OR gate 20, turns on the reset switch 18, and starts integrating. Reset circuit 9.
At the same time, the single pulse generation circuit 22 is operated,
Reset the T flip-flop 23 and switch the changeover switches 4 and 7. As long as this operation is repeated and the product e _v · e _i is positive, the integration circuit 9
The output voltage has a waveform of alternating sawtooth waves. The polarity determining circuit 21 determines the polarity of the product e _v ·e _i using the buffers 14, 15 and the T flip-flop 23, so when it determines that the polarity of the product e _v ·e _i is positive, it outputs a low level signal. The signal is applied to the up-down input terminal U/D of the up-down counter 24 to switch to the addition mode. As a result, the up-down counter 24 is controlled by the single pulse generating circuit 2.
2 pulse signals are counted. Since the frequency of the pulse signal of the single pulse generation circuit 22 is proportional to the product e _v · e _i , the count value of the up-down counter 24 is proportional to the electric energy, and this count value is applied to the constant multiplier circuit 25. It is converted into a numerical value indicating the amount of electric power, displayed, or transmitted to a distant place.

When a negative power component 17 occurs in the product e _v・e _i ,
When the negative power component 17 is input to the integrating circuit 9, the direction of integration of the integrating circuit 9 is reversed from positive to negative or from negative to positive. However, since the integrating circuit 9 is always reset when the integrated value exceeds the reference voltage ± _ES , the integrating circuit 9 does not become saturated and no error occurs. The polarity determination circuit 21 determines that the polarity of the product e _v · e _i is negative and applies a high level signal to the up-down input terminal U/D of the up-down counter 24 to switch to the subtraction mode. 24 subtracts one count from the count value each time a pulse signal is input from the single pulse generating circuit 22. Therefore, the number of pulses proportional to the negative power component 17 is subtracted from the count value of the up-down counter 24, and the accurate amount of power is measured.

The polarity discrimination circuit 21 performs multiplication according to the outputs of the buffers 14 and 15 and the output of the T flip-flop 23.
This is used to determine the polarity of e _v and e _i .
As shown in the figure. 26 is a delay circuit, 27 and 28 are inverters, 29 to 32 are AND gates, 33 and 34 are OR gates, and 35 is an RS flip-flop.
This polarity discrimination circuit 21 detects a T flip-flop 23 immediately before the buffer 14 outputs a high level output.
If the output is low level, the polarity is determined to be positive, and if it is high level, the polarity is determined to be negative. For example, the polarity is determined to be negative, and if it is at a high level, the polarity is determined to be positive. That is, immediately before the buffer 14 outputs a high level output, the integrating circuit 9 is integrating in the positive direction, so the polarity of the average input voltage input to the integrating circuit 9 is negative, and at that time, the polarity of the average input voltage input to the integrating circuit 9 is negative. The output is low level,
Since the average input voltage is _-ev ·e _i /Er, the polarity of the product e _v ·e _i is positive.

In FIG. 7, when the high level output of the buffer 14 is input to the AND gates 29 and 32, the output of the T flip-flop 23 immediately before it is delayed by the delay circuit 26 as shown in FIG. They are input directly to the AND gate 29 and to the AND gate 32 via the inverter 28, so if the output of the delay circuit 26 is low level, the AND gate 32 outputs the high level output via the OR gate 32 to the RS flip-flop. 3
The signal is sent to the reset input terminal R of No. 5 and reset, and the polarity discrimination signal UD is set to low level, and the polarity is determined to be positive. If the output of the delay circuit 26 is at a high level, the AND gate 29 sends a high level output to the set input terminal S of the RS flip-flop 35 via the OR gate 33, sets it, and sets the polarity discrimination signal UD to a high level. ,
Determine the polarity as negative.

When the high-level output of the buffer 15 is input to the AND gates 30 and 31, the output of the T flip-flop 23 immediately before it is delayed by the delay circuit 26, passes through the inverter 27 to the AND gate 30, and then to the AND gate 31. Since they are directly input, if the output of the delay circuit 26 is low level, the AND gate 30 outputs a high level output, sets the RS flip-flop 35, sets the polarity discrimination signal UD to high level, and the delay circuit 26 outputs a high level output. 26 is at a high level, the AND gate 31 outputs a high level signal, resets the RS flip-flop 35, and outputs the polarity determination signal.
Set UD to low level.

The circuit shown in Figure 5 fulfills the function of a watt-hour meter, but it is also useful for calibrating the watt-hour meter.
In order to divide the output pulse signal of the frequency conversion circuit 16 according to the transformation ratio of the instrument transformer PT or current transformer CT, a serial pulse proportional to the average power, in other words, a serial pulse without a polarity indication is used. It is desirable to obtain To this end, as shown in FIG. 9, an averaging circuit 36 is provided between the frequency conversion circuit 16 and an integration circuit 37 consisting of a counter that simply adds pulses. Averaging circuit 36
is the output pulse signal PG of the frequency conversion circuit 16,
That is, the timing control circuit 38 shifts the output pulse signal of the single pulse generation circuit 22 from the timing of the output reversal of the polarity discrimination circuit 21, and the output pulse signal PG at the time of negative polarity discrimination corresponding to the negative power component 17 is counted.
Output pulse signal when positive polarity is determined by this count value
The subtraction circuit 39 that subtracts PG and the output pulse signal PG at the time of negative polarity discrimination start counting until the subtraction of this counted value is completed.
It is formed from an output control circuit 40 that cuts off the PG.

An example of the averaging circuit 36 is shown in FIG. 4
1, 49, 53, 56 are one shot timers synchronized with clock pulse CLK, 42, 51 are 2
Bit shift register, 43, 45, 48, 5
2 is an AND gate, 44 and 46 are D flip-flops, 47 and 50 are RS flip-flops, and 54
is an n-bit up-down counter, and 55 is a NOR gate. The clock pulse CLK has a considerably smaller pulse width and higher frequency than the output pulse signal PG of the single pulse generating circuit 22.

The operation of the circuit shown in FIG. 10 will be explained with reference to the time charts shown in FIGS. 11 and 12. FIG. 12 shows in detail the portion between the dashed lines in FIG. 11. The output pulse signal PG is shaped into a pulse width of 3 clock pulses by a one-shot timer 41, delayed by 2 clock pulses by a shift register 42, and converted by an AND gate 43 into a pulse whose rise is delayed by 2 clock pulses. . Then, the D flip-flop 44 further delays the clock pulse by one clock pulse. On the other hand, the polarity determination signal UD is input to the data input terminal D of the D flip-flop 46. If the polarity determination circuit UD is at a low level, the D flip-flop 46 is activated in synchronization with the rise of the output of the shift register 42.
The output of output terminal Q of is held at low level.
Assuming that the RS flip-flop 47 has been reset in advance, the AND gate 48 is open, so the output pulse signal of the D flip-flop 44 is output as is as the pulse signal PA.

Next, when the polarity discrimination signal UD becomes high level,
The output of the output terminal Q of the D flip-flop 46 becomes high level, and the RS flip-flop 47 is set, so the AND gate 48 is closed and the D flip-flop 46 is set.
The output pulse signal of flip-flop 44 is then cut off. At the same time, AND gate 45 is opened, so the output pulse signal of D flip-flop 44 passes through AND gate 45, is delayed by two clock pulses by shift register 51, passes through AND gate 52, and is sent to the clock input terminal of up-down counter 54. Enter in C. At this time, the up-down input terminal U/D of the up-down counter 54
Since the high level output of the D flip-flop 46 is input to the input mode and the mode is switched to the addition mode, the up-down counter 54 counts the output pulse signal of the D flip-flop 44 at the time of negative polarity determination. In FIGS. 11 and 12, there is only one output pulse signal PG when determining negative polarity, so
The count value is 1. When the polarity discrimination signal UD returns to the low level, the output of the output terminal Q of the D flip-flop 46 becomes low level, and the up-down counter 54 is switched to the subtraction mode. on the other hand,
Since RS flip-flop 47 is not reset, AND gate 48 continues to close and AND gate 45 continues to open. As a result, the output pulse signal of the D flip-flop 44 at the time of positive polarity determination passes through the AND gate 45, the shift register 51, and the AND gate 52, and then goes to the up-down counter 5.
4 and subtract it from the count value. When the count value reaches zero, the NOR gate 55 outputs a high level signal, and when the signal rises, the one shot timer 56 outputs a reset pulse, and the RS flip-flop 47 is reset. Therefore, the AND gate 48 is opened and the AND gate 45 is closed.

When the average value of the product e _v · e _i is negative, or when the negative power component 17 is very large, the count value of the up-down counter 54 in the addition mode becomes large,
There is a risk of overflow and malfunction. To prevent this, the up-down counter 5
When the most significant bit Q _o of 4 becomes high level,
The one-shot timer 53 resets the RS flip-flop 50 and closes the AND gate 52. Next, when the polarity determination signal UD becomes low level, the output from the output terminal of the D flip-flop 46 causes the RS flip-flop 5 to
0 is set, the AND gate 52 is opened, and
Return to normal operation.

The number of bits n of the up-down counter 54 is multiplied by
If the number of output pulse signals PG is set to be larger than the number of output pulse signals PG output in one cycle of e _v · e _i , accurate averaging processing can be performed within one cycle of the product e v _· e _i , and a serial pulse proportional to the average power can be obtained. Also, since this averaging process is all digital processing, it is suitable for LSI implementation.

If there is an offset in the operational amplifier 11 when there is no input, the output voltage of the integrating circuit 9 will be as shown in FIG. 13, and the polarity discrimination signal UD will repeat high and low levels. As a result, the up-down counter 54 alternately repeats addition and subtraction of one count, and the averaging circuit 36 does not output the pulse signal PA. Therefore, it is possible to prevent malfunctions when there is no input, that is, creep, which is a problem in power meters.

Further, in the embodiment shown in FIG. 5, the input is given to the integrating circuit 9 in the form of a voltage, but the input can be given in the form of a current. In that case, the integrating circuit 9 may omit the operational amplifier 11 and may consist only of a resistor R and a capacitor C.

The polarity determination circuit 21 is not limited to the example shown in FIG. 7, and various modifications are possible.

As explained above, the first claim of the present patent application
According to the invention described in section 1, when the integration circuit integrates in the same direction as the previous time due to a negative power component, the first or second comparator resets the integration circuit when the integrated value exceeds the same reference value as the previous time. Since the polarity of the output of the multiplier circuit is inverted using a T flip-flop and the polarity is determined to be negative, the CR time constant of the integrating circuit can be reduced without causing an error, making it suitable for LSI implementation. It is possible to determine the polarity of the instantaneous value of the product of the load voltage and the load current.

Further, according to the invention described in claim 2, the averaging circuit cancels out the pulse signal for negative polarity discrimination with the pulse signal for positive polarity discrimination. A serial pulse signal, that is, a serial pulse signal without polarity indication can be obtained.

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing an example of a conventional electronic watt-hour meter, Figure 2 is a time chart showing its operation,
Fig. 3 is a time chart showing the operation when the CR time constant of the integrating circuit in the electronic watt-hour meter shown in Fig. 1 is reduced, and Fig. 4 shows the part surrounded by the dotted line in Fig. 3 in detail. A waveform diagram, FIG. 5 is a circuit diagram showing an embodiment of the present invention, FIG. 6 is a time chart showing its operation, and FIG. 7 is a circuit diagram showing an example of a polarity discrimination circuit according to an embodiment of the present invention. , FIG. 8 is a time chart showing its operation, FIG. 9 is a block diagram showing an averaging circuit according to an embodiment of the present invention, and FIG.
Figure 0 is a circuit diagram showing an example of an averaging circuit;
FIG. 13 is a time chart showing the operation. 9... Integrating circuit, 10... Multiplying circuit, 12, 13...
Comparator, 16... Frequency conversion circuit, 17... Negative power component, 18... Reset switch, 21... Polarity discrimination circuit, 23... T flip-flop, 24... Up/down counter, 25... Constant multiplication circuit, 36
...Averaging circuit, 37...Multiplication circuit, 38...Timing control circuit, 39...Subtraction circuit, 40...Output control circuit, e _v ...Voltage proportional to load voltage, e _i ...Voltage proportional to load current, R...Resistance , C...capacitor, ±
E _S ...Reference voltage.

Claims (1)

[Claims] 1. Proportional to the instantaneous value of the product of load voltage and load current,
An electronic power consumption system that includes a multiplier circuit that outputs a level signal that includes a negative power component, a frequency conversion circuit that converts the output of the multiplier circuit into a frequency, and an integration circuit that integrates the power amount from the output of the frequency conversion circuit. In the system, the frequency conversion circuit is composed of a CR circuit, and an integration circuit that integrates the output of the multiplication circuit in a direction according to its polarity, and an integration circuit that integrates the output of the multiplier circuit in a direction corresponding to its polarity, and an integration circuit that integrates the output of the multiplication circuit in a direction corresponding to its polarity, and The first one outputs a pulse signal.
a second comparator that outputs a pulse signal every time the integral value in the negative direction of the integrating circuit exceeds a negative reference value, and the integrating circuit is reset by the pulse signals of the first and second comparators. a reset circuit, a T flip-flop whose output level is inverted by the input of the pulse signals of the first and second comparators, and which inverts the polarity of the output of the multiplier circuit in accordance with the inversion of the output level;
The input side is connected to the output side of the second comparator and the output side of the T flip-flop, and the load voltage and load current are determined by the output level state of the T flip-flop when a pulse signal is output from the first or second comparator. and a polarity discrimination circuit that discriminates the polarity of the instantaneous value of the product, outputs the discrimination result as a polarity discrimination signal to the integration circuit, and subtracts the negative electric energy from the positive electric energy. Electronic energy meter. 2 Proportional to the instantaneous value of the product of load voltage and load current,
An electronic power consumption system that includes a multiplier circuit that outputs a level signal that includes a negative power component, a frequency conversion circuit that converts the output of the multiplier circuit into a frequency, and an integration circuit that integrates the power amount from the output of the frequency conversion circuit. In the system, the frequency conversion circuit is composed of a CR circuit, and an integration circuit that integrates the output of the multiplication circuit in a direction according to its polarity, and an integration circuit that integrates the output of the multiplier circuit in a direction corresponding to its polarity, and an integration circuit that integrates the output of the multiplication circuit in a direction corresponding to its polarity, and The first one outputs a pulse signal.
a second comparator that outputs a pulse signal every time the integral value in the negative direction of the integrating circuit exceeds a negative reference value, and the integrating circuit is reset by the pulse signals of the first and second comparators. a reset circuit, a T flip-flop whose output level is inverted by the input of the pulse signals of the first and second comparators, and which inverts the polarity of the output of the multiplier circuit in accordance with the inversion of the output level;
The input side is connected to the output side of the second comparator and the output side of the T flip-flop, and the load voltage and load current are determined by the output level state of the T flip-flop when a pulse signal is output from the first or second comparator. a polarity discrimination circuit that discriminates the polarity of the instantaneous value of the product and outputs the discrimination result as a polarity discrimination signal; an averaging circuit is provided between the frequency conversion circuit and the integration circuit; When the polarity discrimination circuit of the frequency conversion circuit discriminates negative polarity, the first
A subtraction circuit that counts the pulse signals output by the second comparator, and then subtracts the pulse signals of the first and second comparators when the polarity determining circuit determines positive polarity by the count value when determining negative polarity. , and an output control circuit that cuts off the pulse signals of the first and second comparators from the time when the subtraction circuit starts counting the pulse signal at the time of negative polarity determination until the subtraction of the counted value is completed. An electronic power meter featuring the following.