JPH0148564B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a method for generating a debug interrupt during program execution in order to debug a program in an information processing device.

[Prior art]

Conventionally, when debugging a program, control is transferred (hereinafter referred to as dayrail) from the debugged program to be debugged to a program that controls debugging (hereinafter referred to as DU), and the state of the debugged program at the time of the dayrail is transferred to the DU. Methods of investigation have been taken. That is, as shown in FIG. 1a, a part of the debugged program consists of instructions 1 to 5, where instructions 1, 4, and 5 are 2-byte long instructions, and instructions 2 and 3 are 4-byte long instructions. If you want to set the dayrail point immediately before the execution of instruction 3, as shown in Figure 1b, set the dayrail point before instruction 3 by recompiling.
How to embed branch instruction 6 into DU and Figure 1c
There was a method of saving instruction 3 in Figure 1a to the work area 7 of DU, replacing the beginning of instruction 3 with undefined instruction 8, and transferring control to DU by an interrupt caused by a program error. However, in the former method, the branch instruction to DU must be removed by recompilation after debugging is completed, and in the latter method, the instruction 3 saved to the work area 7 under the control of DU must be removed. After execution, to return control to instruction 4,
The disadvantage was that the DU had to manage the addresses.

[Purpose of the invention]

In order to eliminate the above-mentioned conventional drawbacks, the present invention provides an instruction for generating a debug interrupt (hereinafter referred to as a DI instruction) having a specific code. Executes the instruction immediately after without performing any operation, and executes DI.
When an instruction is issued in a debug state, a debug interrupt is generated, and the instruction address stored in memory in response to the interrupt is determined by adding the contents of a predetermined field of the instruction to the address of the DI instruction. It was designed so that it could be obtained easily.

[Embodiments of the invention]

FIG. 2 shows an example of the format of the DI command.
In FIG. 2, 9 is the DI instruction, 10 is the instruction code field of the DI instruction (hereinafter referred to as the F field), and 11 is the first field (hereinafter referred to as R1) used to generate the address of the next instruction to be executed. 12 is a second field (hereinafter referred to as R2 field) used for creating an interrupt code. Below, the length of this DI command is 2
Suppose it is a part-time job.

FIG. 3 shows a processing flow of the debug interrupt method according to the present invention. In the following explanation, the bit indicating whether the program is in a debug state or a normal state and the address of the next instruction to be executed (hereinafter referred to as SCC) are referred to as the program status word (hereinafter referred to as PSW) in the information processing device. ) is held in a register called

Now, the DI instruction 9 in Figure 2 exists at the address specified by the SCC of the PSW, and the information processing device (so-called CPU) decodes the F field 10 of the read instruction and determines that it is a DI instruction. When PSW is detected, if the PSW is displaying the normal state, add the instruction length of the DI instruction (2 in this example) to the SCC and
Finishes execution of the instruction (→→). This results in
The DI instruction, like an instruction generally called a no-operation (NOP) instruction, ends without any involvement in the logic of the program, and the next instruction two bytes after the DI instruction is executed.

On the other hand, DI is sent to the address specified by SCC of PSW.
When instruction 9 exists and the information processing device decodes the F field and detects that it is a DI instruction, the PSW
If the debug status is displayed, the information processing device updates the SCC in the PSW with the value obtained by adding the value of R1 field 11 of DI instruction 9 to that SCC and generates a debug interrupt signal (→→→) . Along with this interrupt, the updated
The contents of the PSW including the SCC are stored as the old PSW at a predetermined memory address ().

The DI instruction whose R1 field value is 2, which is the instruction length of the DI instruction itself, can be used in place of the branch instruction 6 in the conventional debugging method shown in FIG. 1b. In this case, when the debugged program is executed in a debug state, a debug interrupt occurs when the DI instruction at the instruction 6 position is executed. At this time, the contents stored as the old PSW include:
Contains the address of instruction 3 at address +2 of the DI instruction. Along with the interrupt, a new PSW containing the entrance address of the DU is loaded into the PSW (), control is transferred to the DU, and the state of the debugged program after execution of instruction 2 and before execution of instruction 3 is transferred to the DU. can be parsed(). After that, the DU is the old file stored with the debug interrupt.
By loading the PSW into the PSW, control can be returned to instruction 3 of the debugged program (). Note that in debugging using this method, there is no need to recompile to remove the DI instruction after debugging is completed, and the same result as the program in FIG. 1a can be obtained under normal conditions.

For the conventional debugging method shown in Figure 1c, it is possible to use a DI instruction with the instruction length of instruction 3 (4 in this example) as the value of the R1 field instead of undefined instruction 8. can. In this case as well, when the DI instruction at instruction 8 is executed in the debug state, a debug interrupt occurs and the old PSW is stored (). The contents stored as the old PSW at this time include the address of instruction 4 located at address +4 of the DI instruction. When control is transferred to DU due to an interrupt (), DU analyzes the state of the program to be debugged after execution of instruction 2 and before execution of instruction 3 (). After analysis, the DU executes the instruction 3 saved in the work area 7 of the DU (), and loads the old PSW stored with the debug interrupt into the PSW to execute the instruction 4 of the debugged program.
You can return control to (). Since the address of instruction 4 is generated by the DI instruction and stored as part of the old PSW, DU does not need to manage the address of instruction 4.

In addition, by using the R2 field of the DI instruction as is, or by using the contents of the register specified by the R2 field as the interrupt code stored in memory with the debug interrupt, DU can determine the type of day rail etc. from the interrupt code. It is possible to determine. Furthermore, when the value of the R2 field is a specific value (for example, 0), by disabling debug interrupts by DI instructions even in the debug state, some of the multiple DI instructions embedded in the debugged program can be disabled. By setting the R2 field of 0 to 0, it can also be used as a method of inactivating it as a day rail point.

〔Effect of the invention〕

As explained above, according to the present invention, the R1 field of the DI instruction provides a means for setting the instruction address when returning control from the DU to the debugged program in the old PSW at the time of day rail.
This has the effect of reducing the burden on DU. Furthermore, if a debugging method is adopted in which DI instructions are embedded in advance when the target program is generated, there is an advantage that the program to be debugged can be used without recompiling after debugging is completed.

[Brief explanation of drawings]

Figures 1a, b, and c are diagrams explaining the conventional debugging method, Figure 2 is a diagram showing an example of the format of a DI instruction, and Figure 3 is a diagram explaining the conventional debugging method.
The figure is a processing flow diagram of the debug interrupt method according to the present invention. 1 to 6, 8...Instruction, 7...Work area of debug control program, 9...DI instruction.

Claims (1)

[Claims] 1 A debug interrupt method for program debugging that uses a bit in the information processing device to indicate whether the program is in a debug state in which a debug interrupt can occur during program execution or in a normal state in which no debug interrupts can occur. When an instruction with a specific instruction code is issued in the normal state, the instruction immediately following the instruction is executed without performing the operation based on the instruction, and the When an instruction with a specific instruction code is issued in debug state, a debug interrupt is generated and
A debug interrupt method characterized in that an instruction address stored in a memory in response to the interrupt is obtained by adding the content of a predetermined field of the instruction to the address of the instruction.