JPH0148648B2 - - Google Patents
Info
- Publication number
- JPH0148648B2 JPH0148648B2 JP57141809A JP14180982A JPH0148648B2 JP H0148648 B2 JPH0148648 B2 JP H0148648B2 JP 57141809 A JP57141809 A JP 57141809A JP 14180982 A JP14180982 A JP 14180982A JP H0148648 B2 JPH0148648 B2 JP H0148648B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit element
- molded body
- electrode
- synthetic resin
- parallel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000758 substrate Substances 0.000 claims description 27
- 229920003002 synthetic resin Polymers 0.000 claims description 18
- 239000000057 synthetic resin Substances 0.000 claims description 18
- 239000002131 composite material Substances 0.000 claims description 14
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 238000000034 method Methods 0.000 claims description 4
- 238000000576 coating method Methods 0.000 description 7
- 239000011248 coating agent Substances 0.000 description 5
- 238000007639 printing Methods 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 4
- 238000000465 moulding Methods 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 2
- 239000003985 ceramic capacitor Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
Landscapes
- Non-Adjustable Resistors (AREA)
- Coils Or Transformers For Communication (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は複合回路素子およびその製造方法に係
り、例えば、レジスタネツトワークなどの形成に
用いられる複数の抵抗、コンデンサなどの回路素
子片を組込んだものに関する。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a composite circuit element and a method for manufacturing the same. It's about things.
〔発明の技術的背景〕
従来のこの種レジスタネツトワークなどの回路
形成に用いられる複合回路素子はセラミツク基板
の前面に素子被膜例えば抵抗被膜を並列に形成
し、この各抵抗被膜の両端に接続した電極被膜に
導線を半田接続し、全体を絶縁被膜で覆つた構成
が採られている。[Technical Background of the Invention] Conventional composite circuit elements used to form circuits such as this type of resistor network have element films such as resistive films formed in parallel on the front surface of a ceramic substrate, and connected to both ends of each resistive film. The structure is such that a conductive wire is soldered to the electrode coating, and the entire structure is covered with an insulating coating.
従来のこの複合回路素子では基板の前面に抵抗
などの回路素子部を並列に印刷などによつて形成
したため、複数の回路素子部を高密度に形成する
ことができず、また耐湿特性も低く、さらに複数
の各回路素子部が異なる場合例えば異なる抵抗値
の抵抗被膜を形成する場合には複数回印刷の版を
変えて被膜の印刷をなくしてはならず、製造工数
が多く、作業が煩雑で、高価となる欠点を有して
いる。
In conventional composite circuit elements, circuit elements such as resistors were formed on the front surface of the board by printing in parallel, making it impossible to form multiple circuit elements in high density, and the moisture resistance was low. Furthermore, when multiple circuit elements are different, for example, when forming resistive coatings with different resistance values, it is not necessary to change the printing plate multiple times and eliminate printing of the coating, which increases the number of manufacturing steps and makes the work complicated. , it has the disadvantage of being expensive.
本発明は上記欠点に鑑みなされたもので、各回
路素子部を高密度に形成でき、耐湿特性を向上で
き、また種類の異なる回路素子部の形成も作業性
よくでき、安価に得られる複合回路素子を提供す
るものである。
The present invention has been made in view of the above-mentioned drawbacks, and it is possible to form each circuit element part with high density, improve moisture resistance, and form a composite circuit with good workability in which different types of circuit element parts can be obtained at low cost. It provides an element.
本発明は電極部を有する複数の回路素子片を合
成樹脂成形体に埋込み固定し、この成形体端面
に、各回路素子片の回路素子部の露出された電極
部に接続した配線路を形成するとともに導線を接
続してなるものである。
The present invention embeds and fixes a plurality of circuit element pieces each having an electrode part in a synthetic resin molded body, and forms a wiring path connected to the exposed electrode part of the circuit element part of each circuit element piece on the end face of the molded body. It is made by connecting conductor wires to the terminal.
また本発明は複数の回路素子部およびこの回路
素子部に接続した電極部を有する複数の基板を並
列に合成樹脂に埋込み成形し、この成形された合
成樹脂を切断し、この切断した成形体の端面に各
基板の切断によつて形成された回路素子片の露出
された電極部に接続した配線路を形成するととも
に導線を接続してなるものである。 In addition, the present invention involves embedding and molding a plurality of substrates having a plurality of circuit element parts and electrode parts connected to the circuit element parts in a synthetic resin in parallel, cutting the molded synthetic resin, and cutting the molded body. Wiring paths connected to exposed electrode portions of circuit element pieces formed by cutting each substrate are formed on the end faces, and conductive wires are connected thereto.
本発明の一実施例の構成を図面第7図、第8図
について説明する。
The configuration of an embodiment of the present invention will be explained with reference to FIGS. 7 and 8.
1は合成樹脂成形体で、複数の回路素子片2を
一体に埋込み固定している。この回路素子片2は
素子形成面3が互いに平行となるように並列に埋
込み固定され、この各回路素子片2の側縁部は前
記成形体1の端面に露出されている。そしてこの
各回路素子片2の素子形成面3に接続形成した電
極部も成形体1の端面に露出されている。さらに
この回路素子片2に成形体1の端面に露出した電
極部は成形体1の端面に形成した配線路5に接続
され、各回路素子片2の配線路5に導線6がそれ
ぞれ接続されている。この導線6を接続した成形
体1は絶縁被膜7で被覆されている。 1 is a synthetic resin molded body in which a plurality of circuit element pieces 2 are integrally embedded and fixed. The circuit element pieces 2 are embedded and fixed in parallel so that the element forming surfaces 3 are parallel to each other, and the side edges of each circuit element piece 2 are exposed at the end surface of the molded body 1. The electrode portions connected to the element forming surface 3 of each circuit element piece 2 are also exposed at the end surface of the molded body 1. Further, the electrode portions of the circuit element pieces 2 exposed on the end faces of the molded body 1 are connected to wiring paths 5 formed on the end faces of the molded body 1, and conductive wires 6 are connected to the wiring paths 5 of each circuit element piece 2, respectively. There is. The molded body 1 to which the conductive wire 6 is connected is coated with an insulating coating 7.
次にこの複合回路素子の製造方法を第1図ない
し第8図について説明する。 Next, a method for manufacturing this composite circuit element will be explained with reference to FIGS. 1 to 8.
細長板状のセラミツク回路素子基板10の回路
素子形成面3に第1図に示すように長手方向に間
隔をおいて回路素子部11例えば抵抗被膜を印刷
などの適宜の手段で形成する。この回路素子部1
1の両端は、予め回路素子形成面3に長手方向の
両縁に沿つて間隔をおいて蒸着など適宜の手段で
形成した電極部12に接続されている。次いで回
路素子部11をトリミングによつて抵抗調整など
の調整を行う。次いで基板10の長手方向に沿つ
て両縁に連続的に前記回路素子部11の電極部1
2に接続した電極部13を蒸着などによつて形成
する。 As shown in FIG. 1, circuit element portions 11 such as resistive coatings are formed on the circuit element forming surface 3 of the ceramic circuit element substrate 10 in the form of an elongated plate at intervals in the longitudinal direction by appropriate means such as printing. This circuit element section 1
Both ends of the electrode 1 are connected to electrode portions 12 formed in advance on the circuit element forming surface 3 along both longitudinal edges at intervals by an appropriate means such as vapor deposition. Next, the circuit element portion 11 is trimmed to perform adjustments such as resistance adjustment. Next, the electrode portion 1 of the circuit element portion 11 is continuously applied to both edges of the substrate 10 along the longitudinal direction.
The electrode portion 13 connected to the electrode portion 2 is formed by vapor deposition or the like.
次いで第2図に示すように複数の基板10を回
路素子形成面3を平行にして並設する。この各基
板10は図示しないスペーサにて所定間隔をもつ
て並設し或いは直接に当接並設してもよく、基板
10の両面に回路素子部11を形成した場合には
間隔をあけて並設する。そしてこの並設された各
基板10の回路素子部11は複合回路素子の種類
に応じて同一または異種のものを選択して並設す
る。 Next, as shown in FIG. 2, a plurality of substrates 10 are arranged in parallel with their circuit element forming surfaces 3 parallel to each other. These substrates 10 may be arranged side by side with a predetermined interval between them using spacers (not shown) or may be placed side by side in direct contact with each other. If the circuit element portions 11 are formed on both sides of the substrate 10, they may be arranged side by side with a predetermined interval between them. Set up The circuit element portions 11 of each of the substrates 10 arranged in parallel are selected from the same or different types depending on the type of composite circuit element and arranged in parallel.
次いで第3図に示すように並設した基板10を
合成樹脂にて埋込み成形し各基板10を合成樹脂
成形体1にて一体化する。 Next, as shown in FIG. 3, the substrates 10 arranged in parallel are embedded and molded with synthetic resin, and each substrate 10 is integrated with the synthetic resin molded body 1.
次いで第4図に示すように合成樹脂成形体1を
各基板10の回路素子部11間の位置で基板10
とともに各基板10と直交方向に切断し、第5図
に示すように切断された合成樹脂成形体1の端面
に基板10の切断によつて成形された各回路素子
片2の縁部が露出され、電極部13も端面に露出
される。 Next, as shown in FIG.
At the same time, the edges of each circuit element piece 2 formed by cutting the substrate 10 are exposed on the end face of the cut synthetic resin molded body 1 as shown in FIG. 5. , the electrode portion 13 is also exposed at the end surface.
次いで第6図に示すように合成樹脂成形体1の
各回路素子片2の縁部が露出された端面に印刷ま
たはエツチング法など適宜の手段で配線路5を形
成し、この配線路5で電極部13を複合回路素子
の種類に応じて接続する。 Next, as shown in FIG. 6, a wiring path 5 is formed on the exposed end surface of each circuit element piece 2 of the synthetic resin molded body 1 by an appropriate method such as printing or etching. The sections 13 are connected according to the type of composite circuit element.
次いで第7図に示すように配線路5に導線6を
半田などで接続し、導線6を並列に同一方向に突
設させる。 Next, as shown in FIG. 7, conductive wires 6 are connected to the wiring path 5 by soldering or the like, and the conductive wires 6 are arranged in parallel and protruding in the same direction.
次いで第8図に示すように成形1の表面を合成
樹脂などの絶縁被膜7で被覆することにより複合
回路素子8が完成する。 Next, as shown in FIG. 8, the surface of the molding 1 is coated with an insulating coating 7 made of synthetic resin or the like, thereby completing a composite circuit element 8.
なお前述の合成樹脂成形体1と基板10とを切
断した状態(第5図)で基板10の縁部が露出し
た成形体1の端面をエツチングなどの手段で基板
10の側端部を第9図に示すように露出させ、電
極部13と配線路5との接続を確実にすることも
できる。 When the aforementioned synthetic resin molded body 1 and the substrate 10 are cut (FIG. 5), the end surface of the molded body 1 with the edge of the substrate 10 exposed is removed by etching or other means to remove the side edges of the substrate 10. It is also possible to ensure the connection between the electrode portion 13 and the wiring path 5 by exposing it as shown in the figure.
また第10図に示すように複数の回路素子片2
を並列に配設した一つの回路素子片群9に限られ
ず、複数の回路素子片群9を成形体1にて一体に
埋込み固定してもよい。また回路素子片2の両面
を回路素子形成面3としてより高密度に回路素子
部11を設けることができる。 Further, as shown in FIG. 10, a plurality of circuit element pieces 2
The circuit element piece group 9 is not limited to one circuit element piece group 9 arranged in parallel, but a plurality of circuit element piece groups 9 may be integrally embedded and fixed in the molded body 1. Moreover, the circuit element portions 11 can be provided with higher density by using both sides of the circuit element piece 2 as the circuit element forming surfaces 3.
さらに回路素子片2は抵抗に限らず第11図に
示すようにセラミツクコンデンサにも適用でき、
この構成では細長セラミツクコンデンサ基板10
Aの回路素子形成面3の長手方向に沿つた両縁に
連続して電極部13を形成し、前記実施例で示す
ように成形体1に基板10Aを並列に埋込み固定
して切断して複合回路素子とする。 Furthermore, the circuit element piece 2 can be applied not only to resistors but also to ceramic capacitors as shown in FIG.
In this configuration, the elongated ceramic capacitor substrate 10
Electrode portions 13 are formed continuously on both longitudinal edges of the circuit element forming surface 3 of A, and as shown in the above embodiment, the substrates 10A are embedded and fixed in parallel in the molded body 1 and cut to form a composite. As a circuit element.
また第12図に示すようにチツプ形コイルにも
適用でき、コイル基板10Bを同様に成形体1に
埋込み固定して切断して複合回路素子とする。 Further, as shown in FIG. 12, the present invention can also be applied to a chip-shaped coil, in which the coil substrate 10B is similarly embedded and fixed in the molded body 1 and cut to form a composite circuit element.
なお成形体1内に並列に埋込み固定する回路素
子片2は同一種の抵抗、コンデンサ或いはコイル
に限らず、適宜複合回路に応じた抵抗、コンデン
サ或いはコイルを組合せて並設し、さらには抵抗
値、コンデンサ容量、コイル容量なども適宜選択
できる。 Note that the circuit element pieces 2 to be embedded and fixed in parallel in the molded body 1 are not limited to the same type of resistors, capacitors, or coils, but may be arranged in parallel in combination with resistors, capacitors, or coils that suit the composite circuit as appropriate , capacitor capacity, coil capacity, etc. can be selected as appropriate.
本発明によれば複数の回路素子片を合成樹脂成
形体に埋込み固定したので、高密度に回路素子を
並設でき、各回路素子部は耐湿特性が向上され、
製造も容易にでき、安価に得られるものである。
According to the present invention, since a plurality of circuit element pieces are embedded and fixed in a synthetic resin molded body, the circuit elements can be arranged in parallel at high density, and the moisture resistance of each circuit element part is improved.
It is easy to manufacture and can be obtained at low cost.
また基板に複数の回路素子部を形成した基板を
並列に合成樹脂にて埋込み成形し、この合成樹脂
を切断して各基板の切断による回路素子片を形成
することにより異種抵抗値、異種回路素子の組合
せの複合回路素子を容易に得ることができる。 In addition, by embedding and molding a board on which multiple circuit elements are formed in parallel using synthetic resin, and cutting the synthetic resin to form circuit element pieces by cutting each board, different resistance values and different circuit elements can be created. A composite circuit element with a combination of can be easily obtained.
第1図は本発明の回路素子片を形成する基板の
正面図、第2図は同上基板の並設状態を示す斜視
図、第3図は複数の基板を合成樹脂成形体で一体
化した状態を示す斜視図、第4図は同上切断状態
を示す斜視図、第5図は同上切断片を示す斜視
図、第6図は同上配線路を形成した状態の正面
図、第7図は本発明の複合回路素子の正面図、第
8図は同上完成状態の正面図、第9図は他の実施
例を示す切断された成形体の側面図、第10図は
他の実施例を示す複合回路素子の斜視図、第11
図は回路素子部をコンデンサとした基板の正面
図、第12図は回路素子部をコイルとした基板の
正面図である。
1……合成樹脂成形体、2……回路素子片、3
……回路素子形成面、5……配線路、6……導
線、11……回路素子部、13……電極部。
Fig. 1 is a front view of a substrate forming a circuit element piece of the present invention, Fig. 2 is a perspective view showing the same substrates arranged side by side, and Fig. 3 is a state in which a plurality of substrates are integrated with a synthetic resin molded body. FIG. 4 is a perspective view showing the same as the above in a cut state, FIG. 5 is a perspective view showing the same as the cut piece, FIG. 8 is a front view of the same completed state, FIG. 9 is a side view of a cut molded body showing another embodiment, and FIG. 10 is a complex circuit showing another embodiment. Perspective view of element, 11th
The figure is a front view of a board with a capacitor as a circuit element, and FIG. 12 is a front view of a board with a coil as a circuit element. 1...Synthetic resin molded body, 2...Circuit element piece, 3
...Circuit element forming surface, 5... Wiring path, 6... Conductor, 11... Circuit element portion, 13... Electrode portion.
Claims (1)
素子部に接続された電極部を有し回路素子形成面
を互いに平行に配置した回路素子片と、この複数
の回路素子片を一体に埋込み固定し各回路素子片
の縁部の電極部を露出させた合成樹脂成形体とか
らなり、この成形体の電極部が露出した端面にこ
の電極部に接続した配線路を形成するとともに導
線を接続したことを特徴する複合回路素子。 2 基板の回路素子形成面に回路素子部を所定間
隔毎に形成するとともにこの各回路素子部に接続
された電極部を形成し、この複数の基板を回路素
子形成面が互いに平行となるように配置し、この
複数の並設された基板を合成樹脂に一体に埋込み
形成し、この複数の基板を埋込み固定した合成樹
脂成形体を各基板と直交方向に各回路素子部間で
切断し、切断した成形体の端面に、各基板の切断
により形成された複数の回路素子片の各縁部の露
出されている前記電極部を接続する配線路を形成
するとともに導線を接続することを特徴とする複
合回路素子の製造方法。[Scope of Claims] 1. A circuit element piece having a circuit element forming surface and an electrode portion connected to the circuit element portion of the circuit element forming surface and having the circuit element forming surfaces arranged parallel to each other, and the plurality of circuit elements. It consists of a synthetic resin molded body in which the pieces are embedded and fixed together and the electrode parts at the edges of each circuit element piece are exposed, and a wiring path connected to the electrode part is formed on the end surface of this molded body where the electrode part is exposed. A composite circuit element characterized by connecting conductive wires. 2 Form circuit element parts at predetermined intervals on the circuit element forming surface of the substrate, and form electrode parts connected to each of the circuit element parts, and arrange the plurality of substrates so that the circuit element forming surfaces are parallel to each other. Then, the plurality of parallel substrates are integrally embedded in synthetic resin, and the synthetic resin molded body in which the plurality of substrates are embedded and fixed is cut between each circuit element part in a direction perpendicular to each substrate. A wiring path is formed on the end surface of the molded body to connect the exposed electrode portions of the edges of the plurality of circuit element pieces formed by cutting each substrate, and a conductive wire is connected thereto. A method for manufacturing a composite circuit element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57141809A JPS5932120A (en) | 1982-08-16 | 1982-08-16 | Composite circuit element and method of producing same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57141809A JPS5932120A (en) | 1982-08-16 | 1982-08-16 | Composite circuit element and method of producing same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5932120A JPS5932120A (en) | 1984-02-21 |
| JPH0148648B2 true JPH0148648B2 (en) | 1989-10-20 |
Family
ID=15300628
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57141809A Granted JPS5932120A (en) | 1982-08-16 | 1982-08-16 | Composite circuit element and method of producing same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5932120A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6219730U (en) * | 1985-07-22 | 1987-02-05 |
-
1982
- 1982-08-16 JP JP57141809A patent/JPS5932120A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5932120A (en) | 1984-02-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4463338A (en) | Electrical network and method for producing the same | |
| JPH0620802A (en) | Bulk metal chip resistor | |
| FR2653588B1 (en) | ELECTRIC RESISTANCE IN THE FORM OF A CHIP WITH SURFACE MOUNT AND MANUFACTURING METHOD THEREOF. | |
| US5285184A (en) | Chip-type network resistor | |
| US3478424A (en) | Method of manufacturing fixed value resistors | |
| JPH01233701A (en) | Chip resistor and its manufacture | |
| US4164071A (en) | Method of forming a circuit board with integral terminals | |
| US6128199A (en) | Composite device and manufacturing method thereof | |
| JPH0148648B2 (en) | ||
| JPS59501566A (en) | Electronic element manufacturing method | |
| JP2867112B2 (en) | Chip type resistor network and manufacturing method thereof | |
| US3919767A (en) | Arrangement for making metallic connections between circuit points situated in one plane | |
| GB1583684A (en) | Electrical layer resistor and a method for its manufacture | |
| JPS6242539Y2 (en) | ||
| JPS608603B2 (en) | Manufacturing method of chip resistor | |
| JPS6390113A (en) | Resistance-capacitor composite component | |
| JPS60208801A (en) | chip resistor | |
| JP2640767B2 (en) | Method of manufacturing chip-type resistor network | |
| JPS59225503A (en) | Resistance array | |
| JPH0653016A (en) | Network resistor and its manufacture | |
| JPH051100Y2 (en) | ||
| JPS6348111Y2 (en) | ||
| JPH056811U (en) | Inductance circuit | |
| JPS6246048B2 (en) | ||
| JPH0529109A (en) | Varistor part |