JPH0148702B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a phase-locked loop circuit (hereinafter referred to as
The present invention relates to a phase synchronization detection circuit that can accurately detect the presence or absence of phase synchronization in a PLL circuit (abbreviated as a PLL circuit).

[Technical background of the invention and its problems] The basic components of a PLL circuit are a reference oscillator, a phase comparator, a loop filter, and a voltage controlled oscillator (VCO). By disposing a combining circuit 5 on the output side of 1 and adding a modulation signal there, it can be used as a phase modulation circuit. In the figure, 2 and 3 represent a loop filter and a VCO, respectively, and 4 represents a frequency divider.

By the way, a circuit for detecting phase synchronization loss in such a PLL circuit is conventionally known, for example, as shown in FIG.
As shown in FIG.
After shifting the phase by 180 degrees, the frequency is divided by 1/2 by the flip-flop 62, and the frequency of the comparison frequency signal BS is divided by 1/2 by the flip-flop 63, and the outputs of these frequency divisions are sent to the exclusive OR circuit (EX-OR circuit) 64. The signal is introduced into the determination circuit 65 through the DC signal, where it is converted into a DC signal and compared with a determination level to detect out-of-synchronization.

Because of this configuration, for example, if the comparison frequency signal BS is delayed by 180 degrees with respect to the reference frequency signal AS as shown in FIG.
Since the phase difference of DS (the inverted signal of the signal DS generated because the flip-flop 63 and the flip-flop 62 are not set to the same initial state) is zero, the EX-OR circuit 64 outputs "L" or "H". Continuous signal ES or (corresponds to)
is output. As a result, the DC conversion level (GND) or power supply voltage level (VDD) is included in the synchronous region ○a or ○b as shown in FIG. signal is output. On the other hand, if the synchronization is out of synchronization, the phase of the comparison frequency signal BS changes randomly with respect to the reference frequency signal AS, so the DC level of the output of the EX-OR circuit 64 becomes approximately V _DD /2. This is included in the out-of-synchronization region indicated by ○ in FIG. 3, and the determination circuit 65 issues a signal indicating that the out-of-synchronization state exists. Also,
If the input/output characteristics of the VCO 3 change depending on the temperature or there are manufacturing variations, the phase of the comparison frequency signal BS will be slightly shifted as shown by the broken line in FIG. 2, for example. When the phases are shifted in this way, the outputs CS and DS() of each flip-flop 62, 63
is shifted as shown by the broken line, and a pulse signal ES() corresponding to this shift is output from the EX-OR circuit 64. However, if the above-mentioned phase shift amount is within a small range, the _DC conversion level is included within the synchronization regions ○a and ○ _b as shown in FIG.

However, as the amount of temperature change in the input/output characteristics of the VCO 3 increases, the phase of the comparison frequency signal shifts significantly, and a large degree of modulation is required.
When the phase of BS changes significantly, the output signals CS and DS of each flip-flop 62 and 63 change as shown in the figure.
The phase difference increases, and the duty ratio of the output signal ES (broken line) of the EX-OR circuit 64 approaches 50%. Therefore, the DC level of the output signal ES obtained by the determination circuit ₆₅ enters the out-of-synchronization region ○c as shown in _FIG . become.

On the other hand, in order to prevent this misjudgment, it is also conceivable to bring the judgment level (V ₁ , V ₂ in FIG. 3) as close as possible to V _DD /2 to sandwich the out-of-synchronization region ○c. However, in this method, each judgment level V ₁ , V ₂
Since it is necessary to increase the accuracy of setting or the accuracy of converting to DC, the determination circuit 65 becomes complicated and expensive.

Furthermore, in the conventional circuit, since the initial state of each flip-flop 62, 63 is undefined, the third
As shown in the figure, two synchronization areas ○A and ○B must be set in accordance with the two outputs of the EX-OR circuit 64, which makes the determination circuit 65 complicated.

[Object of the Invention] The present invention enables accurate determination of out-of-sync without interfering with the out-of-sync determination area in the determination circuit, and simplifies the determination circuit by unifying the form of the signal used for determination. The purpose of this invention is to provide a phase-out-of-sync detection circuit that is highly efficient.

[Summary of the Invention] In order to achieve the above object, the present invention provides a signal obtained by shifting a reference frequency signal by 180° and a comparison frequency signal to the first and second stages of a cascade configuration of n (n=2, 3,...) stages, respectively. After the frequency is divided by the second flip-flop circuit, it is subjected to exclusive logic processing, thereby making the difference in the DC conversion level of the exclusive OR output significant between when synchronization is lost and when the phase changes significantly due to modulation, etc., and the above-mentioned Each flip-flop circuit is reset or preset by a pulse signal generated in synchronization with a reference frequency signal at a period of 2n ^-1 times or more, thereby defining the initial state of each flip-flop circuit. .

[Embodiment of the Invention] FIG. 5 is a block diagram of a phase synchronization detection circuit according to an embodiment of the present invention, and the same parts as in FIG.

The difference in the configuration of this circuit from the circuit shown in FIG. 1 is that a reference frequency signal whose phase has been shifted by 180 degrees by a phase shifter 61 is transferred to a first flip-flop circuit 71 in which flip-flops 71a and 71b are connected in two stages in series. Frequency division and exclusive OR circuit (EX-OR circuit) 6
At the same time, the comparison frequency signal BS is frequency-divided by a second flip-flop circuit 72 having the same configuration as the first flip-flop circuit 71 and outputted to EX.
−Supplied to the OR circuit 64 and the reference frequency signal AS
The frequency is divided by 1/4 by a frequency divider 73 to obtain a reset signal RS, which is used to reset each of the flip-flops 71a, 71b and 72a, 72b.

With such a configuration, the phase-shifted reference frequency signal AS and comparison frequency signal BS are first divided into 1/2 frequency by flip-flops 71a and 72a, and then divided by flip-flops 71b and 72a.
The frequency is divided by 1/2 by b, and each pulse signal is subjected to exclusive OR processing as a pulse signal with a duty ratio of 50%, which is divided by a total of 1/4. Also, during the frequency division, each flip-flop 71a, 72b
is reset every four times the period of the reference frequency signal AS in synchronization with the reference frequency signal AS by the reset signal RS from the frequency divider 73, and its state is initialized. Therefore, each of the flip-flop circuits 7
The logic states of the signals output from the EX-OR circuits 1 and 72, and the logic form of the output signal of the EX-OR circuit 64, are only one type.

Therefore, if the phase of the current comparison frequency signal BS deviates or changes significantly as shown in FIG. 6 due to temperature change or modulation with a large degree of modulation, each flip-flop circuit 71, 72 will output the period as the standard as shown in the figure. A signal GS with four times the frequency of the signal AS and the same logic (all initial states are the same),
HS is obtained, and as a result, the EX-OR circuit 64 obtains an output IS whose duty ratio is reduced compared to the conventional one (ES in FIG. 4). Therefore, the DC level of the output IS becomes close to the ground level (GND), and it can be included in the conventional (FIG. 3) synchronous region ◯◯ as shown in FIG. 7 V _R '. In other words, this corresponds to the fact that false detection can be prevented without having to bring the determination level V ₂ closer to the V _DD /2 side and interpose the out-of-synchronization region ○c. Furthermore, since the output IS of the EX-OR circuit 64 is limited to only one type, the judgment circuit 65 only needs to make judgments in the range from V _DD /2 to the ground level GND as shown in FIG. .

On the other hand, if the flip-flop circuits 71 and 7 are synchronized as shown in FIG.
Pulse signals with equal phase and equal logic from 2
GS and HS will be output. For this reason,
The output IS of the EX-OR circuit 64 has a continuous "L" level, and its direct current level becomes the ground level, so that it is determined that the synchronization state is established. Here, if each of the flip-flop circuits 71,
If 72 is not reset, the logic of the outputs GS and HS of each flip-flop 71 and 72 may be reversed, and if this is reversed, the output IS of the EX-OR circuit 64 will be as shown in FIG. This results in a signal with a duty ratio of 50%, resulting in an erroneous determination that the signal is out of synchronization.

As described above, in the circuit of this embodiment, each of the flip-flop circuits 71 and 72 has a two-stage configuration, and is reset and initialized every four cycles of the reference frequency signal.
It is possible to make the difference in the DC level of the output IS of the circuit 64 noticeable when it is out of synchronization and when it is modulated with a large modulation degree, and moreover, the logic form of the output IS of the EX-OR circuit 64 is unique It can be of any kind. As a result, accurate synchronization determination can be performed without limiting the out-of-synchronization area. In addition, since the logical form of the signal is limited to only one type, the judgment operation in the judgment circuit 65 is reduced to half of the conventional one, and as a result, the structure of the judgment circuit 65 is It can be made much easier. In other words, according to this embodiment, it is possible to provide an out-of-sync detection circuit that has high determination performance and can be simplified in configuration.

In this embodiment, the reset signal RS is a pulse signal having a period four times that of the reference frequency signal AS, but it is a pulse signal having a period four times that of the reference frequency signal AS. This signal IS has the same waveform even in the period of . In reality, considering the circuit configuration and the out-of-phase detection time, if the number of cascaded flip-flop circuits 71 and 72 is n, then
An appropriate value with a period greater than or equal to 2 ^n-1 is selected.
Furthermore, the present invention is not limited to the above-mentioned embodiments, and for example, the number of stages of flip-flops constituting the flip-flop circuit, the number of divisions of the frequency divider circuit, and
The configuration of the PLL circuit can also be modified in various ways without departing from the gist of the present invention.

[Effects of the Invention] As explained above, the present invention provides phase-shifted reference frequency signals and comparison frequency signals to n (n=2, 3,
…) Frequency is divided by each flip-flop circuit in a cascade configuration, and each of these flip-flop circuits is synchronized with a reference frequency signal to divide its period.
It is designed to be initialized every 2n ^-1 times or more cycles.

Therefore, according to the present invention, it is possible to accurately determine out of synchronization without interfering with the out of synchronization determination area in the determination circuit, and moreover, it is possible to unify the signal form used for determination, and to improve the efficiency of the determination circuit. It is possible to provide an out-of-phase detection circuit whose configuration can be simplified.

[Brief explanation of drawings]

1 to 4 are for explaining a conventional phase synchronization detection circuit. FIG. 1 is a block configuration diagram thereof, FIGS. 2 and 4 are timing diagrams used to explain the operation, and FIG. FIG. 3 is a schematic diagram for explaining the determination state, FIGS. 5 to 9 are for explaining a phase out-of-sync detection circuit according to an embodiment of the present invention, and FIG. 5 is a block diagram thereof; 6, 8, and 9 are timing diagrams used to explain the operation of the circuit, and FIG. 7 is a schematic diagram used to explain the determination state. 61... Phase shifter, 64... Exclusive OR (EX
-OR) circuit, 65...determination circuit, 71...first
Flip-flop circuit, 72... Second flip-flop circuit, 73... Frequency divider, AS... Reference frequency signal, BS... Comparison frequency signal, RS... Reset signal, CS, DS, GS, HS... Flip-flop Circuit output, ES, IS...EX-OR circuit output.

Claims (1)

[Claims] 1 A phase for detecting out of phase synchronization of the phase-locked loop circuit, which compares the output frequency signal of the voltage controlled oscillator with the reference frequency signal of the reference oscillator using a phase comparator, and supplies the output to the voltage controlled oscillator through a loop filter. The out-of-synchronization detection circuit includes a phase shifter that shifts the phase of the reference frequency signal by 180 degrees, and n (n=2, 3,...) stage cascade configuration that divides the phase-shifted reference frequency signal from this phase shifter. a first flip-flop circuit; a second flip-flop circuit having the same configuration as the first flip-flop circuit that divides the output frequency signal of the voltage controlled oscillator; A frequency divider circuit that generates a pulse signal with a period of ⁿ -1 times or more and sets the initial state of the first and second flip-flop circuits, and an exclusive OR of the output signals of the first and second flip-flop circuits. A phase out-of-sync detection circuit comprising: a processing circuit; and a determination circuit that converts the output signal of this circuit into a DC signal, compares the DC signal with a predetermined determination level, and issues a determination output. .