JPH0150004B2 - - Google Patents

Description

[Detailed description of the invention]

Industrial Application Field The present invention relates to a magnetic recording device, mainly a disk device,
The present invention relates to a peak shift compensation circuit that is used in a head reproduction output readout circuit of a flexible disk device and compensates for deviations in the peak position of reproduction output. Configuration of conventional example and its problems FIG. 1 shows an example of a conventional peak shift compensation circuit. 1 is an input end, 2 is a matching resistor, 3 is a delay line, 4 is a level adjuster, 5 is a differential amplifier, and 6 is an output end. A signal delayed by Td of the input signal is input to the (+) side input terminal of the differential amplifier 5, and the input signal and the open terminal B are input to the differential amplifier (-) side input terminal.
The combined signal with the signal that is totally reflected at the matching terminal A and returns to the matching terminal A with a delay of 2xTd is input after adjusting the level. Overall, the difference between the Td delayed signal and the 2xTd delayed signal is taken, the solitary wave time width is narrowed, the influence on adjacent bits is reduced, and it functions as a peak shift compensation circuit. However, in the above conventional example, 250K to 500K bits/bits, such as flexible disk devices,
When the transfer frequency is relatively slow, on the order of seconds, the delay line delay time increases to 1 to 4 microseconds, resulting in an increase in the shape of the delay line, which has the drawbacks of increasing the area occupied on the circuit board and increasing costs. are doing. A second conventional example is shown in FIG. 7 is the input end,
8, 10, 12 are capacitors, 9 is an inductance, 14 is a changeover switch, 15 is an output end,
It constitutes a low frequency circuit (hereinafter referred to as LPF). On the inner circumferential side of the disk, where the peak shift is relatively large, the LPF characteristics are set using the changeover switch 14 to increase the cutoff frequency, widening the signal passing frequency band, and suppressing the peak shift occurring in the circuit as much as possible. On the other hand, in the case of the outer circumferential side of the disk where the peak shift is relatively small, the changeover switch 14 lowers the cutoff frequency and functions as a circuit that gives priority to improving the signal-to-noise ratio over the peak shift. Also called switch filter. However, although this circuit can switch the cutoff frequency, the group delay characteristics cannot be made constant, resulting in waveform distortion, and in particular, the flat part of the output after differentiation of the peak detection circuit, so-called droop, increases. This has the disadvantage that the peak detection margin decreases. OBJECTS OF THE INVENTION The present invention provides a peak shift compensation circuit that eliminates the above-mentioned conventional drawbacks, has less waveform distortion, and has a simple circuit configuration. Structure of the Invention In order to achieve the above object, the present invention
It is characterized by being able to switch between an LC type delay equivalent circuit and a primary LC type low frequency circuit, and cascading the primary LC type low frequency circuit by sandwiching an impedance conversion circuit in this circuit section. It is. DESCRIPTION OF EMBODIMENTS First, the basic configuration and effects of the present invention will be explained. The high-resolution waveform of the magnetic recording and reproducing output is
As shown in the figure, it is considered to be a composite wave 18 of a fundamental wave 16 and an odd harmonic, especially a third harmonic 17.
As the resolution deteriorates, the peak shift increases due to pattern combinations. This is because the temporal spread of the solitary wave output causes a position shift of adjacent peaks, and the third
In the figure, this corresponds to the third harmonic component 17 becoming smaller. Therefore, conversely, by emphasizing the third harmonic, the solitary wave becomes narrower and the occurrence of peak shift decreases. However, what is important here is that the third harmonic emphasizing circuit is required to have equal delay time characteristics for the fundamental wave and for the third harmonic. If the group delay is not constant, the temporal balance of the solitary wave will be lost, leading to an increase in droop as pointed out in the second conventional example. The present invention provides a circuit for compensating for peak shifts by satisfying third harmonic increase and constant group delay;
A fourth embodiment of the present invention will be described below.
This will be explained with figures. In Figure 4, head 1
The reproduced output from 9 is amplified by a differential amplifier 20 and input to a peak shift compensation circuit. External signal PC−
1. When PC-2 is set to zero level, the circuit before transistors 29 and 30 becomes the primary circuit shown in Figure 5.
If it becomes an LCR type LPF circuit and PC-1 + PC-2 are made high impedance, the primary LC shown in Figure 6
It becomes a type delay equalization circuit. In the former case, the circuit shown in Figure 4 has an LPF connected in series with the emitter follower in between, and the peak shift compensation is off.
Used in the disk outer circumference example. In the latter case, the delay equalization circuit and the LPF are connected in series, the peak shift compensation is turned on, and it is used on the inner circumferential side of the disk. When the peak shift compensation is off, in Fig. 4, the emitter follower consisting of transistors 29 and 30 is sandwiched between the front and rear stages, which are the same primary LPF circuit, and the damping constant K ₁ of the front stage, the natural frequency ₀₁ ,
Letting each of the latter stages be K ₂ and ₀₂ ,

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Express it with [Formula]. The frequency characteristics of this type of LPF are shown in Figure 7. When the damping constant is between 0.7 and 0.8, the frequency band with constant group delay becomes the widest. Also, to emphasize the gain near the natural frequency, set the damping constant to 0.6.
This is possible if you do the following. When peak shift compensation is on, the previous stage becomes the delay equalization circuit shown in Figure 6, but as shown in the frequency characteristics in Figure 8, the phase and delay time are exactly the same as in the LPF shown in Figure 7. . The gain becomes 1 when K=1.0, making it a perfect phase equalization circuit. From the above, with the configuration shown in Figure 4, the group delay characteristics are kept constant regardless of whether compensation is on or off, and when compensation is on, the high-frequency gain is emphasized (or the cutoff frequency is raised), and when compensation is off,
It is possible to lower the cutoff frequency. The above characteristics are shown in FIG. First stage natural frequency ₀₁
and the natural frequency ₀₂ of the rear stage is ₀₁ = 0.8, the damping of the front stage is a constant K ₁ = 1.0 and the damping constant of the rear stage K ₂
When peaking is performed with =0.45, as shown in FIG. 9, when the peak shift compensation is off, the gain of the front stage is 37, the gain of the rear stage is 38, and the total gain is 39. Further, the delay time consists of the first stage 40, the second stage 41, and the total 42, and is sufficiently constant up to the vicinity of the cutoff frequency. When the peak shift compensation is on, the total gain is 38, and the total delay time is 42, which is the same as when the compensation is off, so that a wide characteristic with a constant group delay range can be obtained. Effects of the Invention The present invention has the above configuration, and according to the present invention, the following effects can be obtained. a Since the group delay characteristic is constant by switching compensation on and off, it is possible to realize a peak shift compensation circuit with less waveform distortion. b Since it is a combination of two stages of primary LCR filters, it has the advantage that the circuit can be easily constructed.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of a conventional peak shift compensation circuit, Fig. 2 is a circuit diagram of another conventional peak shift compensation circuit, Fig. 3 is a waveform diagram of frequency components and composite waves of the reproduced output, and Fig. 4 is a diagram of a waveform of a synthesized wave. A circuit diagram of a peak shift compensation circuit according to an embodiment of the present invention. FIG. 5 is an equivalent circuit diagram when the compensation of the pre-stage filter section of the same embodiment is off, and FIG. 6 is an equivalent circuit diagram when the compensation of the pre-stage filter section of the embodiment is on. 7 shows the frequency characteristics of the first-order LCR type LPF, FIG. 8 shows the frequency characteristics of the first-order LC type delay equalization circuit, and FIG. 9 shows the frequency characteristics of an embodiment of the present invention. 19...Head, 20...Differential amplifier, 21,
22... Transistor, 23, 24... Inductance, 25, 26... Capacitor, 27, 28
...Resistor, 29,30...Transistor, 31,
32...Inductance, 33...Capacitor,
34, 35...Resistor, 36...Differential amplifier.

Claims (1)

[Claims] 1. A first-order LC type delay equalization circuit and 1.
A peak shift compensation circuit consisting of a first-order LC-type low-frequency circuit connected in cascade with an impedance conversion circuit sandwiched between a circuit section whose circuit configuration can be switched to either the second-order LC-type low-frequency circuit or the second-order LC-type low-frequency circuit. 2. When the circuit section constitutes a first-order LC type low-frequency circuit, its natural frequency is ₀₁ , and the damping constant is
Let K be ₁ , the natural frequency of the first-order LC type low-frequency circuit in the subsequent stage _{be 02} , and the damping constant be K ₂ , then ₀₁ /
₀₂ = 0.7 to 0.9 and (K ₁ +K ₂ )/ ₂ = 0.6 to 0.9, the peak shift compensation circuit according to claim 1.