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JPH0150100B2 - - Google Patents
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JPH0150100B2 - - Google Patents

Info

Publication number
JPH0150100B2
JPH0150100B2 JP58004610A JP461083A JPH0150100B2 JP H0150100 B2 JPH0150100 B2 JP H0150100B2 JP 58004610 A JP58004610 A JP 58004610A JP 461083 A JP461083 A JP 461083A JP H0150100 B2 JPH0150100 B2 JP H0150100B2
Authority
JP
Japan
Prior art keywords
solder
hybrid integrated
integrated circuit
background material
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP58004610A
Other languages
Japanese (ja)
Other versions
JPS59129453A (en
Inventor
Hiroshi Watabe
Susumu Toba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP58004610A priority Critical patent/JPS59129453A/en
Publication of JPS59129453A publication Critical patent/JPS59129453A/en
Publication of JPH0150100B2 publication Critical patent/JPH0150100B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00Marks applied to devices, e.g. for alignment or identification
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0266Marks, test patterns or identification means
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/09Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092Dispersed materials, e.g. conductive pastes or inks
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452Solder masks
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00Marks applied to devices, e.g. for alignment or identification
    • H10W46/601Marks applied to devices, e.g. for alignment or identification for use after dicing
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)

Description

【発明の詳細な説明】 混成集積回路へ搭載する半導体チツプの接続形
態としては、共晶合金、はんだ、導電性接着剤等
によるダイボンデイグと、Al、Au線を熱圧着に
より接合するワイヤボンデイングあるいは第1図
に示すようにチツプ1の電極を盛り上げてバンプ
電極2とし、この電極2を直接基板3の導体パタ
ーン4に重ね合わせるようにして接続するいわゆ
るフエースダウンボンデイング等が知られている
が、本発明は最近自動車用電子回路等に広く使用
されているフエースダウンボンデイング形の素子
(以下フリツプチツプと言う)を用いた混成集積
回路に関する。
[Detailed Description of the Invention] The connection methods for semiconductor chips mounted on hybrid integrated circuits include die bonding using eutectic alloys, solders, conductive adhesives, etc., wire bonding in which Al and Au wires are bonded by thermocompression bonding, and die bonding using thermocompression bonding. As shown in Figure 1, so-called face-down bonding is known, in which the electrodes of the chip 1 are raised to form bump electrodes 2, and the electrodes 2 are connected directly to the conductor pattern 4 of the substrate 3 by overlapping them. The present invention relates to a hybrid integrated circuit using face-down bonding type elements (hereinafter referred to as flip chips) which have recently been widely used in automotive electronic circuits and the like.

従来フリツプチツプの基板上への搭載にあつて
は、接続部分がチツプの裏面にあることにより搭
載時の位置合わせには、第2図に示すようにチツ
プ1と基板3の中間部にハーフミラー5を置き、
ハーフミラー5で反射するチツプ下面の像とハー
フミラー5を透過する回路板面との像の重なりに
より観察する方法が広く用いられていた。
Conventionally, when mounting a flip chip on a board, since the connection part is on the back side of the chip, a half mirror 5 is placed between the chip 1 and the board 3 for alignment during mounting, as shown in FIG. put
A method has been widely used in which the image of the lower surface of the chip reflected by the half mirror 5 and the image of the circuit board surface transmitted through the half mirror 5 are overlapped to make an observation.

しかしこの方法では自動化が難しく、組立工数
の増加を招くとともに、その間隔が極めて小さい
素子の電極と基板の導体パターンとの間に位置ず
れが生ずるという問題があつた。
However, this method has problems in that it is difficult to automate, increases the number of assembly steps, and causes misalignment between the electrodes of the element and the conductor pattern on the substrate, which have extremely small intervals.

本発明は最近のパターン認識の技術の向上によ
り、自動位置位置合わせが可能となつている状況
に鑑みなされたもので、混成集積回路の予備はん
だ形成時に配線に用いられない捨はんだを素子搭
載領域外の導体パターン上に同一マスクにより形
成し、背景材とともに位置合わせマークを構成す
ることにより、組立工数の増加を招くことなく精
度の高い位置合わせ搭載を自動化により実現しよ
うとするものである。
The present invention was developed in view of the situation where automatic positioning has become possible due to recent improvements in pattern recognition technology.When forming preliminary solder for hybrid integrated circuits, waste solder that is not used for wiring is transferred to the element mounting area. By forming alignment marks on the outer conductor pattern using the same mask and forming alignment marks together with the background material, it is possible to achieve highly accurate alignment and mounting through automation without increasing assembly man-hours.

以下に本発明の実施例を第3図の一部平面図及
び第4図一部縦断面図に基づいて説明する。セラ
ミツク基板6上には導体パターン7が印刷、焼成
されており、このパターン7はフリツプチツプと
接続されるリード群を構成している。導体パター
ン7のフリツプチツプ搭載領域(第3図において
一点鎖線で示す)内のチツプのバンプ(電極)と
対応する位置にはメタルマスクを用いた印刷方法
により、予備はんだとしてのバンプ受け用はんだ
8が形成されている。このような構成においてこ
の実施例では、位置合わせマークを抵抗ペースト
の焼成体にて囲繞された捨はんだ9としている。
Embodiments of the present invention will be described below based on a partial plan view in FIG. 3 and a partial longitudinal sectional view in FIG. 4. A conductor pattern 7 is printed and fired on the ceramic substrate 6, and this pattern 7 constitutes a group of leads to be connected to the flip chip. A bump-receiving solder 8 as a preliminary solder is applied at a position corresponding to the bump (electrode) of the chip in the flip-chip mounting area of the conductor pattern 7 (indicated by a dashed-dotted line in FIG. 3) by a printing method using a metal mask. It is formed. In this embodiment, with such a configuration, the alignment mark is a waste solder 9 surrounded by a fired body of resistance paste.

この捨はんだ9は、バンプ受け用はんだ8をメ
タルマスクを用いて印刷方法により形成する際、
フリツプチツプの搭載領域外の導体パターン上
に、メタルマスクに開口部を設けることにより形
成される。一方、抵抗ペーストの焼成体10は、
捨はんだ9が形成される以前の抵抗印刷焼成時
に、中央に捨はんだ9が形成される部分を残して
捨はんだ9を囲繞する位置に形成される。
This waste solder 9 is used when forming bump receiving solder 8 by a printing method using a metal mask.
It is formed by providing an opening in a metal mask on the conductor pattern outside the flip chip mounting area. On the other hand, the fired body 10 of the resistance paste is
At the time of resistance printing firing before the waste solder 9 is formed, it is formed at a position surrounding the waste solder 9, leaving a part where the waste solder 9 is formed in the center.

一般にはんだは銀系色であり、焼成された抵抗
は黒色であるため、抵抗ペーストの焼成体10が
捨はんだ9の背景をなすこの位置合わせマーク
は、自動位置合わせを行なう際の位置検出用信号
の発生源として充当な安定性を得ることができ
る。
Generally, solder is silver-based in color, and fired resistors are black in color. Therefore, this positioning mark, in which the fired resistor paste 10 forms the background of the discarded solder 9, is used as a position detection signal for automatic positioning. Adequate stability can be obtained as a source of

なお混成集積回路構成時、抵抗値の修正の際行
なわれるサンドブラスト法を抵抗ペーストの焼成
体10にも適用し、表面の膜を削りとることによ
りつや消しを行なうことは、マークの二値化信号
をより極だたせる意味で好ましい。
In addition, when configuring a hybrid integrated circuit, applying the sandblasting method used when correcting the resistance value to the fired resistor paste 10 and polishing it by scraping off the surface film will improve the binary signal of the mark. It is preferable in the sense that it makes it more extreme.

またこの実施例では、位置合わせマークとして
の抵抗及びはんだは、いずれも混成集積回路を構
成する際に行なわれる抵抗印刷・焼成工程及び予
備はんだの塗布工程において、それぞれ同時に形
成することができるため組立工数が増える心配は
ない。
In addition, in this embodiment, the resistors and solder as alignment marks can be formed simultaneously in the resistor printing/baking process and the pre-solder application process, which are performed when constructing a hybrid integrated circuit. There is no need to worry about the increase in man-hours.

更にまた、本発明に係る半導体チツプを基板上
の定位置に位置せしめる自動搭載位置合わせと
は、あらかじめ2個以上の位置合わせマークを基
板上の設定された位置に配置して、このマークを
固定位置にある撮像手段(例えばITVカメラ等)
によつて光学的に検出し、この検出したマークと
あらかじめ設定した位置との差から計算によつて
半導体チツプを吸着するヘツドの移動量を求める
ものである。
Furthermore, the automatic mounting positioning for positioning the semiconductor chip at a fixed position on the board according to the present invention means placing two or more positioning marks in advance at set positions on the board and fixing the marks. Imaging means at the location (e.g. ITV camera, etc.)
The amount of movement of the head that picks up the semiconductor chip is determined by calculation from the difference between the detected mark and a preset position.

したがつて基板上に設定される位置合わせマー
クは、半導体チツプの搭載領域との位置関係を予
め設計の段階でメモリ等に記憶させておく必要が
あり、特にその電極間隔が数100μmと微細なフ
リツプチツプの搭載においては、この位置関係の
精度が重要である。例えば搭載領域内の基準位置
と位置合わせマークとの位置関係を設定した上
で、これらを別個に形成したのでは精度の高い位
置合わせは成し得ない。この点本発明によれば基
準位置をバンプ受け用はんだとし、位置合わせマ
ークを捨はんだとして、これらを同一のメタルマ
スクを用いて同時に形成しているため、極めて高
い精度の位置合わせ搭載を行うことができる。
Therefore, the positional relationship between the alignment marks set on the substrate and the mounting area of the semiconductor chip must be memorized in memory at the design stage, especially when the electrode spacing is as small as several 100 μm. When mounting flip chips, the accuracy of this positional relationship is important. For example, if the positional relationship between the reference position and the alignment mark in the mounting area is set and then these are formed separately, highly accurate alignment cannot be achieved. In this regard, according to the present invention, the reference position is made of bump-receiving solder, the alignment mark is made of waste solder, and these are simultaneously formed using the same metal mask, so alignment and mounting can be performed with extremely high accuracy. Can be done.

なお上記実施例では、捨はんだを囲繞する背景
剤を抵抗ペーストの焼成物としたが、本発明はこ
れに限定されるものではなく、例えば背景材を前
記抵抗ペーストの焼成後に保護コート膜として形
成されるガラスペーストの焼成物としてもよい。
この場合でもガラスペーストの焼成物は、捨はん
だ形成前のガラス印刷・焼成工程と同時に行うこ
とが肝要である。
In the above embodiment, the background material surrounding the discarded solder is a fired resistor paste, but the present invention is not limited to this. For example, the background material may be formed as a protective coating film after firing the resistor paste. It may also be a fired product of glass paste.
Even in this case, it is important that the glass paste is fired at the same time as the glass printing and firing process before forming the solder.

また製造工程の短縮化が特に要求されない場合
には、捨はんだを囲繞する背景材は特に前記実施
例で述べたような混成集積回路を形成するための
一構成部材とする必要はなく、確実な二値化信号
の得られるものであれば、はんだとコントラスト
の強い塗料や接着剤であつてもよい。
Furthermore, if shortening of the manufacturing process is not particularly required, the background material surrounding the discarded solder does not need to be a component for forming a hybrid integrated circuit as described in the above embodiment, and it is not necessary to Any paint or adhesive that has a strong contrast with the solder may be used as long as a binary signal can be obtained.

このような本発明は特にフリツプチツプを位置
決め搭載する際に効果が大きいが、チツプ接続の
ためあらかじめ予備はんだを形成するものであれ
ば適応可能であることは言うまでもない。
The present invention is particularly effective when positioning and mounting flip chips, but it goes without saying that it is also applicable to any method in which preliminary solder is formed in advance for chip connection.

以上の説明から明らかなように本発明によれ
ば、混成集積回路の予備はんだ形成時に捨はんだ
を素子搭載領域外の導体パターン上に同一マスク
により形成し、背景材とともに位置合わせマーク
を構成したため、組立工数の増加を招くことなく
精度の高い位置合わせ搭載を自動化により実現す
ることができる。
As is clear from the above description, according to the present invention, during preliminary soldering of a hybrid integrated circuit, discarded solder is formed on the conductor pattern outside the element mounting area using the same mask, and the positioning mark is formed together with the background material. Highly accurate positioning and mounting can be achieved through automation without increasing assembly man-hours.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はフエイスダウン構造を示す側面図、第
2図はフエイスダウンボンダにおける従来の位置
合わせ機構を示す概略図、第3図、第4図は本発
明の一実施例を示す一部平面図及び一部縦断面図
である。 6:セラミツク基板、7:導体パターン、8:
バンプ受け用はんだ、9:捨はんだ、10:抵抗
ペーストの焼結体。
FIG. 1 is a side view showing a face-down structure, FIG. 2 is a schematic diagram showing a conventional positioning mechanism in a face-down bonder, and FIGS. 3 and 4 are partial plan views showing an embodiment of the present invention. and a partial longitudinal sectional view. 6: Ceramic substrate, 7: Conductor pattern, 8:
Solder for bump receiving, 9: Waste solder, 10: Sintered body of resistance paste.

Claims (1)

【特許請求の範囲】 1 基板上に設定された位置合わせマークを光学
的に検出して半導体チツプを基板上に搭載してな
るものにおいて、前記位置合わせマークは、予備
はんだと同一マスクにより形成され、周囲に背景
材を有する捨はんだよりなることを特徴とする混
成集積回路。 2 特許請求の範囲第1項記載のものにおいて、
背景材は抵抗ペーストの焼成体であることを特徴
とする混成集積回路。 3 特許請求の範囲第1項記載のものにおいて、
背景材はガラスペーストの焼成体であることを特
徴とする混成集積回路。
[Claims] 1. In a device in which a semiconductor chip is mounted on a substrate by optically detecting an alignment mark set on a substrate, the alignment mark is formed by the same mask as the preliminary solder. , a hybrid integrated circuit characterized in that it is made of discarded solder with a background material surrounding it. 2. In what is stated in claim 1,
A hybrid integrated circuit characterized in that the background material is a fired body of resistance paste. 3 In what is stated in claim 1,
A hybrid integrated circuit characterized in that the background material is a fired body of glass paste.
JP58004610A 1983-01-14 1983-01-14 Hybrid integrated circuit Granted JPS59129453A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58004610A JPS59129453A (en) 1983-01-14 1983-01-14 Hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58004610A JPS59129453A (en) 1983-01-14 1983-01-14 Hybrid integrated circuit

Publications (2)

Publication Number Publication Date
JPS59129453A JPS59129453A (en) 1984-07-25
JPH0150100B2 true JPH0150100B2 (en) 1989-10-27

Family

ID=11588815

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58004610A Granted JPS59129453A (en) 1983-01-14 1983-01-14 Hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPS59129453A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020071460A1 (en) 2018-10-02 2020-04-09 日本製鉄株式会社 Wound core

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0982760A (en) * 1995-07-07 1997-03-28 Toshiba Corp Semiconductor device, semiconductor element, and solder connection inspection method thereof
JP3416091B2 (en) * 2000-01-21 2003-06-16 株式会社新川 Bonding apparatus and bonding method
KR100461949B1 (en) * 2002-05-15 2004-12-14 앰코 테크놀로지 코리아 주식회사 solder ball for a semiconductor package and its manufacturing method, and evaporation method of solder ball

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020071460A1 (en) 2018-10-02 2020-04-09 日本製鉄株式会社 Wound core

Also Published As

Publication number Publication date
JPS59129453A (en) 1984-07-25

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