JPH0150111B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor inverter circuit device in which an inverter circuit is constructed using a semiconductor substrate, and particularly has a simple configuration and operates at high speed with low power consumption. This paper aims to propose an inverter circuit that can provide multiple inverter functions.

The semiconductor inverter circuit device according to the present invention will become clear from the embodiments described in detail below with reference to the drawings.

FIGS. 1 and 2 show an embodiment of a semiconductor inverter circuit device according to the present invention, which has the configuration described below.

That is, for example, in the N-type semiconductor substrate 1, P-type first and second semiconductor regions Q1 and Q2 are obtained from the main surface 2 side, and an N-type third semiconductor region Q3 is obtained between them. A P-type fourth semiconductor region Q4 is formed.

On the other hand, in the first semiconductor region Q1, from the main surface 2 side, a plurality of N to N ⁺ type fifth semiconductor regions Q51,
Q52... is formed.

Further, in the fourth semiconductor region Q4, from the main surface 2 side, N-type sixth and seventh semiconductor regions Q6 and Q
7 is formed so that a P-type eighth semiconductor region Q8 is obtained between them, and a P-type ninth semiconductor region Q9 is formed between it and the sixth semiconductor region Q6.
The semiconductor region Q10 is formed in such a manner that a tenth semiconductor region Q10 of the same type is obtained.

Furthermore, the third and eighth semiconductor regions Q3 and Q
8, first and second conductive layers C1 and C2 are arranged, which are connected to each other via first and second insulating layers 11 and 12, respectively.

Further, a third conductive layer C8 is arranged on the tenth semiconductor region Q10 with the third insulating layer 13 interposed therebetween.

Further, on the main surface 2 of the semiconductor substrate 1, first and second
An insulating layer 3 is formed in such a manner that it buries and buries the third conductive layers C1, C2 and C8, and the semiconductor substrate 1, the second semiconductor region Q2 and the third conductive layer C8 are buried, respectively. It is connected via windows 4, O2 and 5 pre-drilled in the insulating layer 3 to a fourth electrically conductive layer C3 extending above the insulating layer 3.

In addition, the first and seventh semiconductor regions Q1 and Q7
However, the windows O1 and O7 that are pre-drilled in the insulating layer 3
are interconnected by a fifth conductive layer C4 extending over the insulating layer 3 via the first
A semiconductor region Q1 is connected to a seventh semiconductor region Q7 via a fifth conductive layer C4.

Furthermore, fourth and sixth semiconductor regions Q4 and Q
6 is the window O4 and O which are pre-drilled in the insulating layer 3.
6 to a sixth conductive layer C5 extending over the insulating layer 3.

In addition, the first and second conductive layers C1 and C2
are connected to the seventh electrically conductive layer C6 extending above the insulating layer 3 at their connecting position via a window 6 pre-drilled in the insulating layer 3.

Furthermore, a plurality of fifth semiconductor regions Q51, Q5
2... is a window O5 previously bored in the insulating layer 3
1, O52, . . . are connected to a plurality of eighth conductive layers C71, C72, . . . extending above the insulating layer 3, respectively.

The above is the configuration of the embodiment of the semiconductor inverter circuit device according to the present invention.

According to the semiconductor inverter circuit device according to the present invention having such a configuration, the first, second and third
The semiconductor regions Q1, Q2, and Q3; the first insulating layer I1; and the first conductive layer C1 serve as a drain region, a source region, and a channel forming region; a gate insulating film; and a gate electrode, respectively. A first MIS field effect transistor M1 of P-channel type is configured.

Further, the sixth, seventh and eighth semiconductor regions Q6,
MIS field effect transistor in which Q7 and Q8; second insulating layer I2; and second conductive layer C2 serve as a source region, a drain region, a channel forming region, a gate insulating film, and a gate electrode, respectively. A second MIS field effect transistor M2 of N-channel type opposite to M1 is configured.

Furthermore, the sixth, ninth and tenth semiconductor regions Q
6, Q9 and Q10; third insulating film I3; and third conductive layer C8, which are respectively used as a source region, a drain region, and a channel forming region; a gate insulating film; and a gate electrode. Third MIS field effect transistor M3
is configured.

Further, semiconductor substrate 1; first semiconductor region Q1;
and a plurality of fifth semiconductor regions Q51, Q52...
... constitutes a plurality of NPN bipolar transistors T1, T2, etc. each having a common collector region, a common base region, and a plurality of emitter regions.

Then, as shown in Fig. 3, the first and second
MIS field effect transistors M1 and M2 are first
The source region of the second MIS field effect transistor M1 is connected to the fourth conductive layer C3, and the source region of the second MIS field effect transistor M2 is connected to the sixth conductive layer C5 in series. It is connected.

Further, the gate electrodes of the first and second MIS field effect transistors M1 and M2 are connected to the seventh conductive layer C.
6.

Further, the connection midpoint of the first and second MIS field effect transistors M1 and M2 is connected to the bipolar transistors T1 and T through the fifth conductive layer C4.
2... is connected to the base area of...

In addition, bipolar transistors T1, T2...
are connected to their common fourth conductive layer C3, and emitter regions are respectively connected to the eighth conductive layer C3.
conductive layers C71, C72...

Furthermore, a third MIS field effect transistor M3
The source region, drain region and gate electrode of
Sixth, seventh and fourth conductive layers C5, C6 and C
3 are connected to each other.

Since the semiconductor inverter circuit device according to the present invention shown in FIGS. 1 and 2 has the above-described configuration, the fourth conductive layer C3 is positive between the fourth and sixth conductive layers C3 and C5. With the operating power supply 7 connected, if a logic input A that takes positive logic is supplied to the seventh conductive layer C6 using it as an input line, the logic input A becomes "1". Therefore, the first and second MIS field effect transistors M
1 and M2 are turned off and on, and the output obtained at the fifth conductive layer C4 is "0",
For this reason, bipolar transistors T1, T2...
... are both turned off. For this reason, the eighth conductive layer C71, C72... is the seventh conductive layer C in the next stage.
6, the MIS field effect transistor corresponding to the third MIS field effect transistor M3 in the next stage is on, so the eighth conductive layer sexual layer C7
The output obtained at 1, C72, . . . becomes "0".

In addition, if the logic input A becomes "0" from such a state, the first and second MIS field effect transistors M1 and M2 turn off and on, respectively, and the output obtained at the fifth conductive layer C4 is obtained as "1", and therefore both bipolar transistors T1, T2... are turned on, so the output obtained in the eighth conductive layer C71, C72... becomes "1" and obtained. It will be done.

Therefore, according to the semiconductor inverter circuit device according to the present invention shown in FIGS. 1 and 2, for the logic input A supplied to the seventh conductive layer C6, the eighth
A plurality of inverter functions are obtained in which a plurality of logic outputs B1, B2 . . . which are inversions of the logic input A are obtained from the conductive layers C71, C72 .

Such a function has an aspect in which the drain region of the first MIS field effect transistor M1 and the base region of the bipolar transistors T1, T2... are shared, and the bipolar transistors T1, T2... The emitter region of is the first
It is characterized in that it is formed in the drain region of the MIS field effect transistor M1, and can be obtained with an extremely simple and compact configuration.

Also, if logical input A is "1", the first
Since substantially no current flows through the MIS field effect transistor M1 and the bipolar transistors T1, T2, . . ., the above-mentioned functions can be obtained with low power consumption.

Furthermore, the above-mentioned function can be obtained by using the bipolar transistors T1, T2... as output transistors.
The eighth conductive layer C7 serves as an output line because it can flow a larger current than an MIS field effect transistor.
Even if a relatively large parasitic capacitance is added to 1, C72..., this will be charged at a high speed, and therefore,
The logic outputs B1, B2, . . . can be obtained at high speed, and therefore the above-mentioned functions can be obtained at high speed.

Note that the above description is merely an example of the present invention, and the above-mentioned "N-type" is read as "P-type", and "P-type" is read as "N-type", and the above-mentioned "P-type" is read as "N-type".
It is also possible to change the configuration by replacing "channel type" with "N channel type", "N channel type" with "P channel type", and "NPN type" with "PNP type".
Various other modifications and changes may be made without departing from the spirit of the invention.

[Brief explanation of drawings]

FIG. 1 is a schematic plan view showing an example of a semiconductor inverter circuit device according to the present invention. FIG. 2 is a cross-sectional view of - or above. Figure 3 shows
FIG. 3 is a diagram illustrating an example of the configuration of the semiconductor inverter circuit device according to the present invention shown in FIGS. 1 and 2 in terms of an electric circuit. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Principal surface, Q1-Q10... Semiconductor region, I1-I3... Insulating layer, C1-C6, C
8, C71, C72... conductive layer, M1 to M3...
MIS field effect transistor, T1, T2...bipolar transistor.

Claims (1)

[Claims] 1. In a semiconductor substrate having a first conductivity type, first and second semiconductor regions having a second conductivity type opposite to the first conductivity type are formed from the main surface side thereof. A third semiconductor region having a first conductivity type is formed between them and a fourth semiconductor region having a second conductivity type.
A semiconductor region is formed in the first semiconductor region, from the main surface side,
A plurality of fifth semiconductor regions having a first conductivity type are formed in the fourth semiconductor region from the main surface side.
sixth and seventh semiconductor regions having the first conductivity type are formed such that an eighth semiconductor region having the second conductivity type is obtained between them; and a ninth semiconductor region having the first conductivity type A semiconductor region is formed such that a tenth semiconductor region having a second conductivity type is obtained between the semiconductor region and the sixth semiconductor region, and a tenth semiconductor region is formed on the third, eighth and tenth semiconductor regions, respectively. The first, second and third conductive layers are disposed through the first, second and third insulating layers, and the semiconductor substrate, the second semiconductor region and the third conductive layer are connected to a power source. the first semiconductor region is connected to the seventh semiconductor region via the fifth conductive layer, and the fourth and sixth semiconductor regions are connected to a fourth conductive layer connected to one end thereof; a semiconductor region is connected to a sixth conductive layer connected to the other end of the power supply, and the first and second conductive layers and the ninth semiconductor region are connected to a seventh conductive layer as an input line. the plurality of fifth semiconductor regions connected to a conductive layer; each of the plurality of fifth semiconductor regions connected to a plurality of eighth conductive layers as a plurality of output lines; the first, second and third semiconductor regions; a first insulating layer; and the first conductive layer,
A first channel-type MIS field effect transistor is configured in which these are respectively used as a drain region, a source region, and a channel forming region; a gate insulating film; and a gate electrode; the sixth, seventh, and eighth semiconductor regions; a second insulating layer; and the second conductive layer,
A second channel type MIS field effect transistor opposite to the first channel type is configured in which these are respectively used as a source region, a drain region, a channel forming region; a gate insulating film; and a gate electrode; 9 and 10 semiconductor regions; the third insulating layer; and the third conductive layer,
A second channel-type MIS field effect transistor is configured in which these are used as a source region, a drain region, a channel forming region, a gate insulating film, and a gate electrode, respectively, the semiconductor substrate; the first semiconductor region; and the plurality of semiconductor substrates. A semiconductor inverter circuit device comprising a plurality of bipolar transistors each having a common collector region; a common base region; and a plurality of emitter regions.