JPH0151057B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a semiconductor device, and particularly to a wiring structure in a semiconductor device.

(b) Prior art and problems When there are wires routed in parallel inside a semiconductor integrated circuit (IC), signals from one wire are transmitted to the other due to the coupling capacitance between the two wires, causing noise and noise. (coupling noise). In LSIs that handle analog signals, this coupling noise must be reduced to at least 1/1 of the signal level for performance reasons.
It is necessary to keep it below 100 to 1/1000 (40 to 60 dB).

However, recently, as LSIs have become larger,
As the wiring routed in parallel inside an LSI has become significantly longer, it is necessary to suppress the coupling noise generated between parallel wiring lines to 40 to 60 [dB] or less using conventional metal wiring formed only with metal films. is becoming difficult.

(c) Purpose of the Invention The present invention provides a wiring structure that reduces the above-mentioned coupling noise, and its purpose is to improve the performance of LSIs that handle analog signals in particular.

(d) Structure of the Invention In other words, the present invention provides a semiconductor device that has a wiring group on a semiconductor substrate of one conductivity type, and each of some mutually parallel wirings in the wiring group has a metal pattern,
a diffusion region of opposite conductivity type extending below the metal pattern and connected to the metal pattern; The semiconductor device is characterized in that a shield wiring made of a metal pattern is provided which is connected to the semiconductor substrate of one conductivity type via a conductivity type diffusion region.

(e) Examples of the invention Hereinafter, the present invention will be explained using figures.

FIG. 1 is a schematic plan view showing the place where the present invention is applied;
Fig. 2 is an explanatory diagram of coupling noise, and Fig. 3 is a top view of an embodiment of the present invention.
It is a sectional view B as seen from the arrow.

In larger LSIs, as shown in Figure 1, multiple amplifier circuits A ₁ , A ₂ , A _{3 ,} etc., which conventionally formed one LSI, are placed close together. It is often done. In such a case, for example, the output signal lines S 1 , A ₃ , etc. of these amplifier circuits A ₁ , A ₂ , A ₃
S ₂ , S ₃ , S ₀ , etc. are routed long in parallel to the wiring formation area as shown in the figure, and coupling noise between each signal line becomes a problem. The present invention is mainly applied to a place where parallel signal lines are routed for a long time, as shown surrounded by a dotted line Z in the figure.

Figure 2 is a diagram schematically showing the relationship of coupling (coupling) and anti-coupling (decoupling) between two parallel wires. In the figure, L _A and L _B are wires, C _C
is the coupling capacitance (coupling capacitance between wires),
Cd ₁ and Cd ₂ are the decoupling capacitances of the _LA wiring and the _LB wiring ( _LA and _LB are the coupling capacitances between the respective wirings and the substrate), and R is the equivalent resistance.

As mentioned above, there is a coupling capacitance and a decoupling capacitance between the wires routed in parallel as shown in Figure 2.
Coupling noise ₍ dV _B ), which generates coupling capacitance and is induced in the L _B wire by a signal change (dV _A ) in the LA wire, is given by the following equation.

dV _B /dV _A = C _C /Cd ₂ +C _C Therefore, either reduce the coupling capacitance C _C or
By increasing the decoupling capacitance Cd ₂ of the L _B wiring, the noise dV _B induced in the L _B wiring can be reduced.

In the present invention, a strip-shaped diffusion region of a conductivity type opposite to that of the substrate is provided along the wiring pattern on the semiconductor substrate surface below the metal wiring pattern in the signal wiring, and the metal wiring pattern is spread over the entire bottom surface of the semiconductor substrate. Alternatively, by ohmicly connecting the diffusion region at a predetermined portion, the junction capacitance of the diffusion region is added to the metal wiring pattern to increase its decoupling capacitance, and the parallel signal wiring By providing a metal wiring pattern for shielding that is ohmicly connected to the board through a contact diffusion region of the same conductivity type as the board, the coupling capacitance between the signal wires is reduced, and both of these reduce the coupling capacitance between the signal wires. The induced coupling noise is reduced.

Figures 3A and 3B show a top view and a sectional view taken along the line A-A of an embodiment of the structure of the present invention, in which 1 is a p-type silicon substrate, 2 is a field oxide film, and 3a is a p-type silicon substrate; , 3b are n ⁺ type diffusion regions, 4 is an insulating film such as phosphosilicate glass, 5a, 5b, 5c are electrode contact windows, and 6a, 6b, 6c are wiring lines L _A , L _B , L _S made of aluminum, etc., respectively. Metal wiring pattern, 7 is p-type contact diffusion region, L _A ,
L _B represents signal wiring, and L _S represents shield wiring.

That is, in this structure, the metal wiring patterns 6a and 6b of the signal wirings L _A and L _B are formed by band-shaped n ⁺ -type diffusion regions 3a and 3a, respectively, which are disposed on one surface of the p-type silicon substrate along the wiring patterns. For example, the signal wiring _L
L _B is formed into a wiring having good conductivity due to the metal wiring patterns 6a and 6b and a large decoupling capacitance due to the junction capacitance of the n ⁺ type diffusion regions 3a and 3b. Furthermore, in the structure of the present invention, a contact diffusion region of the same conductivity type as the substrate is provided between the signal wires in a region where the signal wires L _A and L _B run parallel to each other, along these signal wires.
p type substrate 1 via p ⁺ type contact diffusion region 7
A shield wiring L _S made of a metal wiring pattern 6c which is electrically connected to the signal wiring L _A and LB is provided, thereby reducing the coupling capacitance between the signal wiring LA and _LB.

In order to further increase the effect of reducing coupling noise between the signal lines L _A and L _B in the structure of the above embodiment, the n ⁺ type diffusion regions 3a and 3b in the signal lines L _A and L _B are The metal wiring pattern 6c of the shield wiring L _S is made as wide as possible to increase the junction capacitance, and the width of the metal wiring patterns 6a and 6b in the L _A and L _B is narrowed. The width of L A should be made as wide as possible, and the width of L _A
It is desirable to increase the shielding effect by making the distance between the metal wiring patterns 6a and 6b of L _B and the metal wiring pattern 6c of L _S as narrow as possible. To give an example of the numerical values, the width W ₁ of the n ⁺ type diffusion regions 3a, 3b = 10 [μm], the width W ₂ = 6 [μm] of the metal wiring patterns 6a, 6b, the width W ₃ = of the metal wiring pattern 6c. 8 [μm], width W ₄ of p ⁺ type contact diffusion region 7 = 6 [μm], distance d ₁ between metal wiring patterns 6a, 6b and 6c = 5 [μm], n ⁺ type contact diffusion region 3a, 3b and The distance d ₂ from the p ⁺ type contact diffusion region 7 is approximately 4 [μm].

In the structure of the present invention, the metal wiring patterns 6a, 6b and the n ⁺ type diffusion regions 3a, 3b in the signal wirings L _A and L _B are located on the lower surface of the entire metal wiring pattern as in the above embodiment. Although it is most desirable to connect at a plurality of locations, a structure in which connections are made at a plurality of locations through a plurality of contact windows is also sufficiently effective.

Further, the metal wiring pattern 6c of the shield wiring L _S and the contact diffusion region 7 may be connected throughout the lower part of the metal wiring pattern 6c.

Furthermore, in the structure of the present invention, the signal wiring L _A , L _B
Even if one of the wirings consists of only a metal wiring pattern as before, the coupling and
Noise is significantly reduced.

Furthermore, as a modification of the structure of the present invention, it is also effective to some extent that the shield wiring is not provided and the signal wiring is formed only by the wiring made of the metal wiring pattern and the diffusion layer.

Further, it is also effective to provide shield wiring as shown in the above embodiment between signal wirings consisting only of metal wiring patterns.

(f) Effects of the Invention As explained above, according to the present invention, it is possible to reduce the coupling capacitance between signal wires arranged in parallel and to increase the decoupling capacitance of the signal wires themselves.

Therefore, according to the present invention, coupling noise induced in signal wiring arranged side by side can be reduced, so it is particularly suitable for handling analog signals.
LSI performance can be improved.

[Brief explanation of drawings]

FIG. 1 is a schematic plan view showing the place where the present invention is applied;
Fig. 2 is an explanatory diagram of coupling noise, and Fig. 3 is a top view of an embodiment of the present invention.
It is a sectional view B as seen from the arrow. In the figure, 1 is a p-type silicon substrate, 2 is a field oxide film, 3a, 3b are n ⁺ type diffusion regions, 4 is an insulating film, 5a, 5b are electrode contact windows, 6a,
6b is a metal pattern, 7 is a p ⁺ type contact diffusion region, L _A and L _B are signal wirings, and L _S is a shield wiring.

Claims (1)

[Claims] 1. A wiring group is provided on a semiconductor substrate of one conductivity type, and each of some of the wirings in the wiring group that are parallel to each other,
It is composed of a metal pattern, and an opposite conductivity type diffusion region extending along the metal pattern below the metal pattern and connected to the metal pattern, and further between these wirings. 1. A semiconductor device comprising: a shield wiring made of a metal pattern connected to a semiconductor substrate of one conductivity type via a diffusion region of one conductivity type along the semiconductor substrate.