JPH0151091B2 - - Google Patents

Description

[Detailed Description of the Invention] This invention utilizes a power MOS to convert current flowing into a load into a power MOS
The present invention relates to a semiconductor switch circuit in which switching is performed using a transistor, and particularly to a semiconductor switch circuit having a function of blocking the current flowing through the power MOS transistor and thereby protecting the transistor during a load shot or the like.

In recent years, there has been a desire to simplify and integrate drive circuits and reduce the power supply voltage.
There is a movement to apply MOS transistors, especially vertical power MOS transistors, which have low on-resistance and are suitable for power switching.
(Refer to the MOS-IC and FET issue report issued on July 10, 1970.) However, in semiconductor switch circuits using such power MOS transistors, the gate cannot be connected when the load connected to the drain side is short-circuited. When the potential becomes "H", the drain current increases in addition to the drain potential, so the power loss determined by the product of the two rapidly increases.
Eventually, there was a problem that the power MOS transistor was destroyed.

Therefore, as a countermeasure against this problem, conventionally, as shown in FIG _.
The detected voltage is compared with a predetermined reference voltage Vref in a comparator 4, and the drive circuit 5 inserted between the gate G and the input terminal IN uses the comparison output to detect the change in voltage. Attempts have also been made to protect the power MOS transistor 1 by driving the power MOS transistor 1 and forcibly lowering the potential of the gate G to "L" during load shot.

However, with such a circuit configuration, unnecessary power is constantly consumed by the microresistance 3, which hinders the reduction of loss in the entire switch circuit.Furthermore, when integrating on a semiconductor substrate, the microresistance is generally There was a problem in that the occupied area was large, which hindered high integration.

Furthermore, if a vertical power MOS transistor with low on-resistance is used as the power MOS transistor 1, and the entire circuit is integrated on the same semiconductor substrate, in the case of a vertical power MOS transistor, the substrate itself acts as a drain. Therefore, the substrate potential is unstable, making it difficult to integrate other circuit components (e.g., comparator 4, drive circuit 5, etc.) within the substrate and using external components, which is disadvantageous in terms of cost. There was a problem that I had to do it.

The present invention was made in view of these conventional problems, and its purpose is to provide a semiconductor switch circuit that has a small switch drive current and power loss, and is equipped with a protection circuit that can be integrated. It's about doing.

In order to achieve the above object, the present invention provides a protection circuit that protects the transistor by determining the shorting of the load based on the drain potential of the power MOS transistor that switches the load. and M.O.S.
This device is characterized by being composed of a capacitor and a resistor formed on silicon oxide.

Hereinafter, the present invention will be explained in detail based on the embodiments shown in FIGS. 2 to 7.

FIG. 2 is a circuit diagram showing an embodiment of the semiconductor switch circuit according to the present invention.

In FIG. 2, 6 is an n-channel vertical power MOS transistor, the source S ₆ of this transistor 6 is installed, the drain D ₆ is connected to the power supply V _DD via a load 7, and the gate _G6 is connected to the control input terminal IN via a resistor 8.

Therefore, the potential V _IN of the control input terminal IN is “L”
When the potential of the gate G6 changes instantaneously from "H" to "L" or from "H" to "L", the potential of the gate _G6 rises or falls while drawing a time constant curve determined by the resistor 8 and the gate capacitance C _G. It is configured to switch the current _ID flowing through the load 7 by turning it on or off.

9 is an n-channel lateral MOS transistor, the source S ₉ of this transistor 9 is grounded, and the drain D ₉ is connected to the gate G ₆ of the transistor 6.

Therefore, when the gate potential V _G9 of the transistor 9 reaches its threshold voltage V _T9 , the transistor 9 is turned on, thereby lowering the gate potential V _G6 of the transistor 6 to ground potential.

An integrating circuit 12 consisting of a MOS resistor 10 and a MOS capacitor 11 connected in series is provided between the drain D ₆ of the transistor 6 and the ground. Because a short-circuited n-channel lateral MOS transistor is used,
The MOS resistor 10 also functions as a constant current source. Further, the output of the integrating circuit 12 is supplied to the gate G ₉ of the transistor 9, so that the output of the integrating circuit 12 increases and the gate G 9 of the transistor 9 increases.
As soon as the threshold voltage V _T9 is exceeded, the transistor 9 turns on.

Reference numeral 13 denotes an n-channel lateral MOS transistor that forms a discharge path for the capacitor 11 of the integrating circuit 12. Its source S ₁₃ is grounded, and its drain D ₁₃ is connected to the output terminal of the integrating circuit 12. Therefore, when the gate potential V _G13 of the transistor 13 rises and exceeds the threshold voltage V _T13 , the transistor 13 is turned on and the capacitor 1
The charge of 1 is rapidly discharged, and the output of the integrating circuit 12 falls to approximately zero potential.

14 is a resistor 15 and an n-channel horizontal MOS
This is an inverter circuit formed by connecting a transistor 16 in series, and this inverter circuit 14 is supplied with the drain potential V _D6 of the transistor 6 as a power supply, and the gate potential G ₁₆ of the transistor 16 is supplied as a power supply.
is connected to the control input terminal IN.

Therefore, the inverter circuit 14 has a control input terminal
The switching input supplied to IN is inverted and output, and the transistor 13 is controlled to be turned on or off by this inverted output.

Next, the operation of the semiconductor switch circuit described above will be explained separately, with reference to the time chart of FIG. 3, when the load is normal and when the load is short.

The operating time chart under normal load conditions is shown in Figure 3a. As shown in the figure, when the input potential V _IN rises from "L" to "H" to turn on the transistor 6, the gate potential V _G6 of the transistor 6 is the resistance value R of the resistor 8 and the gate capacitance C of the transistor 6. _G
It begins to rise slowly with a time constant τ (=C _G · R) determined by .

Next, when t ₁ time has elapsed since the rise of the input potential V _IN and the gate potential V _G6 of the transistor 6 exceeds its threshold voltage V _T6 , the transistor 6 turns on and the drain current I flows into the load 7. _D begins to flow, and at the same time, the drain potential V _D6 of the transistor 6 begins to decrease due to the voltage drop caused by the load 7.

On the other hand, at the same time that the input potential V _IN rises from "L" to "H", the output of the inverter circuit 14 changes from "H" to "L", thereby turning off the transistor 13 and turning off the integrator circuit 12. Charging of the capacitor 11 is started, and the value of the output potential V ₁ of the integrating circuit 12 rises more slowly than the gate potential V _G6 of the transistor 6.

Therefore, before the output potential V ₁ of the integrating circuit 12 reaches the threshold voltage V _T9 of the transistor 9, that is, from the rise of the input potential V _IN , t ₂
As time passes, the drain potential V _D6 of the transistor 6 drops below the threshold voltage V _T9 of the transistor 9, and as a result, the output potential V ₁ of the integrating circuit 12 becomes V ₁ = V _D6 − V _T10 − V _BG V _D6 ; Value when V ₁ stops rising V _T10 ; Threshold voltage of MOS resistor 10 V _BG ; Clipped to the value given by the back gate effect.

Here, if it is set so that V ₁ <V _T9 , the value of the integral output V ₁ will not rise to V _T9 , so
The gate potential V _G6 of the transistor 6 is maintained at the "H" state, and the current _ID continues to flow through the transistor 6.

Next, in order to turn off transistor 6, the input potential
When V _IN instantaneously falls from "H" to "L", the electric charge charged in the gate capacitance C _G of transistor 6 is discharged through resistor 8, and then when V _G6 < V _T6 , the transistor 6 is completely turned off, and the drain current _ID no longer flows.

Further, the charge stored in the capacitor 11 is also rapidly discharged through the transistor 13, and as a result, the output potential _V1 of the integrating circuit 12 decreases to approximately zero volts.

In this way, as long as the load 7 is normal, the transistor 6 will be normally switched depending on the "H" or "L" level of the input potential V _IN .

Next, an operation time chart during load shot is shown in FIG. 3b. In the same figure, in order to turn on transistor 6, input potential V _IN is set to “L”.
When the voltage is raised to "H" from t, the gate potential V _G6 of the transistor 6 starts to rise along a predetermined time constant curve in the same manner as when the load is normal as described above, and after t ₁ hour has passed, V _G6 = V _T6 At the point in time, the transistor 6 shifts to the on state, and the drain current
_ID begins to flow.

Further, since the load 7 is shorted, the power supply voltage V _DD is directly applied to the drain D ₆ of the transistor 6, and therefore the drain potential V _D6 is maintained at V _DD .

On the other hand, the output potential _V1 of the integrating circuit 12 also starts to rise gradually in response to the rise of the input potential _VIN , but even when the transistor 6 is turned on, the drain potential _VD6 is maintained at the power supply voltage _VDD . Therefore, unlike the case where the load is normal as described above, the integration circuit 1
The rise in the output potential V ₁ of the transistor 2 continues further, and eventually exceeds the threshold voltage V _T9 of the transistor 9 after the elapse of time t ₃ .

Then, the transistor 9 is turned on and the gate potential V _G6 of the transistor 6 starts to decrease, and the drain current _ID also starts to decrease gradually. and,
When ₄ hours have passed and V _G6 < V _T6 , the drain current I _D stops flowing completely.

Therefore, the drain current I _D is low when the input potential V _IN is “L”.
Since the current only flows for an extremely short period of time (t ₄ − _{t 1} ) from the time when the voltage rises to “H” from the current level, it prevents the switching element from being destroyed due to power loss as in conventional switching circuits. can do.

Here, the values of the times t ₁ , t ₂ , and t ₄ are MOS resistance 1
Gate width/gate length of 0, MOS capacitor 11
It can be set appropriately by changing the capacitance of the resistor 8 and the resistance value of the resistor 8.

Next, when the input potential V _IN falls from "H" to "L", the charge in the capacitor 11 is rapidly discharged through the transistor 13 in the same way as when the load is normal, and the integrator circuit is in a reset state.

Note that if the load 7 is suddenly shunted while the load 7 is normal and the transistor 6 is on, the output potential V ₁ of the integrating circuit 12 will be lower than the previous level as shown in FIG. 3a. Immediately it started to rise, and after a short period of time, Fig. 3b
The threshold voltage of transistor 9 as shown in
V _T9 is exceeded, and from then on the gate potential of transistor 6 decreases as shown in figure b, and the drain current
_ID will be blocked.

Thus, in the protection circuit shown in this embodiment, since the shot of the load 7 is detected based on the value of the drain potential V _D6 of the transistor 6, a small resistance is connected to the source side of the transistor 6. As in the conventional example in which the short of the load 7 is detected based on the change in the load current by inserting the
While the transistor 7 is on, no power is wasted due to the minute resistance.

Further, according to this embodiment, the discharging transistor 13 is connected in parallel with the MOS capacitor 11 constituting the integrating circuit 12, and the transistor 13 is connected via the inverter circuit 14 by an inverted signal of the switching input. Due to on/off control, the input potential V _IN changes from “H” to “L”
When V 1 falls, the output V ₁ of the integrating circuit 12
becomes "L" immediately, and even if "H" is repeatedly supplied to the input terminal IN at minute intervals, there will be little variation in the delay time of the integrating circuit 12.
In addition, since a constant current source with the drain and gate shorted is used as the MOS resistor 10, the output potential V ₁ of the integrating circuit 12 increases temporarily as a function of time, and when a simple linear resistor is used. Compared to , it is easier to set the delay time,
A highly accurate integration circuit can be constructed.

In addition, in this embodiment, an n-channel source common power source is used as a power switching element.
In addition to using a MOS transistor 6, an n-channel source-grounded MOS transistor 9 is used as a gate shorting element, and a MOS transistor 9 is used as an integrating circuit.
Resistor 10, MOS capacitor 11, discharge element 1
3 and inverter element 16, respectively.
Since channel source-grounded MOS transistors are used, even if a vertical element with extremely low on-resistance is used as a power MOS transistor, it can be easily installed on the same semiconductor substrate without any special isolation. can be integrated into

Also, an input resistor 8 connected to the gate of the power transistor and a load resistor 1 of the inverter circuit
Regarding No. 5, since all of them require a relatively large resistance value, their occupied area is also small, and high-density integration is therefore possible.

Further, in this embodiment, the transistor 9
Since the drain potential V _D6 of the power MOS transistor 6 is used as the power supply of the integrating circuit 12 that drives the integrator circuit 12 and the gate voltage of the MOS resistor 10,
Even in the case of a large-capacity lamp load where the drain potential V _D6 slowly decreases after the transistor 6 is turned on, the output ratio of the integrating circuit 12 (when shot/normally) can be set to a large value. This has the effect of shortening the time required to decide whether or not to use it.

This effect can be observed when directly detecting the drain potential V _D6 of the power MOS transistor 6 to determine whether or not there is a short, that is, after the input potential rises from "L" to "H", a certain period of time has elapsed. Even if the drain potential V _D6 is “H”, the fourth
This will be explained with reference to the figures.

Figure 4a shows the drain potential under normal load.
Figure 4b shows the changes in V _D6 and the integral output V ₁ , and Figure 4b shows the drain potential V _D6 during load shoot.
and shows the change in product output V ₁ . As shown in Figure 4a, power supply voltage V _DD = 12 volts, input potential V _IN
When “H” is 5 volts, load 7
When a large-capacity lamp is used as the load 7, if the load 7 is normal, at least T ₁ hour is required for the drain potential V _D6 to drop to the threshold voltage V _T (≒1 to 2 volts) of the MOS transistor. .

Therefore, if the threshold voltage V _T of the MOS transistor is used and the drain potential V _D6 is V _T
If you want to determine whether the load 7 is short-circuited based on whether or not the switching input
It takes T ₁ hour after V _IN becomes “H”.
Here, the current continues to flow through the transistor 6 during the time _T1 , so if the load 7 has a large capacity, there is a risk of damaging the transistor 6 due to the lengthening of the time _T1 (10ms). be.

However, in this embodiment, since the drain potential V _D6 is used as the input of the integrating circuit 12, the rise curve of the integral output V ₁ in a state where the load 7 is normal and the drain potential V _D6 is decreasing, and the load There is a significant difference between the rise curve of the integral output V 1 and the rise curve of the integral output V ₁ in a state where the drain potential V _D6 is maintained constant by shortening the drain potential V D6 . That is,
When the load is normal, the integrated output V ₁ does not exceed the threshold voltage V _T9 of transistor 9, whereas when the load is shunting, V ₁ rises in only T ₂ hours after V _IN rises. Since V _T9 is exceeded, it is possible to determine whether the load is normal or short within T ₂ hours, which is shorter than T ₁ , and damage to the transistor 6 can be prevented.

Next, the structure of each part when the semiconductor switch circuit explained above is integrated on the same chip is shown in the fifth section.
This will be explained with reference to FIGS.

Fig. 5 shows the structure of the transistor 6, and Fig. 6 shows the structure of the transistor 6.
The structure of MOS resistor 10 and MOS capacitor 11 is
FIG. 7 shows the structure of the resistor 8 and another MOS transistor 9, respectively.

FIG. 5 shows the structure of a known vertical MOS transistor, in which 61 is a source electrode, 62 is a gate electrode, 63 is a drain electrode, 64 is a source region, 65 is a channel forming region, 66 is a drain region, 67 is a high concentration region, and 68 is a substrate.

Then, the current flows from the n-type drain region 66 to the p
The n-type source region 6 passes through a channel formed under the gate electrode of the type channel formation region 65.
Flows to 4. According to this structure, since current can flow approximately vertically, on-resistance can be reduced,
This makes it suitable for power switching.

FIG. 6 shows a channel formation region 105 formed in the drain region 66 of the vertical MOS transistor shown in FIG. . In the figure, 101 is a source electrode, 102 is a gate electrode, 103 is a drain electrode, 104 is a source region, 105 is a channel forming region, 106 is a drain region, 107 is a high concentration region, and 11 is a MOS capacitor.

As shown in the figure, the capacitor 11 is formed by sandwiching a gate SiO ₂ film between a grounded n-type impurity high concentration region as a lower surface electrode and Al as an upper surface electrode. Further, the MOS resistor 10 and the MOS capacitor 11 are connected to a grounded channel forming region 105.
Since the vertical power MOS transistor 6 is turned on and the potential of the drain region 66 fluctuates, its characteristics do not change.

7, similarly to FIG. 6, a p-type channel forming region 95 is formed in the drain region 66 of the vertical power MOS transistor 6, and a horizontal MOS
A transistor 9 is shown. The figure also shows an input resistor 8 made of poly-Si.

In the figure, 8 is a poly-Si resistor, 91 is a source electrode, 92 is a gate electrode, 93 is a drain electrode,
94 is a source region, 95 is a channel forming region,
96 is a drain region, and 97 is a high concentration region.

Since both the source region 94 and the channel forming region 95 are grounded by the source electrode 91,
Even if the potential of the drain region 66 changes due to switching of the vertical power MOS transistor 6, the potential of the channel forming region 95 is not affected, so that the horizontal MOS transistor 9 operates normally. Also, poly−Si
Since the resistor 8 is formed of poly-Si on the field SiO ₂ , it is completely insulated from the drain region 66 and is not affected by potential fluctuations in the drain region 66 .

Thus, with the structure shown in FIGS. 5 to 7, the semiconductor switch circuit shown in FIG. 2 can be integrated on the same chip as the vertical MOS transistor 6.

In the above embodiment, each circuit element is integrated on the same chip, but it is of course possible to obtain the desired circuit effect even if each circuit element is formed from discrete components.

As is clear from the above description of the embodiments, according to the present invention, it is possible to provide a semiconductor switch circuit with a short switch protection circuit that has a small switch drive current and power loss and can be integrated.
In particular, this shot protection circuit has the advantage of high shot detection responsiveness.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing a conventional semiconductor switch circuit, Fig. 2 is a circuit diagram showing a semiconductor switch circuit according to the present invention, and Fig. 3 shows the operation of the inventive circuit divided into normal load and load shot conditions. 4 is a diagram showing the operation of the circuit of the present invention in comparison with the operation of other circuits, FIG. 5 is a diagram showing the structure of a vertical power MOS transistor, and FIG. 6 is a diagram showing the MOS resistor and MOS
FIG. 7 is a diagram showing the structure of a capacitor, and FIG. 7 is a diagram showing the structure of a poly-Si resistor and a lateral MOS transistor. 6...First MOS transistor, 7...Load,
8...Input resistance, 9...Second MOS transistor, 10...Integrated circuit, 13...Third MOS transistor, 14...Inverter circuit.

Claims (1)

[Claims] 1. A first switch that switches the current flowing through the load.
a MOS transistor; an input resistor connected between the gate of the first MOS transistor and an input terminal; an integration circuit charged with the drain potential of the first MOS transistor; a second MOS transistor that is connected to the gate of the first MOS transistor and performs a switching operation based on the output of the integrating circuit; an inverter circuit that inverts the switching input at the input terminal; a third circuit connected to the output terminal of the integrator circuit and operated by the output of the inverter circuit;
A semiconductor switch circuit characterized by consisting of a MOS transistor.