JPH0152919B2 - - Google Patents
Info
- Publication number
- JPH0152919B2 JPH0152919B2 JP2451280A JP2451280A JPH0152919B2 JP H0152919 B2 JPH0152919 B2 JP H0152919B2 JP 2451280 A JP2451280 A JP 2451280A JP 2451280 A JP2451280 A JP 2451280A JP H0152919 B2 JPH0152919 B2 JP H0152919B2
- Authority
- JP
- Japan
- Prior art keywords
- hole
- inner layer
- wiring board
- outer layer
- reference hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 31
- 239000011889 copper foil Substances 0.000 claims description 28
- 238000000034 method Methods 0.000 claims description 25
- 238000000465 moulding Methods 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 238000005553 drilling Methods 0.000 claims description 5
- 239000010410 layer Substances 0.000 description 72
- 239000011347 resin Substances 0.000 description 24
- 229920005989 resin Polymers 0.000 description 24
- 239000000463 material Substances 0.000 description 10
- 239000004020 conductor Substances 0.000 description 6
- 238000003475 lamination Methods 0.000 description 5
- 239000011521 glass Substances 0.000 description 4
- 238000003825 pressing Methods 0.000 description 4
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000000499 gel Substances 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 238000004364 calculation method Methods 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000004744 fabric Substances 0.000 description 2
- 239000012530 fluid Substances 0.000 description 2
- 230000005484 gravity Effects 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 239000002759 woven fabric Substances 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- DGAQECJNVWCQMB-PUAWFVPOSA-M Ilexoside XXIX Chemical compound C[C@@H]1CC[C@@]2(CC[C@@]3(C(=CC[C@H]4[C@]3(CC[C@@H]5[C@@]4(CC[C@@H](C5(C)C)OS(=O)(=O)[O-])C)C)[C@@H]2[C@]1(C)O)C)C(=O)O[C@H]6[C@@H]([C@H]([C@@H]([C@H](O6)CO)O)O)O.[Na+] DGAQECJNVWCQMB-PUAWFVPOSA-M 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000004040 coloring Methods 0.000 description 1
- 230000000994 depressogenic effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004049 embossing Methods 0.000 description 1
- 238000001879 gelation Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000007373 indentation Methods 0.000 description 1
- 239000002648 laminated material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000007788 roughening Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910052708 sodium Inorganic materials 0.000 description 1
- 239000011734 sodium Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
【発明の詳細な説明】
本発明は、新規な多層印刷配線板の製造法に関
し、予め内層配線板に設けた基準穴ガイドマーク
の座ぐり出しを容易とした多層印刷配線板の製造
法である。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a novel method for manufacturing a multilayer printed wiring board, and is a method for manufacturing a multilayer printed wiring board that facilitates countersinking of reference hole guide marks provided in advance on an inner layer wiring board. .
多層印刷配線板の積層成形における主要な問題
点は、内層、外層配線間の位置決めと層間接着に
ある。 The main problems in lamination molding of multilayer printed wiring boards are the positioning and interlayer adhesion between the inner layer and outer layer wiring.
層間接着は、内層印刷配線板の製造に使用する
銅箔として粗面化処理や接着用メツキ処理を施し
たものを用いる方法、内層用印刷配線板を製造
後、銅箔表面を機械的に処理する方法(粗面化処
理−ホーニング等)、化学的に処理する方法(エ
ツチング、酸化処理−着色処理等、例えば、特許
庁編、発明協会発行昭和54年8月20日「特許から
みた多層印刷配線技術」の第185〜189頁、発明協
会公開技法の公技番号78−180等)を行う方法並
びにこれらの組合せなど種々あり、また、ボイド
の発生を防止するためには、用いるプリプレグの
枚数と成形プログラムを制御してプリプレグ中の
含浸樹脂が一旦流動状態になつたときに、導体間
の空気を該樹脂で追い出し、該樹脂を充填し、か
つ、過剰な樹脂の流失を起こさないようにする方
法が最も一般的であり、特殊な場合−特にプリプ
レグからの樹脂流れを小さく押えたり、絶縁層の
厚みを内層銅箔の厚みに比較してうすくする必要
がある場合、層間絶縁樹脂層の厚み精度を極めて
厳密に制御する必要がある場合等−においては、
内層配線板として配線銅箔と絶縁樹脂基板面とを
予めフラツトにしたものを使用する方法などがあ
る。 Interlayer adhesion is achieved by using copper foil that has been roughened or plated for adhesion to produce the inner printed wiring board, or by mechanically processing the surface of the copper foil after producing the inner printed wiring board. (surface roughening treatment - honing, etc.), chemical treatment methods (etching, oxidation treatment - coloring treatment, etc.), for example, "Multilayer printing from a patent perspective" edited by the Japan Patent Office, published by Japan Institute of Invention and Innovation, August 20, 1974 There are various methods and combinations of these (e.g., pages 185 to 189 of "Wiring Technology", Public Technical No. 78-180 of the Japan Institute of Invention and Innovation Publication Techniques), and in order to prevent the occurrence of voids, the number of prepregs used must be By controlling the molding program and once the impregnated resin in the prepreg becomes fluid, the air between the conductors is expelled by the resin, the resin is filled, and the excess resin is prevented from flowing away. This is the most common method, and in special cases - especially when it is necessary to suppress the flow of resin from the prepreg or to make the thickness of the insulating layer thinner compared to the thickness of the inner layer copper foil, the method of interlayer insulating resin layer In cases where it is necessary to control thickness accuracy extremely strictly,
There is a method in which a wiring copper foil and an insulating resin substrate surface are made flat in advance as an inner layer wiring board.
また、内層配線と外層配線との位置合わせの方
法としては、同様に前記に引用した「特許からみ
た多層印刷配線技術」の第194〜196頁に記載さ
れ、.成形時の位置合せ用の基準穴等を有する
配線網を形成した多数組みの多層化材を該基準穴
等にピンを差し込んで一回の多層化成形により多
層板とする方法と.基準穴ガイドマークを予め
設けた内層配線板に外層用のプリプレグ及び銅箔
又はプリプレグと片面銅張積層板とを重ね多層化
成形した後、該基準穴ガイドマーク部分を座ぐり
出して基準穴をあけ、該基準穴に基づいて外層の
回路形成を行う方法の二つが一般的である。 Furthermore, a method for aligning inner layer wiring and outer layer wiring is described on pages 194 to 196 of ``Multilayer Printed Wiring Technology from a Patent Perspective'' cited above. A method of forming a multilayer board by inserting pins into the reference holes, etc. of multiple sets of multilayer materials forming a wiring network having reference holes, etc. for positioning during molding, and performing multilayer molding once. After forming a multi-layer structure by stacking outer layer prepreg and copper foil or prepreg and single-sided copper clad laminate on an inner layer wiring board on which reference hole guide marks have been provided in advance, the reference hole guide marks are counter-sunk and the reference holes are formed. There are two common methods: drilling a hole and forming a circuit on the outer layer based on the reference hole.
前記の方法の場合、多層化成形後、基準穴ガ
イドマークは積層した外層により隠れるので、基
準穴をあけるためには「座ぐり」を行い、基準穴
ガイドマークを露出させて基準穴をあけることが
必要となる。ところが、該基準穴ガイドマーク部
は通常、積層した外層により隠蔽されているので
座ぐりのために、内層パターンのフイルムをあて
て大体の位置を決めたり、内層パターンの「浮き
だし」があればそれを見て位置を決めて座ぐりを
行つていた。しかしながらこの方法では座ぐりの
位置決めが難しく、作業時間が長くかかる等の欠
点があり、特に外層と中間層(内層)までの距離
が大きい層構成の場合には内層パターンの浮きだ
しが殆どなくなり、その欠点が顕著であつた。 In the case of the above method, after multi-layer molding, the reference hole guide mark is hidden by the laminated outer layer, so in order to make the reference hole, "spot boring" is performed to expose the reference hole guide mark and then drill the reference hole. Is required. However, the reference hole guide mark part is usually hidden by the laminated outer layer, so in order to counterbore, it is necessary to apply a film of the inner layer pattern to determine the approximate position, or to correct any ``embossed'' part of the inner layer pattern. I looked at it, decided on a position, and then proceeded to counterbore. However, this method has drawbacks such as difficulty in positioning the counterbore and long working time.Especially in the case of a layer structure in which the distance between the outer layer and the middle layer (inner layer) is large, the inner layer pattern hardly becomes embossed. The shortcomings were noticeable.
この座ぐりをしなくてよい改良法として、内層
配線板に予め形成した基準穴ガイドマーク部分に
基準穴を設け、この基準穴が外層の積層材の外部
(=周囲)となり外層材で覆われないようにして
外層材を重ね多層化成形する方法があるが、この
方法は、内層材の基準穴ガイドマーク部分と内層
印刷配線部分とを予め離れた設計としておくこと
が必須であり、更に、基準穴ガイドマーク部分と
外層材により被覆される部分との熱、圧力の負荷
が異なることに基づく寸法変化挙動の差などの問
題があり、適用可能な多層板に制限がるものであ
つた。 As an improvement method that does not require counterboring, a reference hole is provided in the reference hole guide mark part previously formed on the inner layer wiring board, and this reference hole becomes the outside (=surrounding) of the outer layer laminate material and is covered with the outer layer material. There is a method of stacking the outer layer material and forming a multi-layer molding so that the inner layer material does not overlap, but in this method, it is essential to design the reference hole guide mark part of the inner layer material and the inner layer printed wiring part to be separated in advance, and furthermore, There are problems such as differences in dimensional change behavior due to differences in heat and pressure loads between the reference hole guide mark portion and the portion covered by the outer layer material, which limits the applicable multilayer plates.
本発明は、上記の方法において、基準穴ガイ
ドマークの座ぐりをより簡便に行う方法について
鋭意検討した結果、上記の欠点を克服する方法を
見出し完成したものである。 The present invention has been completed as a result of intensive study on a method for more easily counterboring reference hole guide marks in the above method, and by discovering a method for overcoming the above drawbacks.
すなわち、本発明は、基準穴ガイドマークを設
けた内層配線板に、外層用のプリプレグ及び銅箔
を重ね多層化成形した後、該ガイドマークに基準
穴を形成し、該基準穴に基づいて外層の回路形成
を行う多層印刷配線板の製造法において、内層配
線板として該ガイドマークの中心部に基準穴径よ
りも小さな穴をあけた内層配線板を用いて多層化
成形し、多層板の該ガイドマーク部に形成された
へこみ部分を座ぐり出し、基準穴をあけた後、該
基準穴に基づいて外層の配線形成を行なうことを
特徴とする多層印刷配線板の製造法である。 That is, in the present invention, prepreg and copper foil for the outer layer are stacked and formed into a multilayered structure on an inner layer wiring board provided with a reference hole guide mark, and then a reference hole is formed in the guide mark, and the outer layer is formed based on the reference hole. In a method for manufacturing a multilayer printed wiring board that forms a circuit, an inner layer wiring board with a hole smaller than the reference hole diameter in the center of the guide mark is used as an inner layer wiring board to form a multilayer printed wiring board, and the This method of manufacturing a multilayer printed wiring board is characterized in that a recessed portion formed in a guide mark portion is counterbored, a reference hole is made, and then wiring in an outer layer is formed based on the reference hole.
本発明において、基準穴ガイドマークの中心部
に基準穴径よりも小さな穴をあけた内層配線板を
用いると、穴の部分は空洞であるために上下のプ
リプレグより樹脂が流れ込みそのまま加熱硬化さ
れる。このとき、穴が上下のプリプレグより流入
する樹脂量と同容積程度以上である場合或いは印
刷配線銅箔間〓を埋めるに充分な樹脂量よりも大
幅に大きい場合には、該穴部に空〓ができたまま
で硬化されるか或いは該穴部の樹脂により充填さ
れるが、その他の部分に比較して極めて低圧の圧
力を受けた状態で硬化されることとなる。その結
果、穴周囲に形成された基準穴ガイドマーク部分
と穴とは積層成形圧力が大幅に異なつたものとな
り、内層パターンの「浮きだし」を強調したこと
と同様の理由により基準穴ガイドマークが浮きだ
し、且つ、穴部の凹みとして容易に目視で認識さ
れるものとなる。 In the present invention, when using an inner layer wiring board with a hole smaller than the reference hole diameter in the center of the reference hole guide mark, since the hole is hollow, resin flows from the upper and lower prepregs and is heated and cured as it is. . At this time, if the volume of the hole is at least the same as the amount of resin flowing in from the upper and lower prepregs, or if the amount of resin is significantly larger than the amount of resin sufficient to fill the gap between the printed wiring copper foils, the hole should be filled with air. Either the hole is cured as it is, or the hole is filled with resin, but the hole is cured under extremely low pressure compared to other parts. As a result, the lamination molding pressure was significantly different between the reference hole guide mark part formed around the hole and the hole, and for the same reason as emphasizing the "embossedness" of the inner layer pattern, the reference hole guide mark was This will be easily recognized visually as an embossment and a depression in the hole.
この理由は以下のごとく推定される。 The reason for this is presumed to be as follows.
従来の多層化積層成形において、内層配線パタ
ーンの「浮きだし」は、上記した如く、内層パタ
ーンと外層との間の距離が小さい場合、すなわち
中間に重ねるプリプレグの厚みや枚数が相対的に
少ない場合には顕著となる。また、銅張積層板、
多層板等の銅箔の表面はプリプレグに使用したガ
ラス織布(通常、平織布)の織り目が明白に認識
されるものである。 In conventional multilayer lamination molding, the inner layer wiring pattern ``emerges'' when the distance between the inner layer pattern and the outer layer is small, that is, when the thickness and number of prepregs stacked in the middle are relatively small, as described above. It becomes noticeable. In addition, copper clad laminates,
On the surface of a copper foil such as a multilayer board, the weave of the glass woven fabric (usually a plain woven fabric) used for the prepreg can be clearly recognized.
まず、プリプレグに含浸した樹脂は積層成形時
の初期においては加熱により一旦流動状態とな
り、内層配線板の配線銅箔間に流入し、間〓を埋
めた後、ゲル化し、ついで完全に硬化するもので
あり、一旦ゲル化した後は積層成形時の圧力によ
つても全く流動しないものである。 First, the resin impregnated into the prepreg becomes fluid due to heating in the early stage of lamination molding, flows into the spaces between the wiring copper foils of the inner layer wiring board, fills the gaps, gels, and then completely hardens. Once gelled, it does not flow at all even under pressure during lamination molding.
樹脂がゲル化するまでの間は、内層配線板の配
線網上のプリプレグ中の樹脂が流れだして導体間
〓を埋めることとなり、この過程に於けるプレス
圧力は主に配線網上のプリプレグ及び銅箔に負荷
されることとなる。又、ゲル化し、硬化する過程
において樹脂は硬化収縮を起こすものであり、こ
の結果、内層配線板の配線網上のプリプレグ中の
ゲル化した樹脂は、導体間〓にあるプリプレグ中
の樹脂に比較して少ないものであるので硬化収縮
量が少なく、同様にプレス圧力は主に配線網上の
プリプレグ及び銅箔に負荷されることとなる。 Until the resin gels, the resin in the prepreg on the wiring network of the inner layer wiring board flows out and fills the gaps between the conductors, and the pressing pressure in this process is mainly applied to the prepreg on the wiring network and The load will be applied to the copper foil. In addition, during the process of gelling and curing, the resin undergoes curing shrinkage, and as a result, the gelled resin in the prepreg on the wiring network of the inner layer wiring board is smaller than the resin in the prepreg between the conductors. Since the amount of curing shrinkage is small, the press pressure is also applied mainly to the prepreg and copper foil on the wiring network.
この結果、多層板の外層銅箔中の内層配線板の
配線網の上にあたる部分は平均のプレス圧力より
も大きな圧力が負荷され、配線網間はより小さな
圧力が負荷されることとなり、この圧力差により
銅箔の表面の状態は、内層配線板の配線網の上に
あたる部分と配線網間とは異なつたものとなる。
また、上記であるので、内層配線板の配線網部上
の外層銅箔に比較してその間〓上の外層銅箔は凹
みぎみとなる。 As a result, a greater pressure than the average pressing pressure is applied to the part of the outer layer copper foil of the multilayer board that is above the wiring network of the inner layer wiring board, and a smaller pressure is applied between the wiring networks. Due to the difference, the surface condition of the copper foil is different between the portion of the inner layer wiring board above the wiring network and the area between the wiring networks.
Further, because of the above, the outer layer copper foil on the wiring network portion of the inner layer wiring board has a concave dent compared to the outer layer copper foil on the wiring network portion of the inner layer wiring board.
従つて、銅箔表面状態の差と微量の凹凸度の差
とが内層配線パターンの「浮きだし」として認識
されるようになると推定されるものであり、中間
層のプリプレグの量が少ない場合の方が、浮きだ
しが顕著となるのは、プリプレグが少ないために
プリプレグより流れ出す樹脂量は多くなり配線導
体上とその間〓との差は大きくなり、従つてプレ
ス圧力の差も相対的に大きくなり、かつ内層配線
板の配線導体上の銅箔に負荷されるプレス圧力も
より直接的となるので内層配線パターン部とその
間〓との境界面よりも明瞭となり、更に間〓の凹
みもやや大きくなることに基づくものと推定され
る。 Therefore, it is presumed that the difference in the surface condition of the copper foil and the slight difference in the degree of unevenness will be recognized as the "embossment" of the inner layer wiring pattern. However, the reason why the lifting becomes more noticeable is because there is less prepreg, so the amount of resin that flows out from the prepreg increases, and the difference between the top of the wiring conductor and the area between them becomes large, and therefore the difference in pressing pressure becomes relatively large. , and the press pressure applied to the copper foil on the wiring conductor of the inner layer wiring board is more direct, so the boundary between the inner layer wiring pattern part and the space between them becomes clearer, and the dent between the inner layer wiring pattern part and the space between them becomes slightly larger. It is presumed that this is based on the following.
尚、もし上記であるとすれば、内層配線部分の
上は盛り上がり、その間〓は凹みとなるはずであ
り測定等により定量化可能と思われるかも知れな
いがこれを凹凸合計による測定により定量化する
ことは成功していない。この理由は、外層銅箔表
面は、上記の内層配線パターンの浮きだしの他
に、プリプレグの補強基材であるガラス織布の織
り目(通常は平織のガラス織布)に基づく凹凸
(3〜4μm程度、明白に目視認識可能)があり、
更に上記の理由による凹凸度の差が存在している
としてもその凹凸は後記した穴部に於ける凹み量
の計算の同様の計算をした場合、精々1μm以下
であり、かつ極めて滑らかな変化であるものと予
測されるものであり、この結果凹凸度計による測
定では、定量化することはできないものと考えら
れる。 If the above is true, the top of the inner layer wiring should be raised, and the area between should be a depression, and although it may seem possible to quantify this by measurement, etc., this can be quantified by measuring the sum of the unevenness. That has not been successful. The reason for this is that in addition to the embossment of the inner layer wiring pattern described above, the surface of the outer copper foil has irregularities (3 to 4 μm degree, clearly visible to the naked eye),
Furthermore, even if there is a difference in the degree of unevenness due to the above-mentioned reasons, when a similar calculation is made to calculate the amount of depression in the hole described later, the unevenness is at most 1 μm or less, and the change is extremely smooth. As a result, it is thought that it cannot be quantified by measurement using an unevenness meter.
次に、本発明の基準穴ガイドマーク部が浮きだ
し或いは凹みとして極めて容易に認識される理由
は、上記の場合と同様でありこれが強調される結
果と推定されるものである。 Next, the reason why the reference hole guide mark portion of the present invention is extremely easily recognized as an embossed or recessed portion is similar to the above case, and is presumed to be a result of this being emphasized.
すなわち、基準穴ガイドマーク部に形成した穴
は、内層配線板の配線導体とその間〓との差に比
較して極めて巨大な差(通常、前者は70μm以
下、後者は1600−70=1530μm)である。この結
果、ゲル化までのプレス圧力は基準穴ガイドマー
ク内に形成した穴周辺上の外層銅箔と穴上の外層
銅箔とでは極端にことなつたものとなる。また、
ゲル化後の硬化収縮、熱膨張率の差も同様に大き
な差となる。ここに、樹脂の硬化収縮(線収縮
率)を0.6%、比重を1.2、ガラス布基材の比重
2.5、樹脂とガラス布基材の熱膨張率(線膨張率)
の差を△=50×10-6cm/cm/℃と仮定し、穴内も
樹脂で完全に充填されたものとして実施例1の
1.6mm厚のシールド板については体積効果はない
ものとして計算すると、
硬化収縮に基づく差;0.0064mm.
●穴周囲部分;
(1.6−0.74−0.07)×(40/1.2)/(60/2.5
+40/1.2)×(0.6/100)=0.00275
●穴 部 分;
(1.6−0.07)×(0.6/100)=0.00918
熱膨張率差による差;0.0052mm.
●穴周囲部分;
(1.6−0.21)×(40/1.2)/60/2.5+40/1.2)×
△×(170−25)=117△
●穴 部 分;
(1.6−0.07)×△×(170−25)=221.8△
∴(221.8−117)×△=5.24×10-3mm
上記より、穴部分上の銅箔は穴周囲に比較して
5.8μm凹むこととなる。 In other words, the hole formed in the reference hole guide mark part has an extremely large difference (usually 70 μm or less for the former and 1600-70 = 1530 μm for the latter) compared to the difference between the wiring conductor on the inner layer wiring board and the gap between them. be. As a result, the pressing pressure required to gel the outer layer copper foil around the hole formed in the reference hole guide mark is extremely different from that of the outer layer copper foil above the hole. Also,
Differences in curing shrinkage and thermal expansion coefficient after gelation also result in large differences. Here, the curing shrinkage (linear shrinkage rate) of the resin is 0.6%, the specific gravity is 1.2, and the specific gravity of the glass cloth base material.
2.5, Thermal expansion coefficient (linear expansion coefficient) of resin and glass cloth base material
Assuming that the difference in is △=50×10 -6 cm/cm/℃, and assuming that the hole is also completely filled with resin,
For a 1.6mm thick shield plate, assuming no volume effect, the difference due to curing shrinkage is 0.0064mm. ●Around the hole; (1.6−0.74−0.07)×(40/1.2)/(60/2.5
+40/1.2)×(0.6/100)=0.00275 ●Hole part; (1.6−0.07)×(0.6/100)=0.00918 Difference due to difference in thermal expansion coefficient; 0.0052mm. ●Around the hole; (1.6−0.21)×(40/1.2)/60/2.5+40/1.2)×
△×(170−25)=117△ ●Hole part; (1.6−0.07)×△×(170−25)=221.8△ ∴(221.8−117)×△=5.24×10 -3 mm From the above, hole The copper foil on the part is smaller than the area around the hole.
This results in a depression of 5.8 μm.
従つて、本発明の場合には、穴部分の上の銅箔
は殆どプレス圧力を受けないものであり、これに
対して穴周囲はプレス圧力を受けたものとなる。
この結果、銅箔表面状態は穴部分上とその周囲と
では大きく異なつたものとなり、更に上記の計算
からも明らかなように穴部分は約6μm凹むもの
であり、通常の内層配線パターンの浮きだしに比
較して巨大な差が生じることとなり、容易に目視
により観察可能なものとなるものと推定されるも
のである。 Therefore, in the case of the present invention, the copper foil above the hole portion is hardly subjected to press pressure, whereas the area around the hole is subjected to press pressure.
As a result, the surface condition of the copper foil is greatly different between the area above the hole and the area around it. Furthermore, as is clear from the calculations above, the hole is depressed by approximately 6 μm, and the normal inner layer wiring pattern is exposed. It is estimated that there will be a huge difference compared to the above, and that it will be easily observable visually.
上記のようにして、内層に形成した基準穴ガイ
ドマーク部分は、内面がへこんだ浮きだしたもの
となり、容易に目視により判別可能となる。従つ
て、座ぐりする場所の設定が一目瞭然に決められ
るため、作業ミスがなく、かつ作業時間が短くて
すむという利点がある。 As described above, the reference hole guide mark portion formed on the inner layer has a concave inner surface and is raised, and can be easily identified visually. Therefore, the location for spot boring can be determined at a glance, which has the advantage of eliminating work errors and shortening the work time.
以下、実施例等をあげて説明する。 The present invention will be described below with reference to Examples.
実施例 1
板厚0.6mm(70μm両面銅張板、銅箔を合わせて
0.74mm)の内層材に所望の配線網を写真焼付−エ
ツチング工程により作成した。このとき四隅にも
うけたガイドマークの穴径は4.0mmφであつた。Example 1 Board thickness 0.6mm (70μm double-sided copper clad board, copper foil combined)
A desired wiring network was created on the inner layer material (0.74 mm) by a photoprinting-etching process. At this time, the hole diameter of the guide marks made at the four corners was 4.0 mmφ.
このガイドマークの中央に2.8mmφの穴をあけ
たあと作成した銅箔配線に公知の接着用表面処理
の一種である黒色酸化被膜処理(次亜鉛素酸ソー
ダ及び水酸化ナトリウムを主成分とする水溶液で
95℃、2分間処理する方法)をし、その後、その
両側に0.1mm厚さのガラス織布エポキシ樹脂含浸
プリプレグ(樹脂量40wt%)を各5枚、35μm厚
さの銅箔を各1枚置き160℃〜170℃、40Kg/cm2の
温度と圧力で60分間プレスした。(なお、上記に
おいては、穴部分の容積は穴と同径の上下プリプ
レグの樹脂量より大きいものである。)
プレスから厚み1.6mmの両面未処理銅箔の多層
板(シールド板)を取り出し、観察したところ、
内層配線板の配線パターンの浮きだしなどは極め
て小さいものであつたが、四隅に設けたガイドマ
ーク部分はへこみとして明白に判別できるもので
あつた。 After drilling a 2.8 mm diameter hole in the center of this guide mark, the copper foil wiring created was treated with a black oxide coating, which is a type of surface treatment for adhesives (an aqueous solution containing sodium hypozinc oxide and sodium hydroxide as main components). in
After that, 5 sheets each of 0.1 mm thick glass woven epoxy resin-impregnated prepreg (resin amount 40 wt%) and 1 sheet each of 35 μm thick copper foil were applied on both sides. The material was placed at 160°C to 170°C and pressed at a temperature and pressure of 40Kg/cm 2 for 60 minutes. (In the above, the volume of the hole is larger than the resin amount of the upper and lower prepregs with the same diameter as the hole.) Take out a 1.6 mm thick double-sided untreated copper foil multilayer board (shield board) from the press, When I observed it,
Although the embossment of the wiring pattern on the inner layer wiring board was extremely small, the guide marks provided at the four corners were clearly distinguishable as dents.
このへこみにより座ぐり位置を決め、座ぐり用
ドリルで内層配線板のガイドマークの座ぐり(露
出)をし、座ぐり出ししたガイドマークに基づい
て、その中央に投影機付ドリルマシンで、3.175
mmφの穴をあけた。 Determine the counterbore position using this indentation, counterbore (expose) the guide mark on the inner layer wiring board with a counterbore drill, and then use a drill machine with a projector to place the 3.175mm in the center of the guide mark based on the counterbore guide mark.
A hole of mmφ was drilled.
上記の座ぐり位置決め、座ぐり、穴あけ加工に
要した時間は、3分/枚(4ケ所/枚)であり、
比較例1の半分以下であつた。 The time required for the above counterbore positioning, counterbore, and hole drilling processing was 3 minutes/piece (4 places/piece),
It was less than half of Comparative Example 1.
この穴を用いて、写真焼付、エツチングにより
外層の配線網を形成し、多層印刷配線板を得た。 Using these holes, an outer layer wiring network was formed by photoprinting and etching to obtain a multilayer printed wiring board.
比較例 1
実施例1において、内層配線板のガイドマーク
中央に穴をあけることをしない他は同様にして多
層シールド板を製造した。Comparative Example 1 A multilayer shield board was manufactured in the same manner as in Example 1, except that a hole was not made in the center of the guide mark of the inner layer wiring board.
プレスから取り出したこの多層シールド板の外
層表面には、内層配線板の配線パターンの極めて
小さい浮きだしがあり、大雑把の判別可能であつ
た。 On the surface of the outer layer of this multilayer shield plate taken out from the press, there was a very small embossment of the wiring pattern of the inner layer wiring board, and it was possible to roughly identify it.
この配線パターンの浮きだしにより大体の座ぐ
り位置を決め、座ぐり用ドリルで内層配線板のガ
イドマークの座ぐり(露出)をし、座ぐり出しし
たガイドマークに基づいて、その中央に投影機付
ドリルマシンで、3.175mmφの穴をあけた。 Determine the approximate counterbore position by embossing this wiring pattern, counterbore (expose) the guide mark on the inner layer wiring board with a counterbore drill, and place the projector in the center based on the counterbore guide mark. I drilled a 3.175mmφ hole with a drill machine.
上記の座ぐり位置決め、座ぐり、穴あけ加工に
要した時間は、8分/枚(4ケ所/枚)であつ
た。 The time required for the above-mentioned counterbore positioning, counterbore, and hole-drilling processing was 8 minutes/sheet (4 locations/sheet).
Claims (1)
外層用のプリプレグ及び銅箔を重ね多層化成形し
た後、該ガイドマークに基準穴を形成し、該基準
穴に基づいて外層の配線網形成を行う外層印刷配
線板の製造法において、内層配線板として該ガイ
ドマークの中心部に基準穴径よりも小さな穴を開
けた内層配線板を用いて多層化成形して得られた
多層板の該ガイドマーク部に形成されたへこみ部
分或いは該ガイドマークの浮きだし部分を座ぐり
出し、基準穴をあけた後、該基準穴に基づいて外
層の配線形成を行うことを特徴とする多層印刷配
線板の製造法。1. On the inner layer wiring board with reference hole guide marks,
In the method for manufacturing an outer layer printed wiring board, in which prepreg and copper foil for the outer layer are stacked and multi-layer molded, reference holes are formed in the guide marks, and a wiring network for the outer layer is formed based on the reference holes. A recessed portion formed in the guide mark portion of a multilayer board obtained by multilayer molding using an inner layer wiring board with a hole smaller than the reference hole diameter in the center of the guide mark, or a recessed portion of the guide mark. A method for manufacturing a multilayer printed wiring board, which comprises countersinking a raised portion, drilling a reference hole, and then forming wiring in an outer layer based on the reference hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2451280A JPS56124297A (en) | 1980-02-28 | 1980-02-28 | Method of manufacturing multilayer printed circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2451280A JPS56124297A (en) | 1980-02-28 | 1980-02-28 | Method of manufacturing multilayer printed circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS56124297A JPS56124297A (en) | 1981-09-29 |
| JPH0152919B2 true JPH0152919B2 (en) | 1989-11-10 |
Family
ID=12140218
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2451280A Granted JPS56124297A (en) | 1980-02-28 | 1980-02-28 | Method of manufacturing multilayer printed circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS56124297A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5982796A (en) * | 1982-11-02 | 1984-05-12 | 松下電工株式会社 | Method of producing multilayer printed circuit board |
| JPS61225893A (en) * | 1985-03-29 | 1986-10-07 | 日立化成工業株式会社 | Manufacture of multilayer printed interconnection board |
-
1980
- 1980-02-28 JP JP2451280A patent/JPS56124297A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS56124297A (en) | 1981-09-29 |
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