Deprecated: The each() function is deprecated. This message will be suppressed on further calls in /home/zhenxiangba/zhenxiangba.com/public_html/phproxy-improved-master/index.php on line 456
JPH0154883B2 - - Google Patents
[go: Go Back, main page]

JPH0154883B2 - - Google Patents

Info

Publication number
JPH0154883B2
JPH0154883B2 JP8981280A JP8981280A JPH0154883B2 JP H0154883 B2 JPH0154883 B2 JP H0154883B2 JP 8981280 A JP8981280 A JP 8981280A JP 8981280 A JP8981280 A JP 8981280A JP H0154883 B2 JPH0154883 B2 JP H0154883B2
Authority
JP
Japan
Prior art keywords
film
electrode
thickness
substrate
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP8981280A
Other languages
Japanese (ja)
Other versions
JPS5715514A (en
Inventor
Kyoshi Asakawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP8981280A priority Critical patent/JPS5715514A/en
Publication of JPS5715514A publication Critical patent/JPS5715514A/en
Publication of JPH0154883B2 publication Critical patent/JPH0154883B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/08Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves

Landscapes

  • Physics & Mathematics (AREA)
  • Acoustics & Sound (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)

Description

【発明の詳細な説明】 本発明は、弾性表面波(以後単に表面波と称
す)すだれ状電極の製造方法に関するものであ
る。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a surface acoustic wave (hereinafter simply referred to as surface wave) interdigital electrode.

表面波すだれ状電極は、圧電基板表面に櫛形電
極を互いに交叉させて成るものであり、効率良く
表面波を送・受信できる変換器としてよく知られ
ている。これを利用した表面波素子は、メガヘル
ツ(MHz)帯からギガヘルツ(GHz)帯の広汎な
周波数領域において、フイルタ、遅延線をはじ
め、各種信号処理を行う優れた性能の電気通信回
路素子としてよく知られている。
A surface wave interdigital electrode is made by intersecting comb-shaped electrodes on the surface of a piezoelectric substrate, and is well known as a transducer that can efficiently transmit and receive surface waves. Surface wave devices using this technology are well known as telecommunication circuit devices with excellent performance that perform various signal processing functions, including filters and delay lines, in a wide frequency range from megahertz (MHz) to gigahertz (GHz) bands. It is being

すだれ状電極は、通常、基板表面に電極材料を
蒸着した後、フオトエツチング技術を用いて所望
の形状に加工して得られるものである。かかるす
だれ状電極の微細構造はしばしば、平担な基板表
面に電極膜厚に等しい高さの段差を形成してい
る。この様な段差を有するすだれ状電極部を表面
波が伝搬するとき、一般に好ましくない現象が起
こる。その1つは、段差により表面波が不要に反
射される事であり、他の1つは段差により表面波
が、不要のバルク波に変換される事である。前者
は表面波のエコーを誘起して、主信号との干渉を
起こし、表面波素子の応答にしばしば不要のリツ
プルをもたらし、好ましくない。又後者は、表面
波の伝搬損失の要因ともなり、同じく好ましくな
い。特にこれらは、表面波素子の高周波化が進む
につれて、深刻な問題となる。この為、従来、す
だれ状電極を基板表面に埋め込み、表面波伝搬面
の段差を解消する構造が知られている。
The interdigital electrode is usually obtained by depositing an electrode material on the surface of a substrate and then processing it into a desired shape using photoetching technology. The fine structure of such interdigital electrodes often forms a step with a height equal to the electrode film thickness on a flat substrate surface. When surface waves propagate through interdigital electrodes having such steps, undesirable phenomena generally occur. One of these is that the surface waves are reflected unnecessarily by the difference in level, and the other is that the surface wave is converted into an unnecessary bulk wave by the difference in level. The former is undesirable because it induces surface wave echoes that interfere with the main signal, often resulting in unnecessary ripples in the response of the surface wave element. Moreover, the latter is also a cause of surface wave propagation loss, which is also undesirable. In particular, these problems become serious as the frequency of surface wave elements becomes higher. For this reason, a structure is conventionally known in which interdigital electrodes are embedded in the substrate surface to eliminate the level difference on the surface wave propagation surface.

この様な埋め込み型すだれ状電極の製造方法と
しては、以下のものが良く知られている。その1
つは予め基板表面にフオトレジストのパターンを
形成し、これをマスクとして、イオンビームエツ
チング技術を用いて、すだれ状電極と同一形状の
溝を基板表面に形成する。しかる後、電極材料膜
を蒸着により付着して前記溝部を前記電極材料で
埋める。最後に前記フオトレジストパターン上の
不要電極をリフトオフの手法を用いて、前記フオ
トレジストマスクパターンと共に除去する。この
方法の欠点は、前記リフトオフの工程において、
前記フオトレジストパターン上の不要電極を、前
記溝部に埋めこんだ電極から切り離す事の困難さ
にある。この為、この製造方法は、一般的に実用
性に欠けるという欠点がある。
The following methods are well known as methods for manufacturing such embedded interdigital electrodes. Part 1
One is to form a photoresist pattern on the substrate surface in advance, and using this as a mask, use ion beam etching technology to form grooves in the same shape as the interdigital electrodes on the substrate surface. Thereafter, an electrode material film is deposited by vapor deposition to fill the groove with the electrode material. Finally, unnecessary electrodes on the photoresist pattern are removed together with the photoresist mask pattern using a lift-off technique. The disadvantage of this method is that in the lift-off step,
The problem lies in the difficulty of separating unnecessary electrodes on the photoresist pattern from the electrodes buried in the grooves. For this reason, this manufacturing method has the drawback of generally lacking in practicality.

他の1つは、第1図に示す如く、段差を有する
電極で狭まれた間隙溝部を他の絶縁物で埋め、基
板表面を平担化する方法である。即ち同図aにお
いて、まず基板表面11に、すだれ状電極12を
通常のフオトエツチングと化学エツチングを用い
て形成する。次に全面に絶縁膜13を、真空蒸着
又はスパツタリングにより付着する。この時、絶
縁膜13の表面には、電極12に起因する段差が
そのまゝ転写されている。この後、回転塗布によ
り、フオトレジスト膜14を塗布する。この状態
では、塗布前の前記段差が若干解消されている。
ここで前記レジスト膜14の斜め上方からイオン
ビームエツチングにより、基板全面をエツチング
する。この時イオンビーム15と、膜14のなす
角θを適当に選ぶことにより、エツチングの開始
時に多少の段差はあつても、イオンビームエツチ
ングが終了した状態、即ち電極12が露呈した状
態では表面の段差は解消されている。即ち、第1
図bの如く基板11の表面上にある電極12の間
隙部には絶縁膜16が埋めこまれて表面の段差は
解消されている。かかる方法では、各々の膜の付
着力は一般に強固にせしむる事が可能であり又表
面の平担さも良好である為、集積回路や磁気バブ
ル素子における多層配線には、実用的であるとい
える。しかし、この方法を表面波素子の電極部平
担化に適用すると重要な欠点が発生する。即ち、
前記の電極間を埋める絶縁膜は、一般に非晶質も
しくは多結晶体である為、表面波の伝搬損失増大
を招く。表面波の伝搬損失は非晶質又は多結晶体
よりは、単結晶体の方が遥かに小さい事は良く知
られている。従つてしばしば実用に供される単結
晶基板を用いた表面波素子においては、電極間に
絶縁物を埋めた平面化構造よりは、基板に電極を
埋めこんだ平面化構造の方が上記の理由により優
れていると言える。
Another method, as shown in FIG. 1, is to fill the gap between the stepped electrodes with another insulator to flatten the surface of the substrate. That is, in FIG. 1A, first, an interdigital electrode 12 is formed on the substrate surface 11 using ordinary photo etching and chemical etching. Next, an insulating film 13 is deposited on the entire surface by vacuum deposition or sputtering. At this time, the step caused by the electrode 12 is directly transferred onto the surface of the insulating film 13. Thereafter, a photoresist film 14 is applied by spin coating. In this state, the level difference before application has been slightly eliminated.
Here, the entire surface of the substrate is etched by ion beam etching from diagonally above the resist film 14. At this time, by appropriately selecting the angle θ formed by the ion beam 15 and the film 14, even if there is a slight step at the beginning of etching, the surface will be flat when the ion beam etching is completed, that is, when the electrode 12 is exposed. The gap has been eliminated. That is, the first
As shown in FIG. 2B, an insulating film 16 is embedded in the gap between the electrodes 12 on the surface of the substrate 11, eliminating the level difference on the surface. In this method, it is generally possible to strengthen the adhesion of each film, and the surface is also good, so it can be said to be practical for multilayer wiring in integrated circuits and magnetic bubble devices. . However, when this method is applied to planarizing the electrode portion of a surface wave device, an important drawback occurs. That is,
The insulating film that fills the space between the electrodes is generally amorphous or polycrystalline, which increases the propagation loss of surface waves. It is well known that the propagation loss of surface waves is much smaller in single crystal materials than in amorphous or polycrystal materials. Therefore, in surface wave devices using single-crystal substrates that are often put into practical use, a planar structure in which electrodes are buried in the substrate is better than a planar structure in which an insulator is buried between the electrodes for the reasons mentioned above. It can be said that it is superior.

以上に述べた従来例の欠点を要約すると、基板
に電極を埋めこむ方法ではリフトオフ法を用いる
為、信頼性、歩留りに欠点があり、又、電極間に
絶縁物を埋めこむ方法では、表面波の伝搬損失を
増大せしむるという欠点があつた。
To summarize the shortcomings of the conventional examples mentioned above, the method of burying electrodes in the substrate uses a lift-off method, which has drawbacks in reliability and yield, and the method of burying an insulator between the electrodes has problems with surface waves. The disadvantage is that it increases the propagation loss.

本発明の目的は、従来の欠点を除去し、実用性
に富む新しい、すだれ状電極埋め込み方法を提供
する事にある。
An object of the present invention is to provide a new method for embedding interdigital electrodes that is highly practical and eliminates the drawbacks of the conventional method.

所望のすだれ状電極パターンとなる溝を備えた
凹凸構造を形成し、次に電極材料膜を凹凸全面に
一様に蒸着した後、凹凸構造を有する電極材料膜
上に、エツチング速度が前記電極材料のそれより
も小さな材料を塗布し、前記凸部の電極膜の厚み
をTe、塗布膜の厚みをTa、前記凹部の塗布膜の
厚みをTbとした時、 Ta+Te>Tb>Ta なる関係を満たす様に各膜厚を制御した構造を形
成し、しかる後に、表面法線方向に対して所定の
角度だけ傾いた方向から基板全面に、イオンビー
ムを照射して、前記被膜及び不要電極膜をエツチ
ングするにより、埋め込みすだれ状電極を形成す
ることを特徴とするすだれ状電極の製造方法が得
られる。
After forming a concavo-convex structure with grooves forming a desired interdigital electrode pattern, and then uniformly depositing an electrode material film over the entire surface of the concavo-convex structure, etching is performed on the electrode material film having the concavo-convex structure at an etching rate of the electrode material. When a material smaller than that of is applied, and the thickness of the electrode film on the convex part is Te, the thickness of the coating film is Ta, and the thickness of the coating film on the concave part is Tb, the relationship Ta + Te > Tb > Ta is satisfied. After that, the entire surface of the substrate is irradiated with an ion beam from a direction inclined at a predetermined angle with respect to the surface normal direction to etch away the film and unnecessary electrode film. As a result, a method for manufacturing an interdigital electrode characterized by forming an embedded interdigital electrode is obtained.

次に図面を用いて、本発明の詳細を説明する。 Next, details of the present invention will be explained using the drawings.

第2図は、本発明の一実施例における工程概略
図である。同図aにおいて、基板21の表面に、
フオトレジストパターン22を形成し、次にこれ
をマスクとして、イオンビームエツチングにより
溝23を形成する。ここにレジストパターン22
は、すだれ状電極の反転パターンである。従つて
溝23が、所望のすだれ状電極に等しい形状を有
している。次に同図bに示す如く、前図のレジス
ト膜22を除去した後、凹凸基板の全面に一様な
厚みのアルミニウム(Al)の電極材料膜24を
蒸着により付着する。この時のAlの膜厚をTeと
する。次に回転塗布法により、再度フオトレジス
ト膜25を付着する。この時、フオトレジスト膜
の、前記凸部および凹部での厚みをそれぞれTa、
Tbとする。ここに、各膜厚は Ta+Te>Tb>Ta である様に制御されている。この後基板表面に対
して約45゜の斜め方向からイオンビーム26を照
射し、前記レジスト膜25及び不要電極部28を
エツチングする。このとき所定の時間でエツチン
グを終了した後、同図cに示す様に、基板21の
表面に電極27が埋めこまれ、表面の段差が解消
された構造のものが得られる。
FIG. 2 is a process schematic diagram in one embodiment of the present invention. In the same figure a, on the surface of the substrate 21,
A photoresist pattern 22 is formed, and then, using this as a mask, grooves 23 are formed by ion beam etching. Resist pattern 22 here
is an inverted pattern of interdigital electrodes. The groove 23 thus has a shape equivalent to the desired interdigital electrode. Next, as shown in Figure b, after removing the resist film 22 shown in the previous figure, an electrode material film 24 of aluminum (Al) having a uniform thickness is deposited on the entire surface of the uneven substrate by vapor deposition. Let the Al film thickness at this time be Te. Next, a photoresist film 25 is deposited again by a spin coating method. At this time, the thickness of the photoresist film at the convex portion and concave portion is Ta, respectively.
Let it be Tb. Here, each film thickness is controlled so that Ta+Te>Tb>Ta. Thereafter, the resist film 25 and unnecessary electrode portion 28 are etched by irradiating the substrate surface with an ion beam 26 from an oblique direction of about 45 degrees. At this time, after the etching is completed for a predetermined time, the electrode 27 is embedded in the surface of the substrate 21, as shown in FIG.

この理由を、第2図bについて述べる。電極膜
24がAlであり、レジスト膜25がAZ−1350J
(商標:米国シプレー社)であるとき、レジスト
膜に比べて、電極膜の方がエツチング速度が大き
い。実測によれば、イオンビーム26と、基板法
線方向とのなす角θが0<θ<80゜であるとき、
レジスト膜に対する電極膜の相対エツチング速度
Rは1R2である。次に段差を有する電極膜
24の上に回転塗布法によりレジスト膜25を塗
布し、且つ、レジスト膜厚は溝底部の方が、凸部
よりも大きくなる様に制御する。この時、前記段
差は若干緩和されるが、依然として残る。この状
態で、エツチングを開始すると、初期の時点で
は、段差をはさむ、凹凸両部が同一膜であるため
前記段差は不変である。しかし、前記凸部に電極
膜が現われると、前述のエツチング速度の違いの
ため、凸部の方がエツチングが早く進行する。即
ち凸部でのレジストおよびAlの合計膜厚(Ta+
Te)と、凹部でのレジスト厚みTbには、前述の
様に Ta+Te>Tb となる様な関係があつても、イオンビームの入射
角θおよびエツチング時間を適当に選ぶと、凸部
の電極膜28を全てエツチングした時点で、前記
段差を解消する事が可能である。
The reason for this will be explained with reference to FIG. 2b. The electrode film 24 is Al, and the resist film 25 is AZ-1350J.
(Trademark: Shipley, Inc., USA), the etching rate of the electrode film is higher than that of the resist film. According to actual measurements, when the angle θ between the ion beam 26 and the normal direction of the substrate is 0<θ<80°,
The relative etching rate R of the electrode film to the resist film is 1R2. Next, a resist film 25 is applied onto the electrode film 24 having the steps by a spin coating method, and the resist film thickness is controlled so that the thickness of the resist film is larger at the bottom of the groove than at the convex part. At this time, the level difference is somewhat alleviated, but still remains. When etching is started in this state, the step remains unchanged at the initial stage because both the concave and convex portions sandwiching the step are the same film. However, when the electrode film appears on the convex portion, etching progresses faster on the convex portion due to the difference in etching speed mentioned above. In other words, the total film thickness of resist and Al (Ta +
Even if there is a relationship between Ta+Te>Tb as mentioned above between the resist thickness Tb at the concave part and the resist thickness Tb at the concave part, if the incident angle θ of the ion beam and the etching time are appropriately selected, the electrode film at the convex part can be removed. At the time when all 28 are etched, it is possible to eliminate the step.

上記所定のエツチング時間はレジスト膜25及
び電極膜28の厚みによつて決まるものである。
試みに、最終的に得られる、電極膜27の基板埋
め込み量が1000Åのとき前記溝部23の深さおよ
び電極膜24の厚みを約1000Åとして、レジスト
膜25の厚みを約2000Å〜5000Åの範囲で選ぶな
らば、上記エツチング時間を3分〜10分の所望の
値に選ぶことで本発明の目的である表面の平担化
が達成される。
The above-mentioned predetermined etching time is determined by the thickness of the resist film 25 and the electrode film 28.
As a trial, when the final amount of the electrode film 27 buried in the substrate is 1000 Å, the depth of the groove 23 and the thickness of the electrode film 24 are set to be about 1000 Å, and the thickness of the resist film 25 is set in the range of about 2000 Å to 5000 Å. If selected, by selecting the etching time to a desired value of 3 to 10 minutes, the object of the present invention, flattening the surface, can be achieved.

次に本発明の利点を従来例と比較して述べる。
前述の従来例のうち、第1のものは、第2図aの
状態で電極材料を蒸着した後、レジストパターン
22の上に付着した不要電極膜を、所謂リフトオ
フの技術によりレジストパターン22と共に除去
する方法であつた。しかし、この場合レジストパ
ターン22の側壁が急峻でないと、上記不要電極
膜の剥ぎ取りが困難である事は前述の通りであ
る。又かかる剥ぎ取り工程の再現性・信頼性を増
すためには、良く知られている様に前記レジスト
パターン22の側壁が逆台形である事が望まし
い。しかし、さりとて逆台形にすると、前記剥ぎ
取り工程の信頼性向上の代償として得られた埋め
込み電極の側壁と、基板溝部の側壁との間には、
間隙が生ずる。この様な間隙は表面波の伝搬にと
つて、反射や散乱の原因となり好ましくない。こ
れに対し、本発明の方法によれば、埋め込み電極
の側壁と基板溝部の側壁とは密に付着せしむる事
ができるので、上述の様な電極端部での間隙によ
る表面波の反射・散乱は起こらない。次に、本発
明と前述の第2の従来例とを比較する。本発明の
平担化手段は、電極間の溝部に絶縁物を埋め込む
方法ではなく、電極自身が基板に埋め込まれる方
法である。従つて前述の様に表面波伝搬損失の低
減化を考えると、本発明が従来例に勝る事は明白
である。従つて、本発明の利点を要約すると、本
発明は基板内部に電極を埋め込み、しかも、埋め
こまれた電極の端部に沿つて溝が発生しない様に
電極と基板を密に付着せしむる様な構造の電極平
担化の製造方法である為、表面波の反射・散乱・
減衰を低減化せしむるものであると言える。
Next, the advantages of the present invention will be described in comparison with the conventional example.
Among the conventional examples described above, the first one is to deposit an electrode material in the state shown in FIG. The method was to do so. However, in this case, as described above, unless the side walls of the resist pattern 22 are steep, it is difficult to strip off the unnecessary electrode film. In order to increase the reproducibility and reliability of the stripping process, it is desirable that the side walls of the resist pattern 22 have an inverted trapezoidal shape, as is well known. However, if the strip is made into an inverted trapezoid, there will be a gap between the side wall of the buried electrode obtained in exchange for improving the reliability of the stripping process and the side wall of the substrate groove.
A gap is created. Such a gap is undesirable for the propagation of surface waves because it causes reflection and scattering. On the other hand, according to the method of the present invention, the side walls of the embedded electrode and the side walls of the substrate groove can be closely attached, so that surface waves can be reflected by the gap at the end of the electrode as described above. No scattering occurs. Next, the present invention will be compared with the second conventional example described above. The flattening means of the present invention is not a method of burying an insulator in the groove between the electrodes, but a method of embedding the electrodes themselves in the substrate. Therefore, when considering the reduction of surface wave propagation loss as described above, it is clear that the present invention is superior to the conventional example. Therefore, to summarize the advantages of the present invention, the present invention embeds an electrode within a substrate, and also closely adheres the electrode and the substrate so that grooves do not occur along the edges of the embedded electrode. Since this is a manufacturing method for flattening electrodes with various structures, reflection, scattering, and
It can be said that this reduces attenuation.

尚、図面による本発明実施例の説明において、
第2図bにおける電極材料24の付着工程の前
に、同図aのレジスト膜22の除去を行つた。し
かしながらこの工程は、本発明の必須要件ではな
い。即ち、最終的に得る電極27の厚みを大きく
選ぶ場合には、同図aの溝23は深くイオンエツ
チングせねばならず、従つてレジスト膜22の膜
厚はイオンエツチングの耐性を考慮して厚く選ば
ねばならない。この様なときは溝23及び残存レ
ジスト膜22双方の寄与による段差が大きい為、
後工程での段差軽減を考慮して、レジスト膜22
は除去する事が好ましい。しかし、電極27の厚
み従つて溝23の深さを小さく選ぶときには、レ
ジスト膜22も薄くてすむ為、除去しないまゝ、
後工程を行つてもよい。この場合でも、最後の斜
めイオンエツチング工程で、当残存レジストは除
去されるのである。
In addition, in the description of the embodiments of the present invention using the drawings,
Before the step of attaching the electrode material 24 in FIG. 2b, the resist film 22 in FIG. 2a was removed. However, this step is not an essential requirement of the present invention. That is, if the final thickness of the electrode 27 is selected to be large, the groove 23 shown in FIG. I have to choose. In such a case, the difference in level caused by both the groove 23 and the remaining resist film 22 is large, so
In consideration of reducing the level difference in the subsequent process, the resist film 22
It is preferable to remove it. However, when the thickness of the electrode 27 and the depth of the groove 23 are selected to be small, the resist film 22 can also be made thinner, so it is not removed.
A post-process may be performed. Even in this case, the remaining resist is removed in the final oblique ion etching step.

又、上記本発明実施例において、第2図aの溝
23の形成には、イオンビームエツチング技術で
用いた。しかし本工程はイオンエツチング手段に
のみ拘束されるものではなく、反応性スパツタエ
ツチング、化学エツチングを含む他のエツチング
手段も許される事は言うまでもない。
Further, in the embodiment of the present invention described above, ion beam etching technology was used to form the groove 23 shown in FIG. 2a. However, it goes without saying that this process is not limited to the ion etching method, and other etching methods including reactive sputter etching and chemical etching are also permissible.

以上、本発明の詳細を説明したが、本発明の権
利は、前記実施例のみに留まらず、前述の特許請
求の範囲に示す全てのすだれ状電極製造方法に及
ぶものである。
Although the details of the present invention have been explained above, the rights of the present invention are not limited to the above-mentioned embodiments, but extend to all interdigital electrode manufacturing methods shown in the above-mentioned claims.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、従来例における工程概略図、第2図
は、本発明の一実施例における工程概略図であ
る。尚、図において、11,21は基板、12,
27はすだれ状電極、14,22,25はフオト
レジスト膜、16は絶縁膜である。
FIG. 1 is a schematic diagram of a process in a conventional example, and FIG. 2 is a schematic diagram of a process in an embodiment of the present invention. In the figure, 11 and 21 are the substrates, 12,
27 is an interdigital electrode, 14, 22, and 25 are photoresist films, and 16 is an insulating film.

Claims (1)

【特許請求の範囲】 1 圧電基板表面に、所望のすだれ状電極のパタ
ーンとなる溝を備えた凹凸構造を形成し、次に電
極材料膜を凹凸全面に一様に蒸着した後、凹凸構
造を有する電極材料膜上に、エツチング速度が前
記電極材料のそれよりも小さな材料を塗布し、前
記凸部の電極膜の厚みをTe、塗布膜の厚みを
Ta、前記凹部の塗布膜の厚みをTbとした時、 Ta+Te>Tb>Ta なる関係を満たす様に各膜圧を制御した構造を形
成し、しかる後に表面法線方向に対して所定の角
度だけ傾いた方向から基板全面にイオンビームを
照射して、前記被膜及び不要電極膜をエツチング
することにより、埋め込みすだれ状電極を形成す
ることを特徴とする弾性表面波すだれ状電極の製
造方法。
[Claims] 1. A concavo-convex structure with grooves forming a desired interdigital electrode pattern is formed on the surface of a piezoelectric substrate, and then an electrode material film is uniformly deposited over the concave-convex surface, and then the concavo-convex structure is formed. A material having an etching rate lower than that of the electrode material is coated on the electrode material film having an etched surface, and the thickness of the electrode film at the convex portion is Te, and the thickness of the coating film is
When Ta and the thickness of the coating film in the recess are Tb, a structure is formed in which the thickness of each film is controlled to satisfy the relationship Ta + Te > Tb > Ta, and then at a predetermined angle with respect to the surface normal direction. A method of manufacturing a surface acoustic wave interdigital electrode, characterized in that a buried interdigital electrode is formed by irradiating the entire surface of the substrate with an ion beam from an inclined direction and etching the coating and unnecessary electrode film.
JP8981280A 1980-07-01 1980-07-01 Manufacture for reed screen electrode for elastic surface wave Granted JPS5715514A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8981280A JPS5715514A (en) 1980-07-01 1980-07-01 Manufacture for reed screen electrode for elastic surface wave

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8981280A JPS5715514A (en) 1980-07-01 1980-07-01 Manufacture for reed screen electrode for elastic surface wave

Publications (2)

Publication Number Publication Date
JPS5715514A JPS5715514A (en) 1982-01-26
JPH0154883B2 true JPH0154883B2 (en) 1989-11-21

Family

ID=13981136

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8981280A Granted JPS5715514A (en) 1980-07-01 1980-07-01 Manufacture for reed screen electrode for elastic surface wave

Country Status (1)

Country Link
JP (1) JPS5715514A (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4577169A (en) * 1984-08-01 1986-03-18 At&T Bell Laboratories Small ripple surface acoustic wave filter with low insertion loss
JPH02149114A (en) * 1988-11-30 1990-06-07 Nippon Dempa Kogyo Co Ltd Surface acoustic wave device
JP2684214B2 (en) * 1989-04-28 1997-12-03 株式会社村田製作所 Surface wave device
WO1996004713A1 (en) * 1994-08-05 1996-02-15 Japan Energy Corporation Surface acoustic wave device and production method thereof
JP3308749B2 (en) * 1995-01-27 2002-07-29 日本電気株式会社 Method for manufacturing surface acoustic wave device, and surface acoustic wave device manufactured using the same

Also Published As

Publication number Publication date
JPS5715514A (en) 1982-01-26

Similar Documents

Publication Publication Date Title
CA2020411C (en) Surface acoustic wave device
US5401544A (en) Method for manufacturing a surface acoustic wave device
US20030111439A1 (en) Method of forming tapered electrodes for electronic devices
JP3174049B2 (en) Method for global planarization of semiconductor integrated circuit surface
GB1587796A (en) Surface wave device having reflecting means
US4853080A (en) Lift-off process for patterning shields in thin magnetic recording heads
JPH0154883B2 (en)
JPH0590865A (en) Central frequency adjusting method for acoustic surface wave filter
US4684841A (en) Saw devices including resistive films
JPH0551174B2 (en)
US5038068A (en) Thin film pattern and method of forming the same
CN114171374B (en) Methods for etching trapezoidal grooves and methods for forming metal lines on a substrate
JP3137659B2 (en) Magnetostatic wave device and method of manufacturing the same
EP0394480B1 (en) Structure of surface acoustic wave transducer having small electrode gaps and method of producing the same
JP2752119B2 (en) Method for forming electrode for semiconductor device
JPH0347603B2 (en)
JPS5893329A (en) Method for flattening insulating layer
JP3426127B2 (en) Frequency adjustment method for surface acoustic wave device
JPH066160A (en) Manufacture of surface acoustic wave element
US5344745A (en) Method for the manufacture of surface acoustic wave transducer
JPH09162670A (en) Surface acoustic wave device and pattern forming method thereof
JPH0351326B2 (en)
JPH06103819B2 (en) Method of manufacturing surface wave device
JPH0468607A (en) Manufacture of surface acoustic wave device
JPS5827655B2 (en) Manufacturing method of aperture diaphragm