JPH0155770B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a source follower circuit that can be used as a buffer circuit.

Prior Art and Problems Due to impedance problems, buffer circuits with an input signal to output signal ratio of approximately 1:1 are used. Conventionally, such a buffer circuit has an input terminal as shown in FIG.
A circuit is known in which an operational amplifier OPA constituting a positive phase amplifier is connected between IN and an output terminal OUT. However, the operational amplifier OPA has the drawbacks of relatively large power consumption and a large area occupied when integrated. Further, as shown in FIG. 2, a source follower circuit composed of n-channel MOS transistors Q1 and Q2 is also known. This source follower circuit has the advantage of consuming less power and occupying a smaller area than the circuit shown in FIG. However, it had drawbacks such as variations in the manufacturing process and large effects due to temperature fluctuations.

That is, the conventional source follower circuit shown in FIG. 2 consists of n-channel MOS transistors Q1 and Q.
2 is connected in series between the power supply and ground G to apply the power supply voltage _VDD , and the input terminal IN is connected to the gate of the MOS transistor Q2 that constitutes the driver.
A constant gate voltage VG is applied to the gate of the MOS transistor Q1 constituting the load, and the output terminal OUT is connected to the connection point between the MOS transistors Q1 and Q2.

For example, if the currents that flow through the gates of MOS transistors Q1 and Q2 when gate voltages VG ₁ and VG ₂ are respectively applied to them are I ₁ and I ₂ , then I ₁ = [β ₁ (VG ₁ −Vth) ² ] /2 ...(1) I ₂ = [β ₂ (VG ₂ −Vth) ² ]/2 ...(2) It is expressed as follows. Note that β ₁ and β ₂ are MOS transistors Q
1 and Q2, VG ₁ and VG ₂ are the gate voltages of the MOS transistors Q1 and Q2, and Vth is the threshold voltage.

If the input voltage applied to the input terminal IN is Vin and the output voltage is Vout, it is expressed as VG ₂ = Vin−Vout (3), so I ₂ = [β ₂ (Vin−Vout−Vth) ² ] /2 ...(4) becomes. Since the MOS transistors Q1 and Q2 constituting the source follower circuit are connected in series as shown in Figure 2, I ₁ = I ₂ and formula (2) can be
Substituting into equation (4), Vout=Vin−Vth−(√ _{1 2} )・(VG ₁ −Vth)
...(5) becomes.

In general, a source follower circuit needs to have a wide dynamic range, so that β ₁ <β ₂ , that is, the channel width of the MOS transistor Q2 as a driver is made larger than that of the MOS transistor Q1 as a load. Therefore, the equation (5) becomes Vout≒Vin−Vth (6), which depends on the threshold voltage Vth. This threshold voltage Vth changes due to variations in the impurity concentration and diffusion depth of the diffusion region during the manufacturing process, as well as temperature fluctuations during use, so even if the input voltage Vin is constant, the output voltage Vout will vary. There was a drawback that this occurred.

OBJECTS OF THE INVENTION It is an object of the present invention to provide a source follower circuit that is less affected by variations in manufacturing processes and temperature fluctuations.

Structure of the Invention The source follower circuit of the present invention comprises a p-channel source follower circuit consisting of first and second p-channel MOS transistors, each having the same channel width, and a third and fourth n-channel MOS transistor that constitutes a driver and a load. An n-channel source follower circuit consisting of channel MOS transistors is connected between the power supply and ground, and the gates and drains of the fifth, sixth, and seventh n-channel MOS transistors are connected, and the power supply and a voltage dividing circuit connected in series between the ground and the ground so that the divided voltage by the fifth n-channel MOS transistor and the divided voltage by the seventh n-channel MOS transistor are equal to each other; an input terminal is connected to the gate of a first p-channel MOS transistor of the p-channel source follower circuit, and an output of the p-channel source follower circuit is connected to a third n-channel MOS transistor of the n-channel source follower circuit. The p-channel source follower circuit and the n-channel source follower circuit are connected in cascade, and the divided voltage by the fifth n-channel MOS transistor of the voltage dividing circuit is connected to the fifth n-channel source follower circuit. connected so as to apply the divided voltage by the seventh n-channel MOS transistor of the voltage dividing circuit to the gate of the second p-channel MOS transistor of the p-channel source follower circuit, respectively. This allows the ratio of the input voltage to the output voltage to be approximately 1:1, and is not affected by the threshold voltage. Examples will be described in detail below.

Embodiment of the invention FIG. 3 is a circuit diagram of an embodiment of the invention, and Q
5 and Q6 are first and second p-channel MOS transistors, Q4 and Q3 are third and fourth n-channel MOS transistors, and Q7, Q8, and Q9 are fifth, sixth, and seventh transistors that constitute a voltage dividing circuit. n-channel
MOS transistors, Q5 and Q6 are p channel
MOS transistor, V _DD is the power supply voltage, G is the ground, IN is the input terminal, and OUT is the output terminal. n
n by channel MOS transistors Q3 and Q4
The p-channel source follower circuit is configured by p-channel MOS transistors Q5 and Q6, and the sizes of the MOS transistors constituting the driver and load of the n-channel and p-channel source follower circuits are made equal, and the p-channel MOS transistors Q5 and Q6 configure the p-channel source follower circuit. The input terminal IN is connected to the gate of the MOS transistor Q5 that constitutes the driver of the channel source follower circuit, and the output of the p channel source follower circuit is applied to the gate of the MOS transistor Q4 that constitutes the driver of the n channel source follower circuit. A p-channel source follower circuit and an n-channel source follower circuit are connected in cascade.

Also, the n-channel MOS transistors Q7 and Q9 are the same size, and the MOS transistors Q7 to Q9
By dividing the power supply voltage _VDD , the gate voltage of the n-channel MOS transistor Q3 and the p-channel
This applies the gate voltage of the MOS transistor Q6, and the characteristics change the same even with temperature fluctuations, so the gate-source voltage of the n-channel MOS transistor Q3 and the gate-source voltage of the p-channel MOS transistor Q6 are can be kept equal.

As mentioned above, configure the drivers and loads for the N-channel and P-channel source follower circuits.
By making the sizes of the MOS transistors the same, the current amplification factor β also becomes the same, and the n-channel
In the source follower circuit, assuming that the gate voltage of the MOS transistor Q3 is VG ₃ , the output voltage Vout is as follows from equation (5): Vout≈Vin−VG ₃ (7). That is, it is not affected by the threshold voltage Vth.

In addition, in the p-channel source follower circuit, the output voltage Vop is the MOS transistor Q.
If the gate voltage of 6 is VG ₆ , then Vop=Vin+VG ₆ ...(8). Therefore, the output voltage Vout is as follows: Vout = Vop - VG ₃ = Vin + VG ₆ - VG ₃ (9). Here, MOS transistors Q7 and Q9
If the sizes of are the same and VG ₆ = VG ₃ , (9)
The formula is Vout=Vin...(10). In other words, the ratio of input voltage to output voltage is 1:1.
It is possible to configure a buffer circuit with Also, the output voltage is not affected by the threshold voltage. Furthermore, the dynamic range is approximately the same as that of the conventional example.

Effects of the Invention As explained above, the present invention provides first and second p-channels having the same width.
A p-channel source follower circuit consisting of MOS transistors Q5 and Q6 and an n-channel source follower circuit consisting of third and fourth n-channel MOS transistors Q4 and Q3, each having the same channel width, are connected in cascade to form a p-channel source follower. The input terminal IN is connected to the gate of the first p-channel MOS transistor Q5 of the circuit, and the fifth n-channel MOS transistor of the voltage divider circuit consisting of the fifth, sixth, and seventh n-channel MOS transistors Q7, Q8, and Q9 is connected to the gate of the first p-channel MOS transistor Q5.
The drain-source voltage of the channel MOS transistor Q7 is set to the gate voltage VG ₃ of the fourth n-channel MOS transistor Q3 that constitutes the load of the n-channel source follower circuit, and
The drain-source voltage of the p-channel MOS transistor Q9 is applied as the gate voltage VG ₆ of the second p-channel MOS transistor Q6 that constitutes the load of the p-channel source follower circuit, and these gate voltages are applied to the voltage divider circuit. The configuration is such that VG ₃ = VG ₆ , and the output voltage Vout is not affected by the threshold voltage, so even if there are variations in the threshold voltage due to manufacturing process variations or temperature fluctuations. Also, the ratio between the input voltage Vin and the output voltage Vout can be maintained at 1:1. That is, it is possible to provide a source follower circuit that does not cause variations in output voltage. Furthermore, the dynamic range is approximately the same as that of the conventional example. Therefore, since it is a circuit that takes advantage of low power consumption and small occupied area, and has little variation in output voltage, it can be applied to various buffer circuits.

[Brief explanation of drawings]

Figures 1 and 2 are conventional buffer circuits;
The figure is a circuit diagram of an embodiment of the present invention. Q3 and Q4 are n-channel MOS transistors forming an n-channel source follower circuit, Q5,
Q6 is a p-channel MOS transistor forming a p-channel source follower circuit, Q7, Q8,
Q9 is an n-channel MOS transistor, IN is an input terminal, and OUT is an output terminal.

Claims (1)

[Scope of Claims] 1. A p-channel source follower circuit consisting of first and second p-channel MOS transistors Q5 and Q6, which constitute a driver and a load, and have equal channel widths, respectively, and a third and fourth n-channel MOS transistor.
An n-channel source follower circuit consisting of channel MOS transistors Q4 and Q3 is connected between the power supply and ground, and the gates and drains of the fifth, sixth, and seventh n-channel MOS transistors Q7, Q8, and Q9 are connected between the power supply and the ground. and the fifth n-channel is connected in series between the power supply and the ground.
A voltage dividing circuit is configured in which the divided voltage by the MOS transistor Q7 and the divided voltage by the seventh n-channel MOS transistor Q9 are equal, respectively, and the first p-channel MOS transistor Q5 of the p-channel source follower circuit The input terminal IN is connected to the gate of the p-channel source follower circuit, and the output of the p-channel source follower circuit is connected to the third n-channel MOS transistor Q of the n-channel source follower circuit.
the voltage divided by the fifth n-channel MOS transistor Q7 of the voltage divider circuit to the gate of the fourth n-channel MOS transistor Q3 of the n-channel source follower circuit, and A source follower circuit, characterized in that the voltage divided by the seventh n-channel MOS transistor Q9 is connected to the gates of the second p-channel MOS transistors Q6 of the p-channel source follower circuit, respectively.