JPH0156388B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention arranges omnidirectional antennas at equal intervals on the circumference, switches them sequentially, and detects the received signal based on the phase change of the received signal obtained by reception. This relates to a so-called stationary Doppler direction finder that determines the direction of arrival of radio waves.

[Conventional technology]

The basic configuration of a conventional direction finder of this type will be explained with reference to FIG.

1 is a group of antennas, which are omnidirectional antennas with the same characteristics arranged at equal intervals on the circumference as shown in Figure 3.
An antenna A ₀ having similar characteristics is provided at the center of A ₁ to An, and its output is connected to the RF input terminal of the receiver 31.
2 is an antenna switcher which sequentially switches and scans the outputs of the antennas A ₁ to An and connects the output to the RF input terminal of the receiver 32 . 3 is a two-channel receiver composed of a main receiver 31 and a slave receiver 32 with a common local oscillator, and by adjusting the frequency of the main receiver 31, the frequency of the slave receiver 32 can be adjusted at the same time. It is now possible to receive the same radio waves at the same time. When the antennas A ₁ to An are sequentially switched and scanned to receive radio waves, the received signal is as shown in Figure 6 (a).
It is already known in Japanese Patent Publication No. 56-35828 that phase modulation is applied depending on the antenna arrangement as shown in (showing an example of eight antennas).

Amplified by 2 channel receiver 3
The IF output is applied to the signal processing circuit 4 where it is amplified and detected to obtain a predetermined azimuth signal. The signal processing circuit 4 separately generates a reference signal and applies this to the antenna switching signal generating circuit 6 to generate switching scanning signals for each antenna. The above-mentioned azimuth signal is subjected to average processing by an adding circuit within the signal processing circuit. This output is the indicator 5
The 3-digit or 4-digit digital azimuth measurement value added to the azimuth is displayed on the numerical display, and at the same time, it is displayed on the cathode ray tube as a single image or a unidirectional bright line image indicating the azimuth.

In such radio direction finders, the phase change component is extracted using a detector such as a disk drive or a PLL (phase locked loop), and the phase difference with the antenna scanning reference signal is measured to determine the direction of the incoming radio wave. , the extracted azimuth component generally contains noise and has an extremely poor S/N ratio, so the above-mentioned phase measurement cannot be directly performed.

For this reason, the effective component in the azimuth component is extracted using a waveform generator or a separately provided phase stabilization circuit, but since this azimuth signal component has a low frequency, the response speed becomes extremely slow. Furthermore, if there is a momentary interruption or mixed signal in the azimuth signal component, the transient phenomenon continues for a long time, causing problems in azimuth measurement, such as the azimuth becoming unstable.

For this reason, the data obtained by detecting the above phase difference is stored and accumulated in memory, and the accumulated data is correlated with the trigonometric function by taking advantage of the fact that the azimuth signal changes like a trigonometric function. Alternatively, the above-mentioned signal processing circuit provides a means for improving the accuracy of the signal for direction display by performing statistical processing to detect defective data and importing data judged to be good in place of the defective data. A device provided in a portion corresponding to No. 4 is disclosed in Japanese Patent Application Laid-Open No. 56-137169.

In addition, in order to prevent the above data from becoming defective due to transient defective changes in the received signal that occur at each switching point in the switching scan, the above switching is performed for a very short period of time before and after each switching point.
A device provided with a means for stopping the operation of the PLL is disclosed in Japanese Patent Laid-Open No. 124067/1983.

[Problem to be solved by the invention]

As described above, data is accumulated in the signal processing circuit 4, and the accumulated data is subjected to correlation processing or statistical processing to detect defective data, or to replace defective data with data judged to be good. With this method, a considerable amount of calculation time is required for processing to detect bad data and determining good data to replace it, making it impossible to obtain direction measurement results early. In addition, if bad data continues for a long time, the memory becomes full. Due to bad data, the balance has become full,
There are disadvantages such as the fact that the desired arithmetic processing becomes impossible.

Therefore, in order to prevent defective data from being included in the data stored in the memory, it is conceivable that the above-mentioned PLL operation stopping means may be configured to stop only during the period in which the defective data occurs. With this means, there arises a disadvantage that data during that period cannot be obtained and the intended direction measurement cannot be performed.

Therefore, there is a problem in that it is desired to provide something that solves these inconveniences.

[Means to solve the problem]

The present invention provides, in such a radio direction finder, a means for generating a signal having positive and negative polarities alternately every 1/2 period of the switching scan period of the antenna as an internal signal, and a phase difference detection signal. means for obtaining a signal obtained by multiplying the signal obtained by alternating positive and negative polarities with the above-mentioned internal signal as a multiplication polarity signal; means for transferring and storing the stored contents of the detected data stored in the first memory portion in a second memory portion of the memory; and each polarity portion of the detected data stored in the second memory portion. Means for variably controlling the phase of the above-mentioned internal signal using a signal obtained from the average level of means for obtaining a detection signal that detects the state of intermittent radio waves; and based on the detection signal, the detection data is stored in a second memory portion in place of the detection data to be stored in the first memory portion. means for storing data in the first memory section; means for stopping the operation of a detection circuit for obtaining a phase detection signal based on the detection signal; and detection data stored in the second memory section. The above problem can be solved by providing a direction display signal means for obtaining a direction display signal based on the phase value of the internal signal obtained based on the content of the internal signal or the phase value obtained with the generation of the internal signal. This is what I did.

〔Example〕

Examples will be described below with reference to the drawings.

The basic components of the radio direction finder of the embodiment are constructed in the same manner as described in FIG. 1, and the portion corresponding to the signal processing circuit 4 is constructed as follows.

FIG. 2 shows details of the signal processing circuit 4. 41 consists of the configuration shown in Figure 4.
2 channel receiver 3 with FM component circuit removal circuit
The IF output amplified by
The signals are frequency-converted by frequency converters 41a and 41b, respectively, and then mixed and converted into one beat signal by a separately provided frequency converter 41e. By passing the FM component removal circuit in this way, the frequency modulation component imparted to the received radio wave can be removed. Therefore, even with radio waves such as FM (FS) and SSB, disturbances to the direction signal can be removed, making stable direction measurement possible.

It goes without saying that even if the received signal is not modulated with frequency changes, the phase change component obtained by antenna switching can be extracted through the circuit described above. The output of the FM component removal circuit is a signal as shown in Figure 6b, in which the voltage changes rapidly at the phase change point detected by the detection circuit 43, which is composed of a PLL or a disk drive, an integrator, etc. By integrating , we obtain a phase change caused by the antenna switching scan, a signal in FIG. 6c, which is equivalent to FIG. 6a. This azimuth signal is a double rectified waveform signal (the polarity before rectification is given as is) as shown in Fig. 6d in the post-product circuit 4.
Add to 4.

42 is a signal detection circuit, and the IF output obtained by amplifying the _A0 antenna output is applied to the input through the FM component removal circuit. The amplitude and center frequency of this IF input are detected, and the detection circuit added to the detection circuit 43 and the memory control circuit 413 by ANDing them is used to prevent unnecessary confusion of the PLL at the moment of momentary interruption of radio waves. In order to avoid this, the operation of the PLL is temporarily stopped, and the memory control circuit is used to switch the input to the first memory circuit from the output of the ADC 45 to the output of the second memory circuit. The product circuit 44 includes a multiplier 44a and a SINROM 44 as shown in FIG.
It is composed of b.

That is, the SINROM 44b has input/output of multiple bits and stores one period or half period of the SIN wave, and when the output of the internal signal generation frequency divider circuit 47 is input, the multiple bits change as shown in FIG. 6e. A digital value of bits is obtained. The waveform diagram of this signal shows a stepwise SIN-like change determined by the number of input/output bits of the SINROM, but for simplicity, the average phase is drawn. The multiplier 44a gives the product of two inputs, and is the product of the detected output double-wave rectified waveform of the analog signal of FIG.
The output of SINROM is multiplied by the digital signal shown in Figure 4 e, and the phase of both signals is exactly 90° different, that is, the product output of the waveform in Figure d and the waveform in Figure e, X, and the output shown in Figure 6 f is obtained. .

When the SINROM output is shown in Figures e and Z, the product circuit output changes as shown in waveform diagrams g and h.

In the above-mentioned multiplier, one input is analog and the other input is digital in the embodiment of the present invention, but the result is exactly the same whether both inputs are analog or digital. Multiplication circuit 4
The output of 4 is applied to the next stage ADC (Analog-to-Digital Converter) and is converted into a parallel multi-bit digital value of the signal shown in FIG.
It is input to 0.

The internal signal generation frequency dividing circuit 47 described above is composed of a counter and a presettable counter having input/output of multiple bits, and the reference signal oscillator 4
The signal input from 8 is divided by the counter,
Each output bit is inputted to a presettable counter and divided by a predetermined frequency so that the maximum bit completely matches the frequency of one cycle of the detection output (Fig. 6c). At the same time, each output bit is The phase of the SINROM44 described above can be advanced or delayed.
The phase of the double-wave rectified output signal b (the polarity before rectification is attached as is) shown in FIG. 6e is advanced or delayed to control the product circuit output to have the waveform shown in FIG.

The reference signal oscillator is a crystal or self-excited clock and a reference signal generation oscillator, and its output is input to the internal signal generation frequency divider circuit 47 and the delay frequency divider circuit 46. The delay frequency divider circuit 46 is a frequency divider circuit that generates an antenna scanning reference signal, which is composed of an up-down counter. This is to give correct directions. Reference numeral 49 denotes a delay time setting device, which is composed of a digital switch, etc., and presets the digital output by adding it to the preset input of the up-down counter of the delay frequency divider circuit 46. If the up-count is made, the phase of the delay frequency divider output will change by the preset value. I will move on. In other words, in the up-down counter with a plurality of bits output, the contents of the counter change from 0 to a full count as shown in FIG. 7 in response to a clock input, and this process is sequentially repeated. Therefore, if the counter is preset to the value P at time R as described above, the seventh
Since the output changes as shown by the dotted line in the figure, the signal advances by q relative to the solid line waveform before presetting. In this way, the detector output, in which the delay occurring in the receiver has been automatically corrected, can correctly indicate the direction of the radio wave with respect to the reference signal.

410 is a first memory circuit, 411 is a second memory circuit, and the output of an ADC (Analog-to-Digital Converter) 45 is stored in the first memory circuit.

When inputting to the first memory circuit, a memory area is provided for each output of each antenna, and the output is sequentially inputted and accumulated a predetermined number of times m. When the m-times of accumulation is completed, the output of the first memory circuit is transferred to the second memory circuit, and at the same time, the contents of the first memory circuit are cleared, and the above-described accumulation is repeated.

413 is a control circuit that switches the input to the first memory circuit from the ADC (analog-to-digital converter) output to the second memory output when the received signal is momentarily interrupted due to the output of the signal detection circuit, transfers data between memories, Performs various controls such as addition commands.

If the output of the detection circuit 43 (Fig. 6 d) and the SINROM output (Fig. 6 e) have a phase difference of 90° as shown by the curve X in the figure, the output of the product circuit will be as shown in Fig. 6 (f). . For the sake of explanation, if we omit the second memory circuit, the sum of one cycle (or m cycles) of the first memory circuit is (+), (-), as is clear from Fig. 6f.
Since it cancels out and becomes 0, the output of the adder circuit 412 is 0.
becomes. When d and e in Fig. 6 deviate from the 90° phase difference (for example, in the case of Y or Z in Fig. 6), the output of the multiplier becomes g or h in Fig. 6, and therefore the output of the adder circuit 49 deviates from 0 (+ ) or (-).

In this way, the average level of the output of the product circuit changes (+) or (-) around 0 depending on the phase relationship between the two inputs d and e in FIG. Therefore, if the presettable counter of the internal signal generation frequency division circuit 47 is preset with the contents of the addition circuit 412, the phase of the output of the internal signal generation frequency division circuit 47 will be the same as the content of the output of the addition circuit, and the product will be The contents of the adder circuit increase or decrease until the phase difference between the two input signals of the circuit becomes 90 degrees, controlling the phase of the SINROM output signal and reaching an equilibrium point.

Looking at this operation in the opposite way, the phase of the output of the presettable counter, that is, the preset value, is made to be the same as the output value of the adder circuit 412, and this value is the same as the output of the above average level. The value is obtained by adding the values.

Therefore, the value calculated based on the contents of the second memory is the output of the adder circuit 412, but this value is determined by the phase of the output of the presettable counter as described above, that is, It is the phase value of the internal signal (Fig. 6 e), and the detection output (Fig. 6 e)
Since there is a phase difference of 90° from the phase shown in Figure d), if we correct this 90° internally and measure from the reference point, we can know the direction of arrival of the radio wave, so we added this to indicator 5 and measured. Direction can be displayed.

When receiving actual radio waves, the PLL of the detector may lose lock due to noise or momentary interruption of radio waves, and a normal detection output may not be obtained. Therefore, the contents of the adder circuit 412 cause unnecessary fluctuations in the control system.
This often causes confusion in the pointing system and causes the measurement direction to fluctuate.

For this purpose, a second memory circuit is provided, and after storing the orientation data in the second memory circuit for a predetermined period m, the data is transferred to the respective second memory circuits,
As mentioned above, the total sum is integrated in the adder circuit 412 to control the internal signal generation frequency divider circuit 47, but when the detection output is cut off, the first
The input of the memory circuit is switched to the corresponding second memory circuit output instead of the ADC output. However, since the value of the second memory circuit output is accumulated over a predetermined period, it is necessary to divide the value by a predetermined period m before inputting it to the first memory circuit.

Averaging is performed by these operations, and even if the detected output fluctuates considerably each time due to noise interference or the like, the average value is input to the first memory circuit, so that the sum total in the second memory circuit is also stabilized.

(Modified Implementation) The present invention can be modified and implemented as follows.

(1) As is clear from the figure, the phase of the output of the frequency divider circuit for internal signal generation always has a 90° phase difference with the detection output (Fig. 6 d) when the control of the adder circuit is completed. Since it is the phase value of the signal, if an output corrected by 90 degrees by an adder circuit, for example, a 3-digit numerical value, is added to the indicator 5, a stable direction of arrival of the radio wave can be indicated.

(2) By switching the output of the delay time setting device in conjunction with switching the IF bandwidth of the receiver, there is no need to correct the direction due to delays in the receiver, etc., and measurement operations are greatly simplified. It is also possible to eliminate the need for timing adjustment.

(3) Each circuit within the dotted line in Figure 2 for controlling the aforementioned memory control, averaging processing, etc. can be easily realized using a microcomputer, so everything after the direction signal is detected is processed digitally. This makes it possible to realize a wireless direction finder that operates stably and reliably and is extremely easy to manufacture and adjust.

〔Effect of the invention〕

According to the present invention, as described above, a. The signal detecting circuit 42 detects the quality of the radio wave itself, and eliminates in advance the acquisition of defective data, and replaces the data in between with the previously obtained signal. Since the data is imported, the data in the memory can be made stable and accurate, and the memory can be prevented from being filled with defective data and becoming impossible to measure.

b. Since the internal signal and the phase difference detection memory are synchronized by the product circuit 44 and its associated circuit, good data can be immediately loaded into the memory as soon as the radio wave reception signal is recovered properly. .

c. In a device that detects radio waves whose S/N ratio is not so bad or intermittent, the purpose can be sufficiently achieved without adding a means to stop the operation of the phase difference detection circuit described above. It will be done.

It has the advantage of being able to provide products.

[Brief explanation of drawings]

The drawings show an example. FIG. 1 is a system diagram of the basic components, FIG. 2 is a detailed system diagram of the signal processing circuit 4 shown in FIG. 1, FIG. 3 is an example of the arrangement of antenna groups, and FIG.
5 is a detailed system diagram of the product circuit 44, FIG. 6 is a waveform diagram showing the operation of each part, and FIG. 7 is a waveform diagram showing the operation of the delay divider circuit 46. be. 1... Antenna group, 2... Antenna switching device, 3
... Receiver, 4 ... Signal processing circuit, 5 ... Direction indicator, 6 ... Antenna switching signal generation circuit, 41 ...
...FM component removal circuit, 42...Signal detection circuit, 4
3...Detection circuit, 44...Product circuit, 44a...Multiplier, 44b...SIN ROM (SIN READ
ONLY MEMORY), 45...ADC (analog
digital conversion circuit), 46...Delay frequency divider circuit, 4
7... Frequency divider circuit for internal signal generation, 48... Reference signal oscillator, 49... Delay time setter, 410...
First memory circuit, 411...Second memory circuit, 4
12... Addition circuit, 413... Control circuit.

Claims (1)

[Scope of Claims] 1. The phase difference of the phase change caused by the switching in the received signal obtained by receiving radio waves while sequentially switching and scanning omnidirectional antennas arranged at intervals on the circumference is detected. Data (hereinafter referred to as detection data) obtained based on a signal (hereinafter referred to as phase difference detection signal) is stored in a memory, and the detection of defects caused by deterioration of S/N of the radio waves or intermittentness of the radio waves is performed. Instead of data,
In a radio direction finder (hereinafter referred to as a device) that obtains a signal for displaying the direction of arrival of the radio waves (hereinafter referred to as a direction display signal) by using the previously obtained good detection data, a. internal signal generating means for generating, as an internal signal, a signal that is alternately formed to have positive and negative polarities every 1/2 period of the scanning period; b. c. multiplication polarity signal means for obtaining a signal obtained by multiplying the formed signal and the internal signal as a multiplication polarity signal; c. a multiplication polarity signal means for storing the multiplication polarity signal as the detection data in a first memory portion of the memory 1
a data storage means; d a second data storage means for transferring and storing the detected data stored in the first memory part in a second memory part of the memory; e in the second memory part; an internal signal phase control means for variably controlling the phase of the internal signal using a signal obtained by the average level of each polarity portion of the stored detection data (hereinafter referred to as an average level signal); f not performing the switching; A signal obtained based on a signal received by an omnidirectional antenna (hereinafter referred to as
(referred to as a second received signal), radio wave condition detection means obtains, as a detection signal, a signal that detects a deterioration of the S/N of the radio wave or an intermittent state of the radio wave; g. alternative storage means for storing in the first memory part the detection data stored in the second memory part in place of the detection data to be stored in the second memory part; h storing in the second memory part; and azimuth display signal means for obtaining the azimuth display signal based on the phase value of the internal signal obtained based on the content of the detected data or the phase value of the internal signal obtained with the generation of the internal signal. A device characterized by: 2. The device according to claim 1, comprising: a. the internal signal generating means for generating the internal signal by SIN RON. 3. The device according to claim 1, wherein: a) the average level signal is obtained by an adder circuit, and the variable control is performed by providing a preset input to a presettable counter based on the output of the adder circuit; An apparatus characterized by comprising the internal signal phase control means for controlling the internal signal phase. 4. The device according to claim 1, characterized in that it comprises: a. the radio wave condition detection means that obtains the detection signal by detecting the amplitude and center frequency of the second received signal; Device. 5 A signal obtained by detecting the phase difference of the phase change caused by the switching in the received signal obtained by receiving radio waves while scanning by sequentially switching omnidirectional antennas arranged at intervals on the circumference (hereinafter referred to as phase difference). data (hereinafter referred to as detection data) obtained based on the detection signal (hereinafter referred to as detection signal) is stored in a memory, and in place of the detection data of defects caused by deterioration of S/N of the radio wave or intermittent of the radio wave,
In a radio direction finder (hereinafter referred to as a device) that obtains a signal for displaying the direction of arrival of the radio waves (hereinafter referred to as a direction display signal) by using the previously obtained good detection data, a. internal signal generating means for generating, as an internal signal, a signal that is alternately formed to have positive and negative polarities every 1/2 period of the scanning period; b. a multiplication polarity signal means for obtaining a signal obtained by multiplying the formed signal by the internal signal as a multiplication polarity signal, c.
a data storage means; d a second data storage means for transferring and storing the detected data stored in the first memory part in a second memory part of the memory; e in the second memory part; an internal signal phase control means for variably controlling the phase of the internal signal using a signal obtained by the average level of each polarity portion of the stored detection data (hereinafter referred to as an average level signal); f not performing the switching; A signal obtained based on a signal received by an omnidirectional antenna (hereinafter referred to as
(referred to as a second received signal), radio wave condition detection means obtains, as a detection signal, a signal that detects a deterioration of the S/N of the radio wave or an intermittent state of the radio wave; g. alternative storage means for storing in the first memory part the detection data stored in the second memory part in place of the detection data to be stored in the first memory part; h. a detection operation stop means for stopping the operation of a circuit for obtaining a phase difference detection signal (hereinafter referred to as a detection circuit); i) the internal signal obtained based on the content of the detection data stored in the second memory portion; 3. An apparatus comprising: an azimuth display signal means for obtaining the azimuth display signal based on a phase value of the internal signal or a phase value of the internal signal obtained as the internal signal is generated. 6. The device according to claim 5, comprising: a. the internal signal generating means for generating the internal signal by SIN RON. 7. The device according to claim 5, wherein: a) the average level signal is obtained by an adder circuit, and the variable control is performed by providing a preset input to a presettable counter based on the output of the adder circuit; An apparatus characterized by comprising the internal signal phase control means for controlling the internal signal phase. 8. The device according to claim 5, characterized in that it comprises: a. the radio wave condition detection means that obtains the detection signal by detecting the amplitude and center frequency of the second received signal; Device. 9. The device according to claim 5, comprising: (a) a detection means in which the detection circuit is a detection circuit using a PLL; and (b) the detection operation stop means for stopping the operation of the PLL in response to the detection signal. A device comprising: