JPH0156566B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a voltage input type impedance conversion circuit having an input impedance proportional to load impedance, and is suitable for integration into an integrated circuit.

[Technical background of the invention and its problems]

In the impedance conversion circuit, as shown as a four-terminal network in FIG. 1, the output voltage V ₂ and the output current I ₂ are in a proportional relationship with the load impedance Z _L with respect to the input voltage V ₁ and the input current I ₁ . Its operation is shown by the following equation (1).

V ₁ I ₁ = A B C DV ₂ I ₂ ...(1) In the above formula (1), A≠0, D≠0, B=C=0
This is called an impedance conversion circuit. In the figure, V _io is the input voltage source and Z _S is the input resistance.

Incidentally, in recent years, with the integration of various circuits, it has been desired to realize the above-mentioned impedance conversion circuit with a bipolar integrated circuit.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and its purpose is to provide an impedance conversion circuit that is optimal for integration into an integrated circuit.

[Summary of the Invention] That is, in the present invention, an input voltage is supplied to a voltage-current converter comprising a voltage follower, and a current corresponding to the input voltage is supplied from the voltage-current converter to a first current mirror circuit. , a current corresponding to this current is supplied from the first current mirror circuit to the second current mirror circuit, and the second current mirror circuit is supplied with a current corresponding to the current.
By feeding back the current obtained by the current mirror circuit to the input terminal of the voltage-current converter, the input impedance is proportional to the load impedance connected to the voltage-current converter.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. Figure 2 shows its configuration.
Voltage-current converter 11 consisting of a voltage follower
A first current mirror circuit 12 consisting of PNP transistors Q ₂ and Q ₃ is provided between the (NPN transistor Q ₁ ) and the positive power supply (one of the power supplies), and a current mirror circuit 12 is provided between the emitter of the transistor Q ₁ and the ground point. By connecting a load impedance Z _L to and supplying an input voltage V 1 and an input current _{I 1 to} the base input terminal 13 of the transistor Q ₁ , the collector current of the transistor Q ₁ (proportional to the input voltage V ₁ ) is
is supplied to the bases of transistors Q ₂ and Q ₃ forming the first current mirror circuit 12. Then, a current _ICE corresponding to the collector-emitter current of the transistor _Q1 obtained by the current mirror circuit 12 is passed through the NPN transistors _Q4 to _Q6 , one end of which is connected to a negative current (the other side of the power supply). It is supplied to the second current mirror circuit 14. The current corresponding to the collector-emitter current of the transistor Q ₁ obtained by the current mirror circuit 14 is fed back to the base of the transistor Q ₁ , and the output voltage V ₂ and the current I are output from the output terminal 15 on the emitter side of the transistor Q ₁ . Get ₂ .

The operation in the above configuration will be explained. When the input voltage V ₁ is applied to the input terminal 13, the base voltage of the transistor Q ₁ becomes V ₁ , and the output voltage V ₂ at this time is calculated by subtracting the base-emitter voltage V _BE of the transistor Q ₁ from the input voltage V ₁ . Therefore, the output voltage V ₂ and current I ₂ are expressed by the following equations (2) and (3).

V ₁ = V ₂ + V _BE ……(2) −I ₂ = V ₂ /Z _L = V ₁ −V _BE /Z _L ……(3) Now, the common base current amplification factor α of transistor Q ₁ is “1”. ”, the collector current of transistor Q ₁ will be equal to I ₂ . Current mirror circuit 1
Let the current transfer ratios of 2 and 14 be r ₁₂ and r ₁₄ , respectively,
Assuming that the base current of the transistor Q ₁ can be ignored, the input current I ₁ becomes I ₁ =−r ₁₂ ·r ₁₄ ·I ₂ (4). Therefore, input voltage V ₁ is applied to transistor Q ₁
When the base-emitter voltage V _BE is sufficiently large compared to the base-emitter voltage _{V BE} of The transfer matrix in this case is the following formula (5)
It will be shown as

V ₁ I ₁ =1 0 0 −r ₁₂ r ₁₄ V ₂ I ₂ ...(5) A=1, B=0 C=0, D=r ₁₂ , r ₁₄ ≠0 The above equation (5) is This matches the definition of the impedance conversion circuit shown in equation (1).

In FIG. 2, the current mirror circuit 1
The transmission ratios r ₁₂ and r ₁₄ of 2 and 14 are respectively “r ₁₂ = 1,
r ₁₄ = 2'', the transfer matrix is V ₁ I ₁ = 1 0 0 −2V ₂ I ₂ (6).

The impedance conversion circuit described above can be represented by the block diagram shown in FIG. This circuit is equivalent to the circuit shown in FIG. 1 in which the potential of one of the input and output terminals is shared as the ground potential.

According to such a configuration, an input impedance proportional to the load impedance can be obtained. Also, the emitter area ratio of transistors Q ₂ and Q ₃ forming the first current mirror circuit, or the
Transistor forming current mirror circuit 14
By changing the emitter area ratio between Q ₄ and Q ₅ and Q ₆ , the current transfer ratios r ₁₂ and r ₁₄ can be changed and the current fed back to the input terminal 13 can be freely set, so the desired impedance conversion characteristics can be achieved. An impedance conversion circuit having the following is obtained.

In order to investigate the operating characteristics of the circuit shown in FIG. 2, a circuit as shown in FIG. 4 was formed and an experiment was conducted. In the figure, V _S is a variable DC power supply (0 to 10 V),
R _S is input resistance (1kΩ), R _L is load resistance (1kΩ),
PNP type transistor Q ₇ and NPN type transistor Q ₈ are connected to current mirror circuit 12,
14 is a transistor for correcting the output current,
Power supply voltage Vcc=10V, current mirror circuit 12,
The current transfer ratios r ₁₂ and r ₁₄ of 14 are respectively ``r ₁₂ = 1,
r ₁₄ = 2. The theoretical formula for the characteristics of this impedance conversion circuit is shown in the following formula.

V _S = R _S I ₁ + V _BE + R _L I ₂ ... (7) I ₁ = -2I ₂ ... (8) Since the resistors R _S and R _L are both 1kΩ, V _S = -3RI ₂ + V _BE ……(7)′, and the input voltage V ₁ is: V ₁ = V _S −RI ₁ = V _S +2RI ₂ = V _S −2R/3R (V _S − V
_BE ) = 1/3V _S + 2/3V _BE ...(9). Assuming that the base-emitter voltage V _BE of transistor Q ₁ can be ignored, the input voltage V ₁
is 1/3 of _VS. Therefore, this corresponds to the case where the resistance value of the load resistor R _L is halved and is connected to the input terminal 13. Further, the output voltage V ₂ is V ₂ =−RI ₂ =1/3 (V _S −V _BE ) (10). In Fig. 5, the actual measured value of the output voltage V ₂ with respect to the voltage of the applied DC power supply V _S is shown as a solid line, and the above equation (10) is shown.
The theoretical value according to the equation is shown by the broken line.

In the transfer determinant of equation (5) above, if the impedance of the load is Z _L , then V ₂ /−I ₂ =Z _L (11). The input impedance Z _io when looking at this impedance conversion circuit from the input side is Z _io = V ₁ / I ₁ = V ₂ / −r ₁₂ r ₁₄ I ₂ = Z / r ₁₂ r ₁₄ ...(12) Yes, the input impedance Z _io is proportional to the load impedance.

FIG. 6 shows a circuit diagram when a capacitor C _L is used as a load. In the figure, the same components as those in FIG. 2 or 4 are given the same reference numerals and their explanations will be omitted. When a capacitor _CL is used as a load, a diode D is connected between the emitter and base of the transistor _Q1 to discharge the charge stored in the capacitor _CL . Furthermore, since this circuit forms a closed loop, a capacitor _C11 for preventing oscillation is provided between the base of the transistor _Q1 and the ground point. Input impedance Z _io in this case
Z _io =1/jωC _L ×r ₁₂ r ₁₄ (j=√−1) (13) Therefore, it is equivalent to the load capacity _CL being r ₁₂ r ₁₄ times larger. Therefore, when r ₁₂ r ₁₄ =2, it is equivalent to connecting a capacitor with twice the capacitance (2C _L ) when viewed from the input side, and a large time constant can be obtained with a small capacitor.

As shown in Figure 7, when a pulsed signal is applied as the input signal _Vio , impedance conversion works during the charging process of the capacitor _CL , but impedance conversion does not work when the capacitor _CL is discharged. The output voltage V ₂ rises slowly and falls quickly. Input/output voltage
The rising time constant of V ₁ and V ₂ is 2R _S C _L and the falling time constant is R _S C _L . In other words, a large time constant can be achieved with a capacitor of small capacitance, and if this invention is applied to devices that use capacitors of relatively large capacitance, such as low-pass filters, the pattern area can be reduced and high integration becomes possible. Become. R _S
When we measured the rise and fall time constants when = 1kΩ and C _L = 0.1μF, the rise time constant was
It was confirmed that the rising time constant was 0.23 msec, and the falling time constant was 0.12 msec, and that the rising time constant was approximately twice the falling time constant.

FIG. 8 shows another embodiment of the present invention. In the circuits of FIGS. 2, 4, and 6, the output voltage V ₂ is set to a transistor as shown in equation (2). This is to correct for the error caused by the base-emitter voltage V _BE of _Q1 .
That is, an NPN type transistor Q ₁ is connected between the first current mirror circuit 12 and the load Z _L as the voltage-current converter 11, and the input voltage V _io is supplied to the non-inverting input terminal (+) so that it is inverted. An operational amplifier 16 is provided at the input end (-) of which the emitter side voltage of the transistor _Q1 is supplied and whose output controls the conduction of the transistor _Q1 . According to such a configuration, the conduction of the transistor Q ₁ is controlled by the comparison output between its emitter potential and the input voltage V _io , so that an error due to the base-emitter voltage V _BE of the transistor Q ₁ does not appear in the output. .

Note that the DC current source _I a connected between the output terminal 15 and the ground point is for discharging the charge of the load impedance Z _L , and the DC current source I _b connected between the positive power supply and the input terminal 13 is for discharging the charge of the load impedance Z L. This is a current source for correction to prevent the level of output voltage V ₂ from decreasing due to current source I _a . (I _a = I _b ) FIGS. 9 and 10 show other embodiments of the present invention. In each of the above embodiments, one end of the load impedance Z _L is grounded, but the load impedance
This is when Z _L is disconnected from the ground potential. The circuit shown in FIG. 9 corresponds to the circuit shown in FIG. 2 arranged symmetrically. That is, the input voltage V _io ,
a pair of voltage-current converters 11 comprising a voltage follower supplied with V _io ' and obtaining a current proportional to this voltage;
11′ (NPN type transistors Q ₁ , Q ₁ ′) are provided,
First and second current mirror circuits 12, 12' each consisting of PNP type transistors Q ₂ , Q ₃ and Q ₂ ', Q ₃ ' are connected between the voltage-current converter 11, 11' and one of the positive current power supplies. A pair of first and second constant current sources I _a and I _a ' are provided between the voltage-current converters 11 and 11' and the negative power source (the other power source). Furthermore, NPN transistors Q ₄ , Q ₅ and Q ₄ ′, whose emitters are connected to the negative power supply, respectively,
A pair of third and fourth current mirror circuits 14, 14' consisting of transistors Q ₅ ' are provided to supply the outputs of the current mirror circuits 12, 12', and the outputs of the current mirror circuits 14, 14' are connected to transistors Q ₁ , Return to the base of Q ₁ ′. Further, a constant current is supplied from the positive power supply to the bases of the transistors Q ₁ and Q ₁ ' through a pair of third and fourth DC constant current sources I _b and I _b ', and the transistors Q ₁ and Q ₁ ' emitter side output terminal 1
A load Z _L is connected between 5 and 15'.

According to such a configuration, any load impedance is connected to the input terminals 13 and 1 in a floating state.
Obtained between 3'. Therefore, connections can be made between any nodes of the network.

FIG. 10 shows another embodiment of the present invention, in which, like the circuit shown in FIG. 9, the circuit shown in FIG. 8 is arranged symmetrically to release the load impedance Z _L from the ground potential. be. Even in this configuration, the same operation as in the embodiment shown in FIG. 9 is performed, and an impedance conversion circuit without error in the base-emitter voltage V _BE of the transistors Q ₁ and Q ₁ ' can be obtained.

[Effects of the Invention] As explained above, according to the present invention, an impedance conversion circuit optimal for integration into an integrated circuit can be obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an impedance conversion circuit, FIG. 2 is a diagram showing an impedance conversion circuit according to an embodiment of the present invention, FIG. 3 is a block diagram of the impedance conversion circuit of FIG. 2, and FIG. Figure 4 is an experimental circuit diagram used to confirm the operation of the impedance conversion circuit according to the present invention, Figure 5 is a characteristic diagram of applied voltage and output voltage in the experimental circuit of Figure 4, and Figure 6 is a diagram of the present invention. FIG. 7 is a timing chart for explaining the operation of the circuit shown in FIG. 6, and FIGS. 8 to 10 are circuit diagrams showing other embodiments of the present invention. It is. V ₁ ... Input voltage, I ₁ ... Input current, V ₂ ... Output voltage, I ₂ ... Output current, 11 ... Voltage-current converter, 12, 12', 14, 14' ... Current mirror circuit , 13... input terminal, 15... output terminal,
16, 16'...Operational amplifier, _Q1 ~ _Q8 ,Q1 _' ~
Q ₅ ′...Transistor, I _a , I _a ′, I _b , I _b ′... Constant current source, D... Diode, C _L ... Load capacitance, C ₁₁
...Capacitor, ...Positive power supply, ...Negative power supply.

Claims (1)

[Claims] 1. A voltage-current converter comprising a voltage follower to which an input voltage is supplied, a first current mirror circuit to which a current corresponding to the input voltage is supplied from the voltage-current converter, and the current mirror circuit. and a second current mirror circuit that is controlled by a current supplied from the voltage current converter and returns a current corresponding to the current to the input terminal of the voltage current converter, and is connected to a load connected between the voltage current converter and the ground point. An impedance conversion circuit characterized in that it is configured to obtain a proportional input impedance from a connection point between a voltage-current converter and a load. 2 The voltage-current converter has a collector whose collector is connected to the first
A patent characterized in that it consists of an NPN type transistor connected to a current mirror circuit, whose emitter is grounded via a load, and whose base is supplied with an input voltage, and configured so that output is obtained from the emitter of this transistor. An impedance conversion circuit according to claim 1. 3 The voltage-current converter has a collector connected to the first
An NPN transistor connected to a current mirror circuit whose emitter is grounded via a load capacitance and whose base is supplied with input voltage, a diode connected between the emitter and base of the transistor, and the base of this transistor. 2. The impedance conversion circuit according to claim 1, comprising a capacitor for preventing oscillation connected between a ground point and a ground point, and configured to obtain an output from the emitter of the transistor. 4 In the voltage-current converter, the collector is connected to the first
An NPN transistor is connected to a current mirror circuit and its emitter is grounded through a load, the input voltage is supplied to the non-inverting input terminal, the emitter voltage of the transistor is supplied to the inverting input terminal, and the output controls the conduction of the transistor. 2. The impedance conversion circuit according to claim 1, wherein the impedance conversion circuit comprises an operational amplifier configured to obtain an output from the emitter of the transistor. 5 A pair of voltage-current converters each comprising a voltage follower to which a differential input voltage is supplied, and a voltage-current converter connected between each of the voltage-current converters and one of the power sources, and a current corresponding to the differential input voltage is connected to the voltage of the pair of voltages. a pair of first and second current mirror circuits supplied from the current converter; a pair of first and second current mirror circuits connected between each of the pair of voltage-current converters and the other of the power source;
A constant current source, one end of which is connected to the other of the power supply, is controlled by the current supplied from the first and second current mirror circuits, and a current corresponding to this current is fed back to the input ends of the pair of voltage-current converters. the third of the pair,
It comprises a fourth current mirror circuit, and a pair of third and fourth constant current sources that supply constant current to the respective input ends of the pair of voltage-current converters, and the pair of voltage-current converters and the first, An impedance conversion circuit characterized in that the impedance conversion circuit is configured to obtain an output whose impedance is converted according to a load disposed between a connection point with a second constant current source from both ends of the load. 6 The above-mentioned pair of voltage-current converters include a pair of NPN type transistors whose collectors are connected to the above-mentioned first or second current mirror circuit, whose emitters are commonly connected through a load, and whose conduction is controlled by a differential input voltage. 6. The impedance conversion circuit according to claim 5, wherein the impedance conversion circuit is configured to obtain an output from both ends of the load. 7 The above-mentioned pair of voltage-current converters are a pair of voltage-current converters whose collectors are connected to the above-mentioned first or second current mirror circuit and whose emitters are commonly connected through a load.
It consists of an NPN transistor, and a pair of operational amplifiers whose non-inverting input terminals are supplied with a differential input voltage, whose inverting input terminals are supplied with the emitter voltages of the pair of transistors, and whose outputs control the conduction of the pair of transistors. 6. The impedance conversion circuit according to claim 5, wherein the impedance conversion circuit is configured to obtain an output from both ends of the load.