JPH0157433B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device, and particularly to an MIS (metal insulating film semiconductor) integrated circuit device including a high resistance element such as one constructed of a polycrystalline silicon layer.

In a static RAM (Random Access Memory) configured with MISFETs (Insulated Gate Field Effect Transistors), the memory cells are, for example, two switching MISFETs whose gates and drains are cross-connected;
It can be constructed by a polycrystalline silicon layer as a drain load resistance of MISFET.

The resistance element made of the polycrystalline silicon layer can have a relatively high resistance value without increasing its length. Therefore, the memory cell as described above can be made smaller than a memory cell having other configurations, such as using MISFET as a resistance element.

The power consumption in a memory cell is determined by the current flowing through one of the pair of cross-connected switching MISFETs that is turned on, and the current flowing through the other MISFET that is turned off.
It is determined by the drain leakage current flowing through the MISFET.

The drain current of the above MISFET in the on state is
This can be limited by making the resistance element connected to the drain relatively high in resistance.

The resistance value of the above resistance element is in the off state.
Its upper limit is limited by the MISFET's drain leakage current. In other words, if the power supply value of the resistor element is made too large, the drain potential of the MISFET, which is turned off due to the voltage drop across the resistor element caused by the leakage current, will exceed this drain potential. This is because the voltage will drop below the threshold voltage of the cross-connected MISFET that receives the gate, and as a result, the data retention characteristics of the memory cell will no longer be guaranteed.

Therefore, in order to reduce the power consumption of the memory cell, it is desirable that the resistance value of the resistance element be increased within a range that guarantees the data retention characteristics as described above.

However, the resistance value of polycrystalline silicon layers obtained by conventional MIS integrated circuit device manufacturing techniques varies relatively widely.

In addition, the resistance value of the polycrystalline silicon layer and
All drain leakage currents, such as the drain junction leakage current of MISFETs, vary with temperature. In this case, the resistance value of the polycrystalline silicon layer usually decreases as the temperature increases, and the drain leak current increases as the temperature increases. Therefore, the increase in drain leakage current due to temperature rise is partially compensated for by the decrease in the resistance value of the polycrystalline silicon layer. However, the temperature coefficient of resistance of the polycrystalline silicon layer and the temperature coefficient of the drain leakage current usually do not match.

Therefore, for the reasons mentioned above, if the design center value of the resistance value of the resistor element is set to a relatively large value, the manufacturing yield of the MIS memory will decrease and the temperature margin will deteriorate.
On the other hand, if the design center value of the resistance value of the resistance element is set to a small value, the current consumption will increase.

Furthermore, in a dynamic logic circuit, it is conceivable to provide high resistance means to maintain the node voltage, but the same problem as described above occurs in this case as well.

Therefore, one object of the present invention is to provide a semiconductor integrated circuit device that can increase manufacturing yield and temperature margin.

Another object of the present invention is to provide a semiconductor integrated circuit device in which an operating voltage applied via a resistance element is corrected.

Another object of the present invention is to provide a MIS static memory in which the operating voltage applied via a resistive element is corrected.

Further objects of the invention will become apparent from the following description and drawings.

According to the invention, power is supplied to a circuit such as a memory cell by the output of a detection circuit including a resistive element and an active element such as a diode-connected MISFET or a diode connected in series with the resistive element. Voltage is controlled. As a result of controlling the power supply voltage described above, the operating voltage supplied from the resistive element in the circuit such as the memory cell to the active element such as MISFET is independent of the resistance value of the resistive element and the leakage current of the active element. To,
Maintained at desired value.

Hereinafter, this invention will be explained in detail together with examples.

FIG. 1 is a circuit diagram showing an embodiment of a static RAM to which the present invention is applied.

Although not particularly limited, the RAM shown in the figure may be a well-known RAM.
It is formed on a single silicon single crystal semiconductor substrate by CMOS (complementary metal-insulator-semiconductor) integrated circuit (IC) technology. Terminals V _DD , V _SS , AX ₁ ,
AX ₂ , D _OUT , D _IN , , AY ₁ and AY ₂ are
It is considered as its external terminal.

In FIG. 1, 1a to 1d are memory cells. These memory cells 1a to 1d are
As shown in memory cell 1a as a representative, high resistance loads R ₁ and R ₂ formed of polycrystalline silicon layers
and a flip-flop circuit composed of N-channel drive MISFETQ ₁ and Q ₂ , and an n-channel transmission gate MISFET Q ₃ , which is provided between the input/output terminal of this flip-flop circuit and the input/output terminal of the memory cell. It consists of Q ₄ .

These memory cells are arranged in a matrix. The gates of the transmission gates MISFETQ ₃ , Q ₄ , etc. of the memory cells arranged in the same row are commonly connected to the corresponding word line W ₁ or W ₂ , respectively, and the input/output terminals of the memory cells arranged in the same column are connected to each other. A pair of bits (data lines) D ₁₀ ,
Connected to D ₁₁ or D ₂₀ and D ₂₁ .

In the above memory cell, in order to make it low power consumption, its resistor R ₁ can keep the gate potential of MISFETQ ₂ almost at the threshold voltage when MISFETQ ₁ is turned off. The resistance value is set to a certain level. Similarly, resistor _R2 is also made to have a high resistance value.

In other words, in order to reduce the power consumption of the memory cell, the resistor R ₁ is configured so that the information charge stored in the gate capacitance (not shown) of MISFETQ ₂ is discharged by the drain leakage current of MISFETQ ₁ . It is designed to have enough current supply capacity to prevent it from being stored away. Similarly, resistor R ₂ is set when MISFETQ ₂ is turned off.
The information charge at the gate of MISFETQ ₁ is
It is designed to have enough current supply capability to prevent discharge due to MISFETQ ₂ 's drain leakage current.

According to this embodiment, although the RAM is manufactured by CMOSIC technology, the memory cell is composed of an n-channel MISFET and a polysilicon resistance element as described above.

When using the memory cell as described above, the size of the memory cell itself and the size of the memory cell array can be made smaller than when using memory cells with other configurations.

For example, instead of the above resistor R ₁ , the above drive
A memory cell configured to use a p-channel MISFET that operates complementary to MISFETQ ₁ , and also uses a p-channel MISFET that similarly operates complementary to the drive MISFETQ ₂ in place of the resistor R ₂ . In this case, the p-channel MISFET is made larger than the polysilicon resistor, and the p-channel MISFET and n-channel MISFET must be separated by a relatively large distance. As a result, the size of the memory cell itself and the memory cell array must become relatively large.

A memory cell configured using a p-channel type MISFET and an n-channel type MISFET as described above is a memory cell using the above-mentioned p-channel type MISFET connected in series.
The MISFET and the n-channel MISFET are operated in a complementary manner, thereby exhibiting low power consumption characteristics. In contrast, the first
In the memory cell shown in the figure, the resistive element
A direct current is passed through the driving MISFET Q ₁ or Q ₂ via R ₁ or R ₂ . However, the memory cell shown in FIG. 1 exhibits sufficient low power consumption characteristics by setting the resistance values of the resistance elements R ₁ and R ₂ to a high value of several megohms to several gigaohms. Become.

Although not shown, the n-channel type shown in Figure 1
The MISFET and p-channel MISFET are structured to have a polysilicon gate electrode.
Accordingly, the polysilicon resistance elements R ₁ and R ₂ are connected to the corresponding drive MISFET Q ₁
and the gate electrode of _Q2 . According to such a configuration, it is possible to further reduce the size of the memory cell.

In FIG. 1, the word line W ₁ is selected by the X address decoder circuit 2a, and the word line W ₂
is selected by the X address decoder circuit 2a. These X address decoder circuits 2a, 2b
have similar configurations, and as shown in detail with 2a as a representative, although not particularly limited, a p-channel type MISFETQ ₁₈ as a load that is switch-controlled by a control signal', and a drain-source A NOR circuit consisting of n-channel drive MISFETs _{Q 16} and Q ₁₇ , which are connected in parallel and address signals bx ₁ to bx ₂ are supplied to their gates, and an n-channel output MISFET.
It consists of an output buffer circuit consisting of MISFETQ ₁₉ , Q ₂₀ and a complementary inverter circuit IN.

Note that the illustrated X address decoder circuits 2a and 2b have n-channel drive in their NOR circuits.
P-channel type that corresponds to each of MISFETQ ₁₆ and Q ₁₇ and can be operated complementary to each other.
Since MISFET such as MISFET is not provided, it is constructed with relatively few circuit elements. MISFETQ ₁₉ in output buffer circuit
is relatively large because the word line constitutes a relatively heavy capacitive load, but it is of an n-channel type rather than a p-channel type.
Normally, when the same conductance characteristics are required, an n-channel MISFET can be made smaller than a p-channel MISFET, so
The output buffer circuit described above can be made relatively small despite the inverter circuit IN being provided. That is, the X address decoder circuits 2a and 2b can be made relatively small.

Address signals supplied from suitable circuit devices (not shown) are input to address buffer circuits BX ₁ and BX ₂ via address input terminals AX ₁ and AX ₂ . Address buffer circuits BX ₁ and BX ₂ above
outputs non-inverted address signals bx ₁ , bx ₂ and inverted address signals ₁ and ₂ in response to input address signals. The output address signals are appropriately selected and supplied to the X address decoder circuits 2a and 2b.

Each pair of bit lines in the memory array
D ₁₀ , D ₁₁ , D ₂₀ and D ₂₁ are transmission gates MISFETQ ₉ , Q ₁₀ and Q ₁₁ for bit line selection, respectively;
It is connected to common bit lines CD ₀ and CD ₁ via a column switch circuit 4 composed of Q ₁₂ .

The input terminals of the read output circuit 6 are connected to the common bit lines CD ₀ and CD ₁ , and the transmission gates MISFETQ ₁₃ and Q ₁₄ are controlled by the write signal WE.
The output terminal of the write circuit 7 is connected through the. And between the common bit lines CD ₀ and CD ₁ is a p-channel type for data reset.
MISFETQ ₁₅ is provided.

A pair of MISFETs Q ₉ and Q ₁₀ for selecting the above bit lines
A selection signal is supplied to the gates of Q ₁₁ and Q ₁₂ from Y address decoder circuits 3a and 3b, respectively.

The Y address decoder circuit 3a receives a control signal
It consists of a p-channel type MISFETQ ₂₃ as a load resistance that is switch-controlled by CS′, and n-channel type drive MISFETs Q ₂₁ and Q ₂₂ whose respective gates are supplied with address signals by ₁ to by ₂ . . Note that the Y address decoder circuits 3a, 3
Since the load on b is light, the above
An output buffer circuit as in address decoder circuits 2a and 2b is not provided.

Although not particularly limited, the readout circuit 6 includes:
It consists of a three-state circuit including an output floating state or a high output impedance state. The read circuit 6 outputs a signal corresponding to the data signal supplied to the common bit lines _CD0 and _CD1 when the control signal CS is set to high level. When the control signal CS is set to a low level such as a ground potential, the readout circuit 6
The output terminal is brought into the floating state.

8 is a control circuit which receives a write control signal via an external terminal and a chip selection signal via an external terminal, thereby controlling the read circuit 6 and the X address decoder circuits 2a, 2.
b, Y address decoder circuit 3a, 3b, MISFETQ ₁₅ for data reset, transmission gate
For MISFETQ ₁₃ , Q ₁₄ , and bit line loads
Outputs control signals to control MISFETQ ₅ to Q ₈ .

When the chip selection signal is set to low level, the control signal CS is set to high level in response to this,
CS′ is set to low level. The X address decoder circuit 2
a, 2b, Y address decoder circuits 3a and 3b
is activated and MISFETQ ₅ for bit line load
Or _Q8 is turned on.

The driving MISFET Q ₁ , Q ₂ in the memory cell coupled to the selected word line is connected to its transmission gate.
It is coupled to the corresponding pair of bit lines via MISFETQ ₃ and Q ₄ . As a result, the paired bit lines are given data corresponding to the data previously written in the memory cell. In this case, the above driving MISFETQ ₁ , Q ₂ ,
Since a relatively large level of operating current is supplied through the bit line load MISFET and the transmission gate MISFETs _{Q 3} and Q ₄ , a relatively large level of operating current is supplied to the bit line pair.
and will be supplied with a data signal that changes at a relatively high rate.

The data signals on the paired bit lines are supplied to the readout circuit 6 via the column switch circuit 4 and the common bit lines CD ₀ and CD ₁ . As a result, the address signal supplied to address input terminal AX ₁ or AX ₂ and the address signal supplied to address input terminal AY ₁ or AY
Data in one memory cell selected by the address signal supplied to AY ₂ is read out via the readout circuit 6.

When the write control signal is set to low level,
In response to this, the control signal WE is set to high level,
Transmission gates MISFETQ ₁₃ and Q ₁₄ are turned on. The write data signal output from the write circuit 7 is supplied to the memory cell via the MISFETs _{Q 13} and Q ₁₄ and the column switch circuit 4. As a result, the data supplied to the external terminal D _1o will be written into the memory cell selected by the address signal.

In this embodiment, each address buffer circuit, address decoder circuit, readout circuit,
The write circuit and the control circuit are operated by a power supply voltage directly supplied from an external power supply 10 placed outside the IC.

On the other hand, the memory cell is operated by a voltage output from a power supply circuit 9 configured within the IC. The specific configuration of this power supply circuit 9 will be explained in detail next.

In FIG. 1, the directions of arrows attached to the base gates of each MISFETQ ₁ to _{Q 22} are distinguished and displayed according to each channel type.

In Figure 1, each p-channel type MISFET
And the base gate of each n-channel type MISFET is
For convenience of the drawing, it is shown as if it is not connected anywhere. However, the body gate of each p-channel type MISFET is coupled to the power supply terminal V _DD , and the body gate of each n-channel type MISFET is coupled to the ground terminal V _SS .

However, it is desirable that the source follower MISFETQ ₁₉ in the X address decoder circuits 2a and 2b has its base gate coupled to its source. In this way, it is possible to prevent the threshold voltage of the MISFETQ ₁₉ from increasing due to the well-known body bias effect, and as a result, it is possible to obtain a word line drive signal that has a higher level and can change at a higher speed. You will be able to do this.

In the above memory cell, the resistors R ₁ and R ₂ made of polysilicon layers can be relatively small and have a high resistance value, but their resistance values vary relatively widely due to various manufacturing technology reasons. It turns out.

If the resistance values of the above-mentioned resistors R ₁ and R ₂ are made too large due to variations in the manufacturing conditions, these resistors R ₁ and R ₂
It becomes impossible to maintain the gate potential of one of MISFETs _Q1 and _Q2 at a value higher than its threshold voltage. As a result, no data is retained within the memory cell.

Similarly, as the temperature rises while the RAM is in use, there is a difference between the increase in drain leakage current and the increase in current due to a decrease in resistance (as mentioned above, polysilicon resistance has a negative temperature coefficient). Even if the gate potential of MISFET _{Q 1} or Q ₂ is no longer maintained above its threshold voltage, data will no longer be retained in the memory cell.

In this example, the memory cell resistances R ₁ and R ₂
The resistance value of is designed to be smaller than that in the case where the voltage supplied to the terminal V _DD is directly supplied to the memory cell, taking into consideration its variation and the maximum value of the voltage output from the power supply circuit 9. It will be done like this.

FIG. 2 is a circuit diagram showing one embodiment of the power supply circuit.

The circuit consists of a p-n junction diode as shown
It consists of a series circuit of D ₁ and resistor R ₃ , and a MISFET Q ₂₄ whose drain is connected to the power supply voltage terminal V _DD and whose gate is connected to the connection point of the series circuit. The output voltage of this circuit is the above MISFETQ ₂₄
obtained from sources.

When the static RAM is constituted by a complementary semiconductor integrated circuit using an n-type silicon single-layer semiconductor substrate, each element shown in FIG. 2 has a structure as shown in FIG. 3.

That is, the diode _D1 includes a p-type semiconductor region 21b formed on the surface of the n-type semiconductor substrate 20 and an n-type semiconductor region 21b formed on the surface of the p-type semiconductor region 21b.
type semiconductor region 22a, and a resistor
R ₃ is a relatively thick field oxide film 2 on the p-type semiconductor region 21a on the surface of the n-type semiconductor substrate 20.
4 is formed by a polysilicon layer 25a formed through the polysilicon layer 25a. Also, n-channel type
The MISFETQ ₂₄ includes an n-type drain region 22b formed on the surface of the p-type semiconductor region 21c formed on the surface of the substrate 20, an n-type source region 22c, and the above-mentioned region between the drain region 22b and the source region 22c. It consists of a gate electrode 25b made of n-type polysilicon formed on the surface of the p-type semiconductor region 21c with a relatively thin gate oxide film 23 interposed therebetween.

The polysilicon layer 25a has a terminal region 25 made of polysilicon with a relatively high impurity concentration.
It has a ₁ and 25a ₂ . Above terminal area 25a ₁
A conductor layer 26a, such as a vapor-deposited aluminum layer, is connected to the p-type semiconductor region 21a, which is connected to the ground potential of the circuit. Above terminal area 25a ₂
Although not shown, is configured to be continuous with the gate electrode 25b of the MISFETQ ₂₄ . The terminal region 25a ₂ is also connected to a p-type semiconductor region 21b serving as an anode region of the diode D ₁ via a conductor layer 26b.

n as the cathode region of the diode D ₁ above
The type semiconductor region 22a and the drain region 22b of the MISFETQ ₂₄ are connected to a conductor layer 26c connected to the power supply terminal _VDD .

The source region 22c of the MISFETQ ₂₄ and the p-type semiconductor region 21c as a base gate are connected to the conductor layer 26d.

The above structure can be obtained, for example, by the following manufacturing method.

First, an n-type single crystal silicon semiconductor substrate 20 is prepared, and a photoresist film is applied to the surface thereof.

By selectively exposing and developing the photoresist film, the p-type semiconductor regions 21a to 21
c, and memory cell n-channel MISFET
p-type semiconductor region (not shown) for forming
Then, using the photoresist film as a mask, a p-type impurity such as boron is introduced into the surface of the semiconductor substrate by a known ion implantation method.

By thermally oxidizing the surface of the semiconductor substrate 20, or by thermally oxidizing the surface of the semiconductor substrate 20,
By oxidizing the surface of the semiconductor substrate excluding the source region, gate region, drain region, semiconductor wiring region of the MISFET, the cathode region 22a of the diode, and the surface portion to be used as the contact region, by selective thermal oxidation method. A relatively thick field oxide film 24 is formed. Note that during this thermal oxidation, the p-type impurity introduced earlier is stretched to form the p-type region 21a and the like.

The surface portions of the semiconductor substrate 20 that will be used as the region where the MISFET will be formed, the wiring region, the cathode region, and the contact region are exposed, and then a comparative film of the same thickness as the gate oxide film of the MISFET is formed on the exposed surface portion by thermal oxidation. Forms a thin oxide film.

A polysilicon layer is formed on the surface of the semiconductor substrate 20 by chemical vapor deposition.

An n-type impurity, such as phosphorus, is introduced into the polysilicon layer by ion implantation. By this ion implantation, n-type impurities are introduced into the polysilicon layer in an amount that will ultimately determine the specific resistance of the resistor element of the memory cell and the resistor _R3 in FIG.

After or before introducing the n-type impurity, p-channel type and n-channel type
The polysilicon layer is selectively etched except for the gate electrode of the MISFET, the resistor 25a, and the portions to be used as polysilicon wiring.

The remaining surface of the polysilicon layer is thinly oxidized.

A photoresist film is selectively formed on the portion of the polysilicon layer that is to be the resistor of the memory cell and the portion that is to be the resistor _R3 .

Using the photoresist film as an etching mask, the oxide film on the polysilicon layer and the relatively thin oxide film not covered by the polysilicon layer are etched away. By this etching, a mask layer 27 for preventing impurity introduction is left on the portion of the polysilicon layer which is to be the resistor.

After removing the photoresist film, a new photoresist film is formed.

By selectively exposing and developing the above new photoresist film, p-channel MISFET
A portion where a p-type semiconductor wiring region is to be formed, and a portion where a p-type polysilicon wiring is to be formed are exposed.

Using the photoresist film and field oxide film as masks, p-type impurities are introduced into the exposed polysilicon layer and the surface of the semiconductor substrate by ion implantation. This ion implantation creates a p-channel type into the polysilicon layer.
P-type impurities necessary for the gate electrode and wiring of the MISFET are introduced, and the source region of the p-channel MISFET,
A necessary amount of p-type impurity is introduced to form a drain region and a semiconductor wiring region.

The photoresist film is removed and a new photoresist film is formed. By selectively exposing and developing this photoresist film, an n-channel type
A portion where a MISFET is to be formed, a portion where an n-type semiconductor wiring region is to be formed, a portion where the cathode region 22a of diode _D1 is to be formed, and a portion where an n-type polysilicon wiring is to be formed are exposed.

Similarly, using the photoresist film and field oxide film as a mask, the source region, drain region, n-type semiconductor wiring region, and n-type polysilicon wiring of the n-channel MISFET were
Necessary n-type impurities are introduced by ion implantation.

After removing the photoresist film, the surface of the polysilicon layer is lightly oxidized.

Portions of the semiconductor substrate and the polysilicon layer to be used as contact regions are exposed by photo-etching.

An aluminum layer is formed by vapor deposition and then selectively etched.

In the embodiments of FIGS. 2 and 3 above, the resistance R ₃
A voltage is generated by the leakage current of the diode _D1 flowing through the diode D1. The voltage signal of this resistor R ₃ is
Output via n-channel type MISFETQ ₂₃ . The MISFETQ ₂₃ acts as an impedance conversion means.

Since the resistor R ₃ is formed at the same time as the resistors R ₁ and R ₂ of the memory cell as described above, the same variation in resistance value as that of the resistors R ₁ and R ₂ occurs. The reverse biased diode D ₁ produces a leakage current that varies approximately in accordance with a change in the drain leakage current of the off-state MISFET _{Q 1} or Q ₂ in the memory cell. Therefore, if the resistance values of the memory cell resistors R ₁ and _{R 2 are} increased, a large voltage drop will occur in the resistor R 3 and the power supply circuit 9
will output a relatively large level of voltage. That is, the resistance R ₁ in the memory cell,
The decrease in current due to the increase in the resistance value of R ₂ will be corrected by the increase in the power supply voltage.

Contrary to the above, if the resistance values of resistors R ₁ and R ₂ vary to a smaller value than the designed value, the current flowing through the MISFET that is turned on among MISFETs _{Q 1} and Q ₂ of the memory cell increases. However, in this case, by lowering the output voltage of the power supply circuit 9, the increase can be suppressed. Therefore, the current consumption can be reduced while ensuring the current for data retention in the memory cell despite variations in resistance value.

When the leakage current of the MISFET increases due to the temperature rise of the RAM, the voltage drop across the resistor _R3 increases due to an increase in the leakage current of the diode _D1 corresponding to the increase in the leakage current, and the voltage drop of the resistor R3 increases.
The output voltage level of will be increased. In this case, the current for holding data in the memory cell will be increased. As a result, the temperature margin of the memory cell can be expanded.

In addition, in FIG. 3, the polysilicon resistance layer 2
Although a p-type semiconductor region 21a which is brought to the ground potential is arranged below 5a, this can be omitted. However, the p-type semiconductor region 21a
If omitted, by maintaining the n-type semiconductor substrate 20 at the potential of the power supply terminal V _DD , the voltage from the n-type semiconductor substrate 20 is applied to the polysilicon resistance layer 25a via the field oxide film 24. A positive electric field will be applied. A polysilicon layer for forming the resistors R ₁ and R ₂ in the memory cell is disposed on a p-type semiconductor region (not shown) maintained at a ground potential via a field oxide film, and Considering that if the polysilicon layer forming R ₁ , R ₂ and R ₃ is made to have a significantly low impurity concentration, it will be relatively susceptible to the influence of an electric field. It is preferable that a semiconductor region maintained at a ground potential be disposed below.

FIG. 4 is a circuit diagram of a power supply circuit 9 according to another embodiment of the present invention.

In this embodiment, a resistor R ₄ is provided on the power supply voltage side, and a pn junction diode D ₂ reverse biased is provided on the ground potential side. Also, the voltage at the connection point between the resistor R ₄ and the diode D ₂ is p
Connected to the gate of channel type MISFETQ ₂₅ ,
The source of this MISFETQ ₂₄ is connected to the power supply voltage terminal V _DD . The output voltage is output from the drain of MISFETQ ₂₅ above.

FIG. 5 is a sectional view of the circuit element shown in FIG. 4 above. As shown in the figure, the resistor _R4 is constituted by a polysilicon layer 25c formed via a field oxide film 24 on a p-type semiconductor region (p-type well) 21d maintained at ground potential, and is a diode.
D ₂ is the p-type well 21d and the n-type semiconductor region 22 formed on the surface of the p-type well 21d.
d.

In the embodiments shown in FIGS. 4 and 5, the output is obtained from the drain of the MISFETQ ₂₅ as described above, and the MISFETQ ₂₅ operates as a current power supply means. Therefore, for example, if the resistance value of each of the above-mentioned resistors varies greatly with respect to the design value, the voltage between the gate and source of the MISFETQ ₂₅ will be increased, and therefore the MISFETQ 25 will be controlled to increase its drain current. It turns out. the result,
As in the embodiments described above, the operating voltage of the memory cell can be corrected to a desired value regardless of variations in resistance value and changes in the operating temperature of the memory cell.

FIG. 6 is a circuit diagram of a power supply circuit 9 showing another embodiment of the present invention. Power supply circuit 9 of this embodiment
It is considered that the method can also be applied to the case where a static RAM is configured with n-channel MISFETs as follows. That is, the reverse biased pn junction diode _D3 has its anode electrode connected to the ground potential terminal,
The voltage signal formed at the connection point between the resistor R ₅ and the diode D ₃ above is for driving the n-channel type.
The signal is supplied to the gate of an n-channel MISFETQ _{28 operating as a source follower via an inverting amplifier circuit composed of a MISFETQ 27 and} a depletion mode n-channel load MISFETQ ₂₆ . The cathode of the diode _D3 is formed simultaneously with the source and drain regions of the n-channel MISFET. Above diode
The anode of _D3 is shared with the base gate of the n-channel MISFET. As a result, a circuit composed only of n-channel MISFETs can be constructed without any increase in process.

Note that if the gain of the inverting amplifier circuit is set too large, the voltage obtained via MISFETQ ₂₈ will show digital changes. Therefore, in order to perform a linear correction operation, it is necessary to pay attention to the setting of the gain of the inverting amplifier circuit.

FIG. 7 is a circuit diagram of a power supply circuit 9 of another embodiment in which the current consumption in the inverting amplifier circuit of the circuit of the embodiment of FIG. 6 is reduced.

In this example, an inverting amplifier circuit is constructed.
MISFETQ ₂₉ and Q ₃₂ , which constitute a power switch, are provided in series with MISFETQ ₃₀ and Q ₃₁ , respectively. This power switch is periodically turned off by a pulse signal φ supplied from a suitable pulse source.

When the above power switch is off,
The gate potential of MISFETQ ₃₃ is held by the capacitance such as the gate capacitance present therein.

Therefore, a substantially constant voltage can be obtained regardless of whether the power switch is in the OFF state. Note that the power switch may be controlled to be turned on only when the memory is holding data, in other words, when the chip is not selected. In any case, by providing the power switch as described above, the power consumption of the power supply circuit 9 can be reduced.

Further, FIG. 8 shows a cross-sectional view of the structure of a reverse biased pn junction diode D and a resistor R, showing an embodiment of the present invention.

In this embodiment, a resistor R and a reverse diode D are configured by the polysilicon layer 825e. That is, by forming a polysilicon layer 25e on the field insulating film 24 formed on the surface of the substrate 20, and selectively setting a semiconductor impurity and its concentration in this polysilicon layer 25e, the above-mentioned resistance R and A diode D is formed.

The n ⁺ portion 25e ₁ is configured as an electrode or wiring to which the power supply voltage V _DD is applied, and the n ⁻ portion 25e ₁ is configured as a resistor R. And the n ⁺ part 25e ₂ is
The p part 52e ₃ is configured as the wiring connected to the gate of the MISFET and one electrode of the diode.
is configured as the other electrode of the diode.

This embodiment has the advantage that a diode in any direction can be formed regardless of the conductivity type of the substrate 20 by selecting semiconductor impurities. Therefore, if the conductivity types of the polysilicon layers in this embodiment are reversed, the resistor R ₃ and diode D ₁ in the embodiment circuit of FIG. 2 can be constructed.

Furthermore, FIG. 9 shows another preferred embodiment of the present invention.

In this example, the example circuit of FIG.
MISFETQ ₂₄ as a power switch
This corresponds to the one equipped with MISFETQ ₃₄ .

FIG. 10 is a circuit diagram of a power supply circuit 9 of still another embodiment.

In this embodiment, a detection circuit DT is configured by a resistor R ₉ and an n-channel type MISFETQ ₃₇ connected between the gate and source, and an inverting amplifier circuit is configured by a resistor R ₈ and an n-channel type MISFETQ ₃₅ . IV
is configured.

By connecting as shown, the above detection circuit DT
The output of the inverting amplifier circuit LV is supplied to the inverting amplifier circuit IV, and the output of the inverting amplifier circuit LV is returned to the detecting circuit DT via the n-channel MISFET Q ₃₆ of source follower operation. The output voltage is output from the source of MISFETQ ₃₆ above.

The above resistance R ₉ is the resistance R ₁ of the memory cell in FIG.
and R ₂ is made of a polysilicon layer.

When a pn junction diode is used as a leakage current forming element as in each of the above embodiments, it is similar to a MISFET in a memory cell.
Since it does not have a MISFET structure, it does not necessarily exhibit leakage current characteristics that correspond well to the leakage current characteristics of the MISFET described above.

On the other hand, the MISFETQ ₃₇ is structurally similar to the MISFET in the memory cell, and its gate potential is similar to the gate potential of the MISFET that is turned off in the memory cell. Since it is maintained at the ground potential, it exhibits leakage current characteristics similar to the drain leakage current characteristics of the MISFET in the above memory cell.

Therefore, by making the resistor R ₉ and the MISFETQ ₃₇ similar in structure to the resistance and drive MISFET in the memory cell, the detection circuit DT
The memory cells exhibit the same voltage characteristics.

According to this embodiment, due to the negative feedback operation of the circuit via the inverting amplifier circuit IV, the output voltage V _DD1 becomes
The output voltage of the detection circuit DT is controlled to a value slightly higher than the threshold voltage of the MISFET.

Therefore, according to this embodiment, a good operating voltage that compensates not only for variations in the resistance value of the polysilicon resistor and variations in the drain leakage current of the MISFET, but also for variations in the threshold voltage of the MISFET can be maintained in the memory cell. Can be given to drive MISFET.

FIG. 11 shows a circuit diagram of the power supply circuit 9 of another embodiment. In the power supply circuit of this example,
Resistor R ₁₂ and MISFETQ ₄₁ constitute a detection circuit similar to the circuit shown in FIG. 10 above.

An offset voltage corresponding to the voltage drop across the resistor ₁₁ is applied to the voltage V _DD1 outputted from the MISFETQ ₃₀ and supplied to the memory cell. As a result, the MISFET of the memory cell is turned off.
An offset voltage corresponding to the above-mentioned offset voltage is applied to the drain of the transistor. By applying the above-described offset voltage to the memory cell, it becomes less susceptible to the effects of noise and the like.

FIG. 12 shows a circuit diagram of a power supply circuit 9 of yet another embodiment. In this embodiment, a differential amplifier circuit DA as shown is used in place of the inverting amplifier circuit IV shown in FIG. 11.

One input terminal of the above differential amplifier circuit DA has
A reference voltage is provided from a bias circuit VR consisting of MISFETQ ₄₂ and diode-connected MISFETQ ₄₃ . The above reference voltage is set so that the conductance of the above MISFETQ ₄₂ is relatively small.
By making the conductance of MISFETQ ₄₃ relatively large, it is brought to a value close to the threshold voltage of the MISFET.

FIG. 13 shows a circuit diagram of a power supply circuit 9 of still another embodiment.

In this example, the resistor R ₁₉ and
MISFETQ ₅₁ constitutes a detection circuit DT similar to that of the previous embodiment, and a resistor R ₂₀ and MISFETQ ₅₂ having a similar configuration to this circuit DT constitutes an offset circuit OS. Also, MISFETQ ₄₈ ,
An amplifier circuit is constituted by Q ₄₉ , resistors R ₁₇ and R ₁₈ .

The voltage supplied to the memory cell is a p-channel type controlled by the above amplifier circuit.
Output from the drain of MISFETQ ₅₀ .

According to the circuits shown in FIGS. 10 to 12, source follower operation MISFETs _{Q 36} , Q ₃₉ ,
By using _Q46 , the maximum value of voltage V _DD1 is V _DD −V _th (however, V _DD is the power supply voltage supplied to the power supply terminal, and V _th is the threshold voltage of the above MISFET). ).

On the other hand, according to the circuit shown in FIG. 13, the voltage V _DD1 is output from the drain of the MISFETQ ₅₀ , so its maximum value is increased to approximately V _DD . Therefore, when the power supply circuit 9 of FIG. 13 is used, the temperature margin of the memory cell can be made larger than when the power supply circuit of each of the embodiments described above is used.

The invention is not limited to the examples. The power supply circuit as described above can be combined with an appropriate logic circuit including a load resistance element with a relatively high resistance value.

For example, in FIG. 14, X or Y in FIG.
A decoder circuit is shown that can replace the address decoder circuit.

The illustrated decoder circuits include first decoder circuits 2a ₁ and 2a ₂ that output intermediate term signals by receiving address signals, and a second decoder circuit that receives output signals of the first decoder circuits 2a ₁ and 2a ₂ . It is composed of a circuit 2a.

The first decoder circuits 2a ₁ and 2a ₂ are MISFETQ ₅₆ , which are controlled by high resistances R ₂₁ , R ₂₂ coupled to their respective output nodes and a control signal ″.
Contains _Q59 .

A compensated voltage V _DD2 is supplied to the power supply side terminals of the high resistances R ₂₁ and R ₂₂ from the power supply circuit as shown in each of the embodiments.

The said control signal "is converted into a chip select signal by suitable circuitry, e.g. as shown in FIG. 15C.
The above for a predetermined period of time immediately after CS is added.
It is changed to a level that turns on MISFETQ ₅₆ and Q ₅₉ .

Therefore, the signal at each output node of the first decoder circuits 2a ₁ and 2a ₂ is the chip selection signal.
Immediately after CS is added, MISFETQ ₅₆ and
Q ₅₉ is turned on and exhibits a relatively low load resistance characteristic, causing it to change at a relatively high rate. Above MISFETQ ₅₆ and
After Q ₅₉ is turned off, the signal level at each of the output nodes is held at the previous logic level by the holding current provided through the resistors R ₂₁ and R ₂₂ . Said first decoder circuit 2a ₁ and 2
In _a2 , when the MISFETs Q ₅₆ and Q ₅₉ are turned on, their operating current is relatively large, but only flows for a relatively short time. Therefore, the first decoder circuits 2a ₁ and 2a ₂ substantially have high speed characteristics and low power consumption characteristics.

By providing the first decoder circuit, the second decoder circuit 2a can reduce the number of circuit elements constituting it, and can be operated with a relatively small operating current. As a result, the first
The two-stage decoder circuit shown in Figure 4 reduces its overall power consumption to the first level without impairing its speed characteristics.
It is possible to lower the decoder circuit with a one-stage configuration as shown in the figure.

The second decoder circuit 2 on the semiconductor substrate
Although a needs to be arranged in correspondence with, for example, a word line of the memory array, there is no such need for the first decoder circuits 2a ₁ and 2a ₂ . Therefore, the decoder circuit as shown in FIG.
Particularly suitable for RAM.

In the present invention, the resistance stage in the detection circuit of the embodiment described above does not need to be a polysilicon layer. For example, even when the high resistance for maintaining node voltage is formed of a polysilicon layer, the resistors R ₉ , R _12, etc. may be resistors having a different configuration, for example, resistors using diffused resistors. In this case,
Although it is not possible to correct variations in the resistance value of polysilicon resistors, it responds to changes in leakage current, so it is possible to expand the temperature margin.

In addition to the static type memory cell described above, the present invention can be widely used in various logic circuits having high resistance for maintaining node voltages, such as dynamic logic circuits of address decoder circuits.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a static RAM to which the present invention is applied, FIG. 2 is a circuit diagram of a power supply circuit showing an embodiment of the present invention, and FIG.
The figure is a cross-sectional view of the circuit elements constituting the circuit of FIG. 2 above, and FIG. 4 is a circuit diagram of a power supply circuit of another embodiment.
FIG. 5 is a sectional view of elements constituting the circuit of FIG. 4, FIGS. 6 and 7 are sectional views of power supply circuits of other embodiments, and FIG. Cross-sectional view, Fig. 9, Fig. 10, Fig. 1
1, 12, and 13 are circuit diagrams of power supply circuits of other embodiments, FIG. 14 is a circuit diagram of an address decoder circuit, and FIG. 15 is a diagram of a control signal applied to the circuit of FIG. 14 above. It is a timing chart diagram. 1a to 1c...memory cells, 2a to 2b...X
Address decoder circuit, 3a-3b...Y address decoder circuit, 4...Column switch circuit, 5
... Bit line load circuit, 6 ... Readout circuit, 7
...Writing circuit, 8...Control circuit, 9...Power supply circuit, 10...External power supply.

Claims (1)

[Claims] 1. Gate and drain are mutually cross-connected. 2.
The power supply circuit includes a memory cell composed of two insulated gate field effect transistors and a resistance element connected to the drain of each insulated gate field effect transistor, and a power supply circuit that supplies voltage to the memory cell. a resistance element formed at the same time as the resistance element of the memory cell; and an active element connected in series with the resistance element and configured to have similar characteristics to the insulated gate field effect transistor when turned off. A semiconductor integrated circuit device comprising: outputting a voltage that is changed in a direction opposite to fluctuations in a voltage between terminals of the active element based on a voltage at a connection point between the resistive element and the active element. 2. The semiconductor integrated circuit device according to claim 1, wherein the active element is a PN junction element. 3. The semiconductor integrated circuit device according to claim 1, wherein the resistive element is constituted by a polycrystalline silicon layer formed on a semiconductor substrate with an insulating film interposed therebetween. 4. The semiconductor integrated circuit device according to claim 2, wherein the PN junction element has an insulated gate field effect transistor structure. 5. The semiconductor according to claim 1, wherein the power supply circuit includes an output insulated gate field effect transistor whose gate is connected to a connection point between the resistance element and the active element. Integrated circuit device.