JPH0157536B2 - - Google Patents

Description

[Detailed description of the invention]

Technical Field The present invention relates to a four-value output circuit that utilizes pack gate potentials formed in CMOS circuits, and more specifically, to obtain two levels between the _Vcc level and the _Vss level in an LSI chip. It is something. The present invention can be used as a four-value DA converter, particularly as a liquid crystal drive circuit. Prior Art Conventionally, when obtaining a multi-value output by digital-to-analog conversion inside an LSI, the multi-value output is obtained using a resistor ladder circuit. However, in order to obtain a multi-value output in a resistor ladder circuit, current must be kept flowing at all times, which is disadvantageous in terms of large power consumption. Furthermore, if the resistance is increased in order to reduce power consumption, even though the necessary potential can be obtained, there is a drawback that the ability to drive an external circuit is lost. OBJECT OF THE INVENTION The object of the present invention is to obtain a four-value output circuit that is substantially free from the above-mentioned drawbacks of the conventional technology. The purpose of the present invention is to obtain a four-value output circuit which can obtain four-value output without consuming power when there is no power, and which can have a sufficiently large driving capacity when a load is connected. Structure and operation of the invention In a CMOS circuit, the back gate of an N-channel transistor is normally fixed at _Vss . The N-channel transistor changes the _Vcc level to Poly-Si
When transferred by the gate, the gate potential is
If V _cc , the potential transferred by the N-channel transistor is output at a level of V _cc -V _th (N-ch). Here, V _th (N-ch) is the threshold increased by the substrate effect, that is, the effective threshold level of the N channel. Similarly, in a P channel transistor, V _cc in N channel
The same phenomenon can be explained by simply replacing V _ss with
By P channel transistor with substrate effect
When transferring the V _ss level, V _ss −V _th (P−
ch) level is output. The present invention utilizes the above phenomenon to obtain four values. A circuit according to the invention is shown in FIG. TR ₁ , TR ₃ ,
TR ₅ is an N-channel MOS transistor,
TR ₂ , TR ₄ , and TR ₆ are P-channel MOS transistors, and each N-channel transistor has its substrate connected to ground, that is, the low level V _ss (Figure 2A), and each P-channel transistor has its substrate connected to It is connected to the high potential side, ie, the _Vcc level (FIG. 2B). The P-channel transistor _TR6 on the high potential side has a source connected to _Vcc , a drain connected to the source of the P-channel transistor _TR2 , and a gate connected to the input B.
The source of the N-channel transistor _TR5 is connected to _Vcc , and the drain of the N-channel transistor TR5 is connected to Vcc.
The source and gate of TR ₂ are connected to input B, respectively. The source of the P-channel transistor TR ₂ is connected to the drain of TR ₆ and the drain of TR ₅ , respectively, and the drain is connected to the drain of the N-channel transistor TR ₁ , and the gate is connected to the input terminal A, respectively. The gate of the N-channel transistor TR ₁ is connected to the input terminal A, its source is connected to the drains of the N-channel transistor TR ₃ and the P-channel MOS transistor TR ₄ on the ground side, and the sources of each of the transistors TR ₃ and TR ₄ are connected to the ground side. Both are connected to the ground _Vss level, and the gates of each transistor TR ₃ and TR ₄ are connected to input B. The output Y is taken out from the drain of the P channel transistor _TR2 and the drain of the N channel transistor _TR1 . To explain the correspondence between the above circuit and 4-level output, in order to output 4-level levels, from the _Vcc side,
In order to output the level of _Vcc , a P channel transistor _TR6 is required. This is because the source level of TR ₆ and the board level are _Vcc , so the output
V _cc is output from Yo. the next level is
V _cc −V _th (N-ch), and when the N-channel transistor TR ₅ is selected, the substrate is at the ground V _ss level and the source is at V _cc , so it is back gated and the N-channel transistor is The threshold value or effective threshold value V _th (N-ch) increases, and a potential of V _cc −V _th (N-ch) is obtained at the output Y. Conversely, from the ground level _Vss side, in order to output ground level _Vss , an N-channel transistor whose source level and substrate level are the same is required.
TR ₃ is required, and in order to output a potential different from V _ss , a P with different source level and substrate potential is required.
Channel transistor TR ₄ is required. Actually, the substrate potential of P-channel transistor TR ₄ is V _cc
Since the source level is set to the ground V _ss , an effective threshold value that does not have the substrate effect of V _th (P-ch) and whose potential is shifted by V _th due to the V _th plus substrate effect occurs. to result output Y
V _ss −V _th (P-ch) is output. In the circuit of the present invention, these four values are V _cc , V _cc −V _th (N-ch),
V _ss -V _th (P-ch) and V _ss can be obtained from two signal lines, input A and input B. Next, the operation of the circuit shown in FIG. 1 will be explained in relation to input A and input B. The correspondence between input A, input B, and output Y is as shown in the following table.

[Table] (1) When A=0, B=0 When the input of A is 0 (V _ss ), it becomes an ON signal for the P channel transistor and an OFF signal for the N channel transistor. TR ₂ is ON, TR ₁
is turned OFF, so the effect or potential of either transistor TR ₅ or TR ₆ is output to the output Y by TR ₂ . Since the input of B is 0, the P channel transistor TR ₆ is ON, the N channel transistor TR ₅ is OFF, and the _Vcc level is output. (2) When A=0, B=1 Since A=0, TR ₂ is ON and TR ₁ is the same as in (1).
is OFF and B=1 (V _cc ), so the N-channel transistor TR ₅ is ON and the P-channel transistor TR ₆ is OFF, and the threshold level has changed due to the substrate effect due to TR _{5.V th} − The potential lowered from V _cc by the N _ch potential is transmitted by TR ₂ and obtained as output Y. (3) When A=1, B=0 When A=1 (V _cc ), TR ₁ is ON and TR ₂ is OFF, so the potential obtained by TR ₃ or TR ₄ is the N channel of TR _1. Output by a transistor. B
= 0, so TR ₃ (N channel) is OFF,
TR ₄ (P channel) is ON, and the potential raised from the _Vss level by the amount that the effective threshold level has changed due to the substrate effect of the P channel transistor in TR ₄ is the N channel of TR ₁ . It is supplied to output Y through a transistor. (4) When A=1, B=1 Since A=(V _cc ), TR ₁ is ON as in (3).
Since TR ₂ is OFF and B=1, TR ₃ (N channel) is ON and TR ₄ (P channel) is OFF.
The _Vss level is directly output to the output Y. The present invention has been explained above using one embodiment, but
The present invention can also be modified as shown in FIG. Third
The figure differs from FIG. 1 in that TR ₁ and TR ₂ are placed outside, ie, on the V _ss side and V _cc side, respectively, but the operation of the circuit is similar to the circuit in FIG. 1. Furthermore, a modification as shown in FIG. 4 is also possible. In the figure, TR ₃ and TR ₄ are not commonly connected to V _ss through the transistor TR ₁ as in FIG _.
and connected to the V _ss level via TR ₇ .
Note that a similar modification is possible on the _Vcc side as well. Effects of the Invention According to the present invention, there is sufficient driving capacity for the four levels obtained, and the power required to obtain each level is only used at the moment when one of the four levels is selected, that is, each transistor is turned ON-OFF and OFF-ON. If there is no external load, no current is actually consumed. For example, when connecting the output Y to the gate of the next transistor, almost no power is consumed. On the other hand, if the size of the transistor itself is considered, it is possible to provide any amount of external driving capability.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of one embodiment of a four-value output circuit using the CMOS process of the present invention, FIGS.
The figure is a circuit diagram of another embodiment of the invention, and FIG. 4 is a circuit diagram of still another embodiment of the invention. (Main signs), A, B...input, Y...output, TR ₁ ,
TR ₃ , TR ₅ ...N channel MOS transistor,
TR ₂ , TR ₄ , TR ₆ ... P-channel MOS transistor, V _cc ... Potential on the high potential side, V _ss ... Potential on the low potential side (ground).

Claims (1)

[Claims] 1. First and second P-channel MOS transistors TR2 and TR6 connected in series between an output terminal Y that outputs a 4-value signal and a high potential side power supply line Vcc; and the output terminal Y. first and second N-channel MOS transistors TR1 and TR3 connected in series between the power supply line VSS and the low-potential side power supply line Vss; and the second P-channel MOS transistor TR6.
a third N-channel MOS transistor TR5 connected in parallel with the second N-channel MOS transistor TR3;
and a third P-channel MOS transistor TR4 connected in parallel with the first P-channel MOS transistor TR2.
and first N-channel MOS transistor TR1
each receives a first binary input, A, at its gate; receives a second binary input B, and in response to the first and second binary inputs A and B,
the first and second P-channel MOS transistors;
The first level is output via TR2 and TR6,
the first P-channel MOS transistor TR2 and the third N-channel MOS transistor TR5
A second level is outputted through the first and second levels.
A third level is outputted through the N-channel MOS transistors TR1 and TR3, and a fourth level is outputted through the second N-channel MOS transistor TR1 and the third P-channel MOS transistor TR4. 4-value output circuit. 2 The first P-channel MOS transistor TR
2 and the first N-channel MOS transistor
The drains of TR1 are each connected to the output terminal Y, and the second P-channel MOS transistor TR6
The source of
2. The four-value output circuit according to claim 1, wherein a source of the N-channel MOS transistor TR3 is connected to the low potential side power supply line Vss. 3 Said second P-channel MOS transistor TR
6 and the second N-channel MOS transistor
The drains of TR3 are each connected to the output terminal Y, and the first P-channel MOS transistor TR2
The source of
2. The four-value output circuit according to claim 1, wherein the source of the N-channel MOS transistor TR1 is connected to the low potential side power supply line Vss. 4. First and second P-channel MOS transistors TR2 and TR6 connected in series between the output terminal Y that outputs a four-value signal and the high potential side power supply line Vcc, and the output terminal Y and the low potential side power supply line first and second N-channel MOS transistors TR1 and TR3 connected in series between the output terminal Y and the low potential side power supply line Vss; and a third N-channel MOS transistor connected in series between the output terminal Y and the low potential side power supply line Vss. TR7 and third P-channel MOS transistor
TR4, and the second P-channel MOS transistor TR6.
and a fourth N-channel MOS transistor TR5 connected in parallel with the first P-channel MOS transistor TR.
2. The first N-channel MOS transistor TR
1. The third N-channel MOS transistor TR
7 receives the first binary input A at its gate, and the second and third P-channel MOS transistors TR6, TR4 and the second and fourth N-channel MOS transistors TR3, TR5 each receive the first binary input A at their gates. receiving a second binary input B; in response to the first and second binary inputs A and B;
the first and second P-channel MOS transistors;
The first level is output via TR2 and TR6,
the first P-channel MOS transistor TR2 and the fourth N-channel MOS transistor TR5
A second level is outputted through the first and second levels.
A third level is outputted through the N-channel MOS transistors TR1 and TR3, and a fourth level is outputted through the third N-channel MOS transistor TR7 and the third P-channel MOS transistor TR4. 4-value output circuit.