JPH0158592B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory device using a shot gate type field effect transistor (hereinafter abbreviated as shot FET).

In recent years, GaAs crystals have been developed as three-terminal active devices that surpass the operating speed of bipolar transistors.
MES (Metal Semiconductor) FETs have attracted attention, and GaAs integrated circuits that integrate these FETs are being actively prototyped.

The present invention uses a normally-off type stopper FET in the memory cell and a normally-on type stopper FET in the peripheral circuit, so that high-speed signals generated in the peripheral circuit are efficiently supplied to the cell array.

A circuit using a normally-on type shotgun FET and a circuit using a normally-off type shotgun FET have different power supply voltages and signal amplitudes, and when they are integrated on the same substrate, they cannot be directly coupled. Furthermore, when driving a large-area cell array, it is necessary to suppress the potential difference between both ends of the cell array as much as possible. According to the present invention, by directly connecting the two using a level clamp diode and specifying the position where it is added, a semiconductor memory device can be obtained in which the potential difference within the array is suppressed as much as possible.

In a semiconductor memory, memory cells are arranged in a matrix, and around them are arranged circuits for selecting cells, circuits for driving selected cells, circuits for amplifying read signals from the cells, and the like. FIG. 1 shows a schematic diagram of a semiconductor memory. This figure shows the arrangement of each circuit in a chip of a semiconductor memory integrated circuit device. In the figure, 100 is a cell array in which memory cells are arranged in a matrix, and 101 is a column of the cell array 100 supplied from the outside. a signal conversion circuit that converts the signal for selecting the direction into a chip internal signal;
102 is a column selection circuit that selects one column in the column direction of the cell array according to the output signal of the signal conversion circuit 101; 103 is a column selection circuit that selects a memory cell connected in the column direction selected by the column selection circuit 120; This is a drive circuit for driving. In addition, in the figure, the circle indicated in the cell array 100, for example, 10
8 means a memory cell, and a line in the column direction, for example 109, is a column line for sending a drive signal from the drive circuit 103 to a selected cell. When a cell drive signal is applied to a selected column line, signals are read out from all memory cells connected to that column line and supplied to the signal amplification circuit 104 through a row line such as 110 in the row direction. be done. The read signal amplified by the signal amplifier 104 is sent to the row selection circuit 1
05, and only the read signal corresponding to one row line is outputted to the outside of the chip through the output buffer 107. Also, 106
A signal conversion circuit converts a signal for selecting the row direction of the cell array supplied from the outside into a chip internal signal, and its output is supplied to the row selection circuit 105. The above is a simple explanation of the read operation, but for the write operation, the column line and row line selection operations are the same, and the write information is supplied only to the selected row line, and the information is written to the memory cell. It's starting to become easier. Note that the signal conversion circuit 106 receives write signals inside the chip, corresponding to signals supplied from outside the chip,
Also included is circuitry for generating write information signals.

The reading and writing operations of semiconductor memory have been briefly described above, but when it comes to memory cells, it is important to integrate a large number of them on a chip.
It is necessary to make the circuit as simple as possible and occupy as little space as possible. For this purpose, it is effective to use a normally-off type shotgun FET that does not require a level shift circuit and has a simple circuit configuration. on the other hand,
The circuit that drives the large number of memory cells connected to each column line drives the large load capacitance associated with the column line, so even if there are multiple circuits to some extent, an element that can flow a large current is required. It is effective to use a normally-on type shotgun FET. Figure 2 shows a cross-sectional view of a normally-off type shotgun FET.
Figure 3 shows a cross-sectional view of a normally-on type shotgun FET. In FIG. 2, 200 is a GaAs semi-insulating substrate, 201 is a heavily doped N-type ion-implanted layer for the source and drain portions, and 202 is a lightly-doped N-type ion-implanted layer for the channel forming portion. 203 is a shot gate electrode made of a metal group (for example, Al) that makes shot contact with the N-type ion implantation layer 202.
etc.) to form a pattern. Reference numeral 204 indicates a drain electrode, and reference numeral 205 indicates a source electrode, both of which are patterned with a metal group (for example, an Au-Ge alloy) to make resistive contact with the N-type ion-implanted layer 201. In this type of device, the depletion layer 206 that spreads under the gate electrode is caused by the gate voltage.
The FET expands and contracts vertically, which changes the current flowing between the drain and source.
An action is taken. Since the device shown in FIG. 2 is a normally-off type short-circuit FET, when the gate voltage is zero, the depletion layer 206 reaches the lower end of the channel forming portion 202, and no current flows between the drain and source. The gate voltage at which current begins to flow between the drain and source is called the threshold voltage _VT , and in the case of a normally-off type short-circuit FET, this value is approximately
It is 0.1V. When the gate voltage is a positive voltage equal to or higher than the threshold voltage V _T , the depletion layer 206 contracts and current flows between the drain and source. on the other hand,
Normally-on type shotgun FET in Figure 3
300 GaAs semi-insulating substrate, 301 high concentration N type ion implantation layer, 303 gate electrode, 3
The drain electrode 04 and the source electrode 305 are the same as those of the normally-off type shotgun FET, but the thickness of the low concentration N-type ion implantation layer 302 is thicker than that of the normally-off type shotgun FET. Therefore, even when the gate voltage is zero, current flows between the drain and source, and the current stops flowing only when the gate voltage becomes negative. The threshold voltage V _T of a normally-on type shotgun FET is normally used at a value of -1.0 to -2.0V. Comparing the drain-source current of a normally-off type FET and a normally-on type FET with the same element dimensions and the same gate voltage, the latter allows several times larger current to flow.

Figure 4 shows an example of a memory cell circuit using a normally-off type short-circuit FET. This type of FET does not require a level shift circuit and can be configured by directly connecting FETs, so it requires fewer elements. You can configure a circuit with In Figure 4,
400 is a word line, and 401 and 402 are data lines. The column lines explained in FIG. 1 correspond to the word lines 400 in this figure, and the row lines correspond to the data lines 401 and 40.
Corresponds to 2. In FIG. 1, one row line is shown for each cell, but in reality, a pair of data lines constitutes a data line as shown in FIG. 403,
404 is resistance, 405, 406, 407, 408
is a normally-off type shotgun FET. FET
The sources of 406 and 407 are commonly grounded, and the drains are connected to the power supply through resistors 403 and 404, respectively.
V _C (for example, +0.5V), and its gates are connected to opposite nodes 410 and 409, respectively, to form a flip-flop circuit. Also,
The drains of FETs 405 and 408 are connected to data lines 401 and 402, respectively, the sources are connected to nodes 409 and 410, respectively, and the gates are connected to word line 400. Here, FET
The respective resistance values are selected so that one of 406 and 407 is on and the other is off, and in the case of two cases where FET 406 is on and FET 407 is off, or FET 406 is off and FET 407 is on. Binary information “0”, “1” corresponding to
is memorized. When a drive signal is applied to the word line 400, FETs 405 and 408 are turned on, and
A storage signal is read out onto the data line. A write operation is performed by applying a drive signal to the word line 400.
After turning on FET405 and 408, the data line,
This is done by lowering the potential of either 401 or 402. Normally off type like this
The amplitude of the word line signal for driving memory cells using FETs is limited by the FET threshold voltage V _T and the forward characteristics of the shot gate, and is approximately 0.6V.
That's about it. This restriction will be explained in more detail below. Assume that the FET 406 is on, the FET 407 is off, and information "0" is stored in the cell. At this time, node 409 is at approximately ground potential, while node 410 is at approximately 0.5 to 0.6V.
When the cell is not selected, nodes 409 and 410
Since the FETs 405 and 408 must be electrically isolated from the data lines 401 and 402, the FETs 405 and 408 must be turned off. Therefore,
It is necessary to maintain the voltage of the word line 400 at about the potential of the node 409, that is, the ground potential.
Next, when the cell becomes selected and performs a read operation, the potential of the word line 400 rises and the FET
405 and 408 are turned on, but the word line voltage cannot be increased indefinitely. The reason for this is that in FETs using Schottki gates,
Since the gate electrode, source electrode, and drain electrode constitute a Schottky diode, when the gate voltage is approximately 0.6V higher than the source or drain voltage, the gate to source,
Alternatively, this is because current begins to flow to the drain electrode. Consider this situation using the cell in Figure 4.
Assuming that information "0" is currently stored in the cell, the node 409 is almost at ground potential, so
When the potential of the word line 400 reaches approximately 0.6V, a current begins to flow from the word line 400 toward the node 409, and as the potential of the word line 400 further increases, the potential of the node 409 begins to increase, and finally, Nodes 409 and 410 have the same potential, causing information destruction. Furthermore, a phenomenon similar to that during reading may occur during writing as well. Therefore, when the cell is in a non-selected state, the signal amplitude of the word line 400 must be kept to about 0.6V in order to maintain the stored information in the cell and not destroy the stored information during reading and writing. I understand that.

Next, the word line drive circuit will be described. As mentioned above, it is efficient to use a normally-on type shotgun FET in this drive circuit, and an example thereof is shown in FIG. Figure a is
It is generally called SDFL ( Schotky Diode FET Logic ). In the figure, 500 is an input terminal, 501 is an output terminal, 502, 503 are diodes, 504, 505, 506 are normally-on type shotgun FETs, FET 504 is a level shift circuit, and FETs 505, 506 control the output potential. It is for the purpose of Input terminal 5
00 is the anode of the diode 502, the cathode of the diode 502 is the anode of the diode 503, and the cathode of the diode 502 is the anode of the diode 502.
The drain of FET504 is connected, and FET504
The gate and source of are commonly connected to the power supply _Vs to form a level shift circuit. Furthermore, the cathode of the diode 503 is connected to the gate of the FET 506, and the drain of the FET 506 is connected to the FET 50.
Commonly connected to the source and gate of 5,
It is connected to the output terminal 501. FET505
The drain of FET 506 is connected to the power supply V _D , and the source of FET 506 is grounded. In this way, this circuit is
Compared to a circuit using a normally-off type short-circuit FET, an extra level shift circuit is required, and the circuit configuration is accordingly more complicated. In this circuit, V _D is 2V, V _s is -1.5V, and the threshold voltage V _T of the normally-on type shotgun FET is -
1V is commonly used. The output of this circuit is
Since it changes from approximately ground potential to V _D potential,
The signal amplitude will also be approximately 2V. The input terminal 500 has
A signal with the same potential as the output terminal 501 is input, and the potential is lowered by about 1.2V by the diodes 502 and 503. Therefore, the FET 506 turns off and on in response to the input signal "L" and "H", and the output potential also becomes "H".
(2V) to “L” (approximately 0V). In this case, the way the input signal and output signal change are exactly opposite. Note that in the circuit of Figure 5a, the FET
Even if 504 is replaced with a resistor, the operation is essentially the same. The circuit shown in FIG. 5b is a push-pull version of the circuit shown in FIG. 5a to further reduce the power consumption. Input terminal is 510, output terminal is 51
1, and 512 is an inverter for inverting the input signal. Diodes 513, 514, 51
5,516, FET517, 518 operations are almost the same as in case a, but FET519,520
Since only one of them is always on, it is suitable for low power consumption. Note that in the circuit b, the connections are such that the input and output change directions are in the same direction. However, the output amplitude of circuit a is approximately
Since the output amplitude of the 2V,b circuit is approximately 1.5V, it is not possible to directly connect the memory cells mentioned above to these peripheral circuits, and some kind of contrivance is required. 6th
In the figure, a level clamp diode 706 is inserted at the boundary between a cell array 700 and a column line drive circuit 705. With this circuit configuration, the output level of the drive circuit 705 is clamped at the signal voltage of approximately 0.6V allowed by the memory cell, and at the same time, it is clamped within the range where the output waveform rises quickly, so that high-speed signals can be can be supplied to the selected column line. Furthermore, by using a clamping diode at the boundary between the cell array and the drive circuit, the potentials at the near and far ends of the column line, for example, the column line 701, when selected, can be kept constant. Stable operation of the memory cell becomes possible. Now, if the column line 701 is in the selected state, the potential of the column line 708 becomes "H" level,
FET709 is on, FET710 is off,
The on/off relationship of these FETs is reversed, and the column line 7
The potential of 01 begins to rise. Then, as mentioned earlier, when the voltage reaches about 0.6V, the diode 70
6 operates and the waveform is clamped. At this time,
A steady current flows from the FET 709 to the diode 706 to the ground, but by placing the diode 706 at the boundary between the cell array 700 and the driving circuit 705, this steady current can flow without passing through the column line 701. As a result, during selection, the potential can be kept constant at the near and far ends of the column line, allowing stable operation of the memory cell.

As mentioned above, we have developed a circuit configuration in which a normally-off type stopper FET is used for the static memory cell, a normally-on type stopper FET is used for the column line drive circuit, and a clamping diode is placed at the boundary between the two. By doing so, it is possible to realize a highly integrated, high-speed, and stable semiconductor memory device.

FIG. 7 shows signal waveforms in the circuit of FIG. 6. A shows the signal waveform input to the terminal 708. When the column line 701 is selected, the signal level increases from approximately 0V to 2V, and as a result, the potential of the column line begins to rise. b shows this situation, where the solid line is the waveform in the circuit diagram of FIG. 6, and the broken line is the waveform when the clamping diode 706 is not provided. As you can see from this waveform,
The amplitude of the column line is suppressed within the permissible signal amplitude of the memory cell, and the rise of the output signal of the drive circuit is also fast. Although the rise portion of the column line has not been described, in the drive circuit shown in FIG. 5, the fall time is considerably shorter than the rise time, and is not as problematic as the rise time.

Although one embodiment of the present invention has been described above,
The present invention is effective not only for memory devices using compound semiconductor GaAs, but also for Si memory devices using shotgun gate type FETs. Further, a substrate other than a semi-insulating GaAs substrate, for example a GaAs or Si semiconductor memory device using epitaxial crystal, may be used. Furthermore, it may be a Si semiconductor memory device using an SOS crystal.
Furthermore, although the level shift circuit in the circuit shown in FIG. 5 is constructed of diodes and FETs, the level shift circuit may be constructed using other circuit configurations. For example, as shown in FIG. 8a, a level shift circuit including a diode, a FET, and a capacitor is preferably used in the present invention. Note that the operation is essentially the same even in a circuit in which the FET 804 in FIG. 8a is replaced with a resistor. In the figure, the capacitor 803 operates as a coupling capacitor, and the input signal 803
This is added in order to discharge the potential of node 808 at high speed when the voltage falls. Further, the diodes 801, 802 and the FET 804 are provided to fix the potential of the node 808 to a constant value when the input signal reaches a steady state. Furthermore, when the input signal rises, the potential of the node 808 changes rapidly to the High level due to both the transient current flowing through the capacitor 803 and the direct current flowing through the diodes 801 and 802. Since this circuit can reduce the DC current of the level shift section, it can be said that it is suitable for driving a high load with lower power consumption than the SDFL circuit shown in FIG. 5a.

The circuit shown in FIG. 8b has a push-pull configuration based on the circuit shown in FIG. Same as in case. This circuit can be used as is as the column line drive circuit 705 in FIG. 6, and can achieve lower power consumption and higher speed operation than the circuit shown in FIG. 5b. In addition, in FIG. 8, FET804, 805, 806, 815, 8
Of course, 17, 816, 821, 823, and 824 are normally-on type shotgun FETs.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram showing the arrangement of circuits within a chip in a semiconductor memory device, FIGS. 2 and 3 are cross-sectional views showing the configuration of a GaAs shot gate type field effect transistor, and FIG. FIGS. 5a and 5b are circuit diagrams showing an example of a memory cell used in the invention, and FIG. 6 is a circuit diagram showing an example of a memory cell drive circuit used in the invention, respectively.
FIG. 7 is a circuit diagram showing a main part of an embodiment of the present invention, FIG. 7 is a diagram showing signal waveforms in the circuit of FIG. 6, and FIGS. FIG. 7 is a circuit diagram showing another example. 400...word line (column line), 401, 402
...Data line (row line), 405, 406, 407,
408... Normally-off shot gate type FET, 502, 503, 513, 514, 5
15,516,801,802,812,81
3,818,819...Diode, 504,5
05,506,517,518,519,52
0,804,805,806,815,816,
821, 823, 824... Normally-on shot gate type FET, 512... Inverter, 706... Level clamp diode, 8
14,820...capacity.

Claims (1)

[Claims] 1. A memory cell array in which static memory cells using normally-off shot gate field effect transistors are arranged in a matrix, and a common connection to the memory cells arranged in each column of the cell array. 1. A semiconductor memory device comprising: a plurality of word lines, and a plurality of drive circuits that supply drive signals to the word lines using normally-on shot gate field effect transistors. 2. The semiconductor memory device according to claim 1, further comprising a level clamp diode provided at each boundary between the plurality of word lines and the plurality of drive circuits.