JPH0158673B2 - - Google Patents
Info
- Publication number
- JPH0158673B2 JPH0158673B2 JP56137562A JP13756281A JPH0158673B2 JP H0158673 B2 JPH0158673 B2 JP H0158673B2 JP 56137562 A JP56137562 A JP 56137562A JP 13756281 A JP13756281 A JP 13756281A JP H0158673 B2 JPH0158673 B2 JP H0158673B2
- Authority
- JP
- Japan
- Prior art keywords
- diaphragm
- semiconductor
- thin film
- groove
- mounting base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D48/00—Individual devices not covered by groups H10D1/00 - H10D44/00
- H10D48/50—Devices controlled by mechanical forces, e.g. pressure
Landscapes
- Measuring Fluid Pressure (AREA)
- Pressure Sensors (AREA)
Description
【発明の詳細な説明】
この発明は圧力・差圧・絶対圧などを測定する
機器において検出素子として使用される半導体ダ
イヤフラムの改良に関する。半導体ダイヤフラム
上にピエゾ抵抗素子を形成したものを検出素子と
して用いる圧力・差圧・絶対圧などの測定器は今
年多見されるものであるが、その性能達成上殊に
難点とされるのは、ピエゾ抵抗係数の温度変化に
起因する測定スパンの温度変化、周囲温度変化に
よつて半導体ダイヤフラムに加わる歪応力に起因
するゼロ点の温度ドリフトなどである。本発明
は、上記のゼロ点の温度ドリフトの改良にかかる
もので、半導体ダイヤフラムとそれが取り付けら
れる取付台及び取り付けのための接合層などとの
熱膨張係数の差によつて薄膜ダイヤフラムに加わ
る熱歪の影響を減少することを目的とする。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improvements in semiconductor diaphragms used as detection elements in devices that measure pressure, differential pressure, absolute pressure, and the like. Measuring instruments for pressure, differential pressure, absolute pressure, etc. that use a piezoresistive element formed on a semiconductor diaphragm as a detection element are becoming more common this year, but there are particular difficulties in achieving their performance. , a temperature change in the measurement span due to a temperature change in the piezoresistance coefficient, and a temperature drift at the zero point due to strain stress applied to the semiconductor diaphragm due to a change in ambient temperature. The present invention relates to improving the temperature drift at the zero point described above, and the heat applied to the thin film diaphragm due to the difference in thermal expansion coefficient between the semiconductor diaphragm and the mount to which it is attached and the bonding layer for attachment. The purpose is to reduce the effects of distortion.
上記目的を達成するための従来の提案として、
特開昭54―99585号公報に開示のものがある。こ
れは圧力・差圧・絶対圧計などの受圧部を構成す
る部材から検出素子である半導体ダイヤフラムに
加わる歪応力を減らすために特殊な構造を採用し
た取付台を用いるものであるが、その取付台の構
造が複雑なため製造上難点があると共に、歪応力
の伝達を完全にはなくしえないなどの欠点があ
る。また他の従来の提案として、特開昭54―
143275号公報に開示のものがあり、これは半導体
ダイヤフラムと同じ素材からなる取付台を用いる
ことにより、取付台と半導体ダイヤフラムの熱膨
張係数の差による熱歪応力の発生を防止すること
を目的とし、取付台に溝を形設することにより、
この目的をより完全に達成しようとするものであ
る。しかし、上記いずれの提案のものも半導体ダ
イヤフラム自身は何ら歪を吸収する手段を有して
おらず、半導体ダイヤフラムと取付台を一体化す
るための接合層が起歪部として発生する歪応力を
吸収することはできないという難点がある。半導
体ダイヤフラムと取付台を一体化するための方法
としては、合成樹脂による接着、低融点ガラスに
よる接合、金―シリコンの共晶合金による接合、
陽極接合法、金属ソルダー層による接合など種々
の方法が既に提案・実用化されているが、上記い
ずれの方法を用いても、接合層には接合時に発生
した歪応力が残ると共に、半導体ダイヤフラムと
接合層や取付台の熱膨張係数を完全には一致させ
ることはできないために熱歪応力が薄膜ダイヤフ
ラムに加わることはまぬがれ得ない。 As a conventional proposal to achieve the above purpose,
There is a disclosure in Japanese Patent Application Laid-open No. 54-99585. This uses a mounting base with a special structure to reduce the strain stress applied from the members that make up the pressure receiving part of pressure, differential pressure, and absolute pressure gauges to the semiconductor diaphragm that is the detection element. It has a complicated structure, which makes it difficult to manufacture, and it also has drawbacks such as the fact that it cannot completely eliminate the transmission of strain stress. In addition, as another conventional proposal,
There is a method disclosed in Publication No. 143275, which aims to prevent the occurrence of thermal strain stress due to the difference in thermal expansion coefficient between the mounting base and the semiconductor diaphragm by using a mounting base made of the same material as the semiconductor diaphragm. , by forming a groove in the mounting base,
It seeks to achieve this objective more fully. However, in any of the above proposals, the semiconductor diaphragm itself does not have any means to absorb strain, and the bonding layer for integrating the semiconductor diaphragm and the mounting base absorbs the strain stress generated as a strain-generating part. The problem is that it cannot be done. Methods for integrating the semiconductor diaphragm and the mounting base include bonding with synthetic resin, bonding with low melting point glass, bonding with gold-silicon eutectic alloy,
Various methods have already been proposed and put into practical use, such as anodic bonding and bonding using a metal solder layer, but no matter which method is used, the strain stress generated during bonding remains in the bonding layer, and the semiconductor diaphragm and Since the thermal expansion coefficients of the bonding layer and the mounting base cannot be made to match perfectly, it is inevitable that thermal strain stress will be applied to the thin film diaphragm.
この発明は、この悪影響をとり除き、周囲温度
変化に対して安定に動作する。すなわち熱歪応力
が薄膜ダイヤフラムに加わることの無い半導体ダ
イヤフラムを提供するものであり、圧力・差圧・
絶対圧計等に好適に使用される。 The present invention eliminates this adverse effect and operates stably against changes in ambient temperature. In other words, it provides a semiconductor diaphragm in which thermal strain stress is not applied to the thin film diaphragm, and it is capable of handling pressure, differential pressure,
Suitable for use in absolute pressure gauges, etc.
すなわち、この発明の半導体ダイヤフラムは、
半導体単結晶の板状チツプの下面中央部を上面へ
向けて凹ませて中央部を薄肉にしてその中央部を
薄膜ダイヤフラムとすると共に、その周囲の比較
的厚肉の部分を周辺固定部とし、さらにその周辺
固定部に前記薄膜ダイヤフラムを取り囲むように
応力吸収の為の細く深い溝を形成して構成された
ものである。この半導体ダイヤフラムは、取付台
から接合層を介してあるいは接合層自体から半導
体ダイヤフラムの周辺固定部に加わる歪応力が薄
膜ダイヤフラムへと伝わるのを、細く深い溝を設
けることにより防止することができるので、半導
体ダイヤフラムとの熱膨張係数の一致、歪応力の
伝達防止などを考慮した特別な取付台を必要とせ
ず、半導体ダイヤフラムと取付台の接合の手法も
容易で広い温度範囲にわたつて安定に動作しうる
ものである。 That is, the semiconductor diaphragm of this invention is
The central part of the lower surface of a semiconductor single crystal plate chip is recessed toward the upper surface, the central part is made thin, and the central part is used as a thin film diaphragm, and the relatively thick part around it is used as a peripheral fixing part, Further, a narrow and deep groove for absorbing stress is formed in the peripheral fixing portion so as to surround the thin film diaphragm. This semiconductor diaphragm can prevent the strain stress applied to the peripheral fixing part of the semiconductor diaphragm from being transmitted from the mounting base through the bonding layer or from the bonding layer itself to the thin film diaphragm by providing a narrow and deep groove. , does not require a special mount that takes into consideration the matching of the coefficient of thermal expansion with the semiconductor diaphragm and the prevention of transmission of strain stress, and the method of joining the semiconductor diaphragm and mount is easy and operates stably over a wide temperature range. It is possible.
以下、図に示す実施例に基いて、この発明を詳
説する。 Hereinafter, this invention will be explained in detail based on embodiments shown in the drawings.
第1図に示す1は、この発明の半導体ダイヤフ
ラムの一実施例であるシリコンダイヤフラムであ
る。 Reference numeral 1 shown in FIG. 1 is a silicon diaphragm which is an embodiment of the semiconductor diaphragm of the present invention.
このシリコンダイヤフラム1は、110面を有
するシリコン単結晶で概略7mm×7mm×200μmの
正方形の板状チツプの下面中央部2を電解エツチ
ング等により削除して、その中央部に厚さ+数
μmの薄膜ダイヤフラム3を円形に形成したもの
である。円形の直径は2〜3mmである。 This silicon diaphragm 1 is made of a silicon single crystal with 110 planes, and is made by removing the center part 2 of the lower surface of a square plate-shaped chip approximately 7 mm x 7 mm x 200 μm by electrolytic etching, etc., and adding a thickness of several μm to the center. The thin film diaphragm 3 is formed into a circular shape. The diameter of the circle is 2-3 mm.
薄膜ダイヤフラム3の周囲の厚さ200μmの部分
は周辺固定部4である。 A 200 μm thick portion around the thin film diaphragm 3 is a peripheral fixing portion 4 .
薄膜ダイヤフラム3を取り囲むように周辺固定
部4に形設された溝は歪応力吸収のための細く深
い溝6であり、周辺固定部4の下面5に開口して
おり、それら開口6a,6b,6c,6dは四辺
形をなしている。そしてその四辺形の辺をなす開
口の長手方向はいずれも<112>軸方向を向い
ている。開口の幅は数μmから数十μmで、溝の深
さは周辺固定部4の厚みの概略80〜90%すなわち
約160〜180μmである。 The groove formed in the peripheral fixing part 4 so as to surround the thin film diaphragm 3 is a narrow and deep groove 6 for absorbing strain stress, and is opened in the lower surface 5 of the peripheral fixing part 4, and these openings 6a, 6b, 6c and 6d form a quadrilateral. The longitudinal directions of the openings forming the sides of the quadrilateral are all oriented in the <112> axis direction. The width of the opening is from several μm to several tens of μm, and the depth of the groove is approximately 80 to 90% of the thickness of the peripheral fixing portion 4, or approximately 160 to 180 μm.
このような歪応力吸収の為の溝6は、周辺固定
部4の下面5にSiO2,Si3N4などの薄膜を形成し
た後上記開口6a,6b,6c,6dに対応した
四辺形パターンをフオト・リソグラフイーの技術
によりくり抜いたのち、APW(Amine
Pyocatechol Water)エツチングを施すことで
極めて好適に形設できる。すなわち、APWエツ
チングによれば111面はほとんどエツチングさ
れない。従つて、110面上に112軸方向に長
手方向を有するように開けられたエツチング窓を
有するシリコンをAPWエツチングすれば、深さ
方向にのみエツチングされ、横方向のエツチング
すなわちアンダーエツチは111面があらわれる
のでほとんど進まない。結局、下面5が上記四辺
形パターンの深さ方向にのみエツチングされて下
面5に垂直な溝壁7a,7b,7c,7dをもつ
歪応力吸収の為の溝6が狭く深い断面略U字状に
形成されることになるからである。歪応力吸収の
為の溝6の深さはエツチング時間によりコントロ
ールでき、幅は前記フオト・リソグラフイー技術
によつてエツチングマスクに開けられる四辺形パ
ターンの辺の幅によつてコントロールできる。 The grooves 6 for absorbing strain and stress are formed by forming a thin film of SiO 2 , Si 3 N 4 , etc. on the lower surface 5 of the peripheral fixing part 4, and then forming a rectangular pattern corresponding to the openings 6a, 6b, 6c, and 6d. After hollowing out using photolithography technology, APW (Amine
It can be shaped very well by etching (Pyocatechol Water). That is, according to APW etching, surface 111 is hardly etched. Therefore, if APW etching is performed on silicon that has an etching window with the longitudinal direction along the 112 axis on the 110 plane, etching will occur only in the depth direction, and lateral etching, that is, underetching will occur on the 111 plane. Because it appears, there is almost no progress. As a result, the lower surface 5 is etched only in the depth direction of the quadrilateral pattern, and the grooves 6 for absorbing strain and stress, which have groove walls 7a, 7b, 7c, and 7d perpendicular to the lower surface 5, have a narrow and deep cross section that is approximately U-shaped. This is because it will be formed in The depth of the groove 6 for absorbing strain stress can be controlled by the etching time, and the width can be controlled by the width of the sides of the quadrilateral pattern formed in the etching mask by the photolithography technique.
このようにして周辺固定部4の下面5に開口す
る断面略U字状の歪応力吸収の為の溝6を形成さ
れたシリコンダイヤフラム1は、第4図に示すよ
うに、その上面にフオト・リソグラフイーの手法
によりたとえばピエゾ抵抗素子より成る歪ゲージ
部9を形成され、歪応力吸収の為の溝6より外側
の周辺固定部下面5の取付面5aの部分で取付台
10に取り付けられ、圧力・差圧・絶対圧等の検
出素子11とされる。 As shown in FIG. 4, the silicon diaphragm 1 in which the groove 6 for absorbing strain and stress, which has a substantially U-shaped cross section and opens in the lower surface 5 of the peripheral fixing part 4, is formed has a photo-conductor on its upper surface. A strain gauge part 9 made of, for example, a piezoresistive element is formed by a lithography method, and is attached to a mounting base 10 at a part of the mounting surface 5a of the peripheral fixing lower surface 5 outside the groove 6 for absorbing strain stress. - Used as a detection element 11 for differential pressure, absolute pressure, etc.
上記シリコンダイヤフラム1では、上記説明の
ようにそれ自身が歪応力吸収の為の溝6を有して
いるから、周辺固定部4から薄膜ダイヤフラム3
への歪応力の伝達がほとんどない。従つて、歪応
力による零点の温度ドリフトが非常に少く、極め
て安定に動作しうるものである。また、取付台1
0を特殊な構造とする必要もなく、素材もガラ
ス、シリコン、アルミナ、金属などの素材を任意
に使用することができる。さらにその上、取付台
10への取り付けを、低融点ガラス、合成樹脂接
着剤、金―シリコンの共晶を利用する方法など任
意に選択して行うことができる。また歪応力吸収
の為の溝6が狭く深い断面U字状であるから、ダ
イヤフラム1の両面の差圧によりブリツジ部12
に生ずる応力は剪断応力になるが、シリコンは剪
断応力に対して強いので、大きな差圧下でも強度
的に問題なく使用できる。 Since the silicon diaphragm 1 itself has the groove 6 for absorbing strain stress as described above, the thin film diaphragm 3 is connected to the peripheral fixing part 4.
There is almost no transmission of strain stress to the Therefore, there is very little temperature drift at the zero point due to strain stress, and the device can operate extremely stably. In addition, mounting base 1
There is no need for 0 to have a special structure, and any material such as glass, silicon, alumina, or metal can be used. Furthermore, attachment to the mounting base 10 can be carried out by any method such as using low melting point glass, synthetic resin adhesive, or gold-silicon eutectic. In addition, since the groove 6 for absorbing strain stress is narrow and deep and has a U-shaped cross section, the differential pressure between both sides of the diaphragm 1 causes the bridge portion 12 to
The stress generated in this case becomes shear stress, but silicon is strong against shear stress, so it can be used even under large differential pressures without any problems in terms of strength.
他の実施例としては、歪応力吸収の為の溝をダ
イヤフラムの上面に開口する溝とするもの、ある
いは下面に開口する溝と上面に開口する溝との二
重の溝とするものが挙げられる。また、他の異方
向性エツチングたとえばアルカリエツチングを用
いて歪応力吸収の為の溝を形成してもよい。 Other examples include one in which the groove for strain stress absorption is a groove that opens on the top surface of the diaphragm, or one in which the groove is a double groove with a groove that opens on the bottom surface and a groove that opens on the top surface. . Further, grooves for absorbing strain stress may be formed using other anisotropic etching such as alkali etching.
さらにスパツタリング、プラズマエツチング、
電子ビーム加工などを用いて歪応力吸収の為の溝
を形成してもよい。この場合には、<112>軸
方向の辺をもつ四辺形パターンの溝とする必要が
ないから、円形パターンなどの任意のパターンの
溝を形設することができる。またさらに、半導体
をゲルマニウムとしたものが挙げられる。 In addition, sputtering, plasma etching,
Grooves for absorbing strain stress may be formed using electron beam machining or the like. In this case, since it is not necessary to form grooves in a quadrilateral pattern with sides in the <112> axis direction, it is possible to form grooves in any pattern such as a circular pattern. Further, examples include those using germanium as the semiconductor.
第1図はこの発明の半導体ダイヤフラムの一実
施例の第2図における―断面図、第2図は第
1図に示す半導体ダイヤフラムの底面図、第3図
は同じく底面部を見た斜視図、第4図は第1図に
示す半導体ダイヤフラムを用いた圧力検出素子の
縦端面図である。
1…シリコンダイヤフラム、3…薄膜ダイヤフ
ラム、4…周辺固定部、5…下面、5a…取付
面、6…歪応力吸収の為の溝、6a,6b,6
c,6d…開口、7a,7b,7c,7d…溝
壁、9…ピエゾ抵抗素子、10…取付台、11…
圧力検出素子。
FIG. 1 is a sectional view of an embodiment of the semiconductor diaphragm of the present invention in FIG. 2, FIG. 2 is a bottom view of the semiconductor diaphragm shown in FIG. 1, and FIG. 3 is a perspective view of the same bottom surface. FIG. 4 is a longitudinal end view of the pressure sensing element using the semiconductor diaphragm shown in FIG. 1. DESCRIPTION OF SYMBOLS 1...Silicon diaphragm, 3...Thin film diaphragm, 4...Peripheral fixing part, 5...Bottom surface, 5a...Mounting surface, 6...Groove for strain stress absorption, 6a, 6b, 6
c, 6d...Opening, 7a, 7b, 7c, 7d...Groove wall, 9...Piezo resistance element, 10...Mounting base, 11...
Pressure detection element.
Claims (1)
面へ向けて凹ませて薄膜ダイヤフラムを形成する
と共に、その周囲の比較的厚肉の部分を周辺固定
部として取付台に取付けられる半導体ダイヤフラ
ムにおいて、薄膜ダイヤフラムを取り囲むように
周辺固定部に細く深い溝を形成し、この溝より外
側の上記周辺固定部の下面を上記取付台の取付面
としてなる半導体ダイヤフラム。 2 半導体がシリコンであり、板状チツプの上・
下面を110面とし、下面110面上で<112
>軸方向に辺をもつ4辺形の各辺に沿つて異方向
性エツチングを施して、周辺固定部下面に開口す
る細く深い溝を形成してなる請求の範囲第1項記
載の半導体ダイヤフラム。 3 異方向性エツチングが、APW(Amine
Pyrocatechol Water)エツチングである請求の
範囲第2項記載の半導体ダイヤフラム。 4 薄膜ダイヤフラム上面にピエゾ抵抗素子が形
成されてなる請求の範囲第1項から第3項のいず
れかに記載の半導体ダイヤフラム。[Scope of Claims] 1. A thin film diaphragm is formed by recessing the central part of the lower surface of a semiconductor single crystal plate chip toward the upper surface, and a relatively thick part around the thin film diaphragm is used as a peripheral fixing part to be attached to a mounting base. A semiconductor diaphragm to be mounted, in which a narrow and deep groove is formed in the peripheral fixing part so as to surround the thin film diaphragm, and the lower surface of the peripheral fixing part outside the groove serves as the mounting surface of the mounting base. 2 The semiconductor is silicon, and the top of the plate-shaped chip
The bottom surface is 110, and <112 on the bottom 110 surface.
2. The semiconductor diaphragm according to claim 1, wherein the semiconductor diaphragm is formed by performing anisotropic etching along each side of a quadrilateral having sides in the axial direction to form a narrow and deep groove opening at the lower surface of the peripheral fixation. 3 Anidirectional etching is APW (Amine
3. The semiconductor diaphragm according to claim 2, wherein the semiconductor diaphragm is etched using pyrocatechol water. 4. The semiconductor diaphragm according to any one of claims 1 to 3, wherein a piezoresistive element is formed on the upper surface of the thin film diaphragm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56137562A JPS5839069A (en) | 1981-08-31 | 1981-08-31 | Semiconductor diaphragm |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56137562A JPS5839069A (en) | 1981-08-31 | 1981-08-31 | Semiconductor diaphragm |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5839069A JPS5839069A (en) | 1983-03-07 |
| JPH0158673B2 true JPH0158673B2 (en) | 1989-12-13 |
Family
ID=15201618
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56137562A Granted JPS5839069A (en) | 1981-08-31 | 1981-08-31 | Semiconductor diaphragm |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5839069A (en) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0643129B2 (en) * | 1984-03-01 | 1994-06-08 | キヤノン株式会社 | Inkjet recording head |
| JPH064334B2 (en) * | 1984-10-19 | 1994-01-19 | キヤノン株式会社 | Liquid jet recording head manufacturing method |
| JPS63283073A (en) * | 1987-05-15 | 1988-11-18 | Toshiba Corp | Semiconductor pressure sensor |
| JPH01127268U (en) * | 1988-02-23 | 1989-08-31 | ||
| JPH0363834U (en) * | 1989-10-24 | 1991-06-21 | ||
| US6346742B1 (en) | 1998-11-12 | 2002-02-12 | Maxim Integrated Products, Inc. | Chip-scale packaged pressure sensor |
| US6351996B1 (en) * | 1998-11-12 | 2002-03-05 | Maxim Integrated Products, Inc. | Hermetic packaging for semiconductor pressure sensors |
| JP4347560B2 (en) | 2002-12-17 | 2009-10-21 | シャランインスツルメンツ株式会社 | Optical element fixing structure, optical element fixing body, optical element and optical element holder |
| JP5837846B2 (en) * | 2012-02-29 | 2015-12-24 | アルプス電気株式会社 | Capacitance type physical quantity sensor and manufacturing method thereof |
| JP5824385B2 (en) * | 2012-02-29 | 2015-11-25 | アルプス電気株式会社 | Capacitance type physical quantity sensor and manufacturing method thereof |
-
1981
- 1981-08-31 JP JP56137562A patent/JPS5839069A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5839069A (en) | 1983-03-07 |
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