JPH0159766B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital delay device, and more particularly to a digital delay device used, for example, in video signal processing of a digital television receiver.

[Prior Art] Conventionally, as a large-capacity digital delay means, there is a so-called digital delay device that sequentially reads and writes to memory cells arranged in a matrix to obtain a desired delay. FIG. 2 is a block diagram showing an example of a conventional digital delay device. In the figure, a basic clock φ _S is input to an input terminal 1. The unit delay (minimum delay width) in this digital delay device is equal to one cycle of the basic clock φ _S. The basic clock φ _S input from the input terminal 1 is applied to the address counter 2 . This address counter 2 is incremented at the rising edge of the basic clock _φS , and
It outputs the X address to the decoder 3 and the Y address to the Y decoder 4. The input terminals 13 ₁ to 13 _o are terminals that receive input data signals input in synchronization with the basic clock φ _S , and will be described here with a configuration that receives n-bit input. It is assumed that the MSB (most significant bit) of the input data signal is applied to the terminal ₁₃₁ , and the LSB (least significant bit) is applied to the terminal _13o . The input data signal is applied via input latch 11 to a write circuit controlled by signal WE. The memory cell array 5 is a group of memory cells arranged in a matrix, and its storage capacity is MXn bits. Transfer gate 6 transmits read data from memory cell array 5 to sense amplifier 7, and also transmits data from write circuit 10 to memory cell array 5. Sense amplifier 7 is controlled by signal SE,
Amplify read data. Data latch 8 temporarily stores the output of sense amplifier 7. signal
The data latch 8 is electrically isolated from the sense amplifier 7 while SE is at a low level. Output latch 9 outputs the delayed output from data latch 8 in cycles of basic clock φ _S and applies it to output terminals 12 ₁ to 12 _o . of the output data signal
The MSB is output from the terminal ₁₂₁ , and the LSB is output from the terminal _12o .

Further, the basic clock φ _S input from the input terminal 1 is applied to the timing generator 14 .
The timing generator 14 receives the basic clock _φS and generates the signal SE and the signal WE in the timing sequence shown in FIG. While the signal SE is at high level, the sense amplifier 7 is activated.
The signal W puts the write circuit 8 into an operating state during a high level period. Note that the address counter 2 is reset every M cycles by a reset circuit (not shown). The conventional digital delay device is configured as described above.

In a PAL television receiver, an analog video signal is sampled at a frequency of 4f _SC (f _SC : color subcarrier frequency) to generate a digital video signal, and a delay of one scanning line ( When trying to realize a 1-line memory that achieves 1H delay) with the configuration shown in Figure 2, M=
1135, n=8. Also, the X address is X ₀ ~
X ₇ , Y address is Y ₀ ~ _{Y 2} , 1 of basic clock φ _S
The cycle is 56ns.

Next, the operation of the conventional configuration example shown in FIG. 2 will be explained using the timing chart shown in FIG. 3. In this example, we will explain how a delay of M cycles can be obtained using an M×n bit memory having an address space of A ₁ to A _M and processing n bits of data in parallel. Note that the memory used in this digital delay device is arranged in n sets of arrays each having an address capacity of M, and each set of arrays corresponds to one memory cell for one address. Therefore, when a certain address is designated, a total of n memory cells from n sets of arrays are accessed in parallel. In a so-called byte-structured memory, n=8. In the following explanation, the input data newly stored at each address of A ₁ to _{A M} will be referred to as D ₁ to _DM , respectively, and the output data read from A ₁ to A _M will be referred to as PD ₁ , respectively. 〜PD _M.

First, the address counter 2 is operated by the basic clock φ _S and outputs an X address to the X decoder 3 and a Y address to the Y decoder 4.

In the memory cell array 5, among the cells belonging to the row selected by the X decoder 3, data of a total of n bits of memory cells belonging to the column connected to the transfer gate 6 selected by the Y decoder 4 is inputted to I/O. It is output on line 17. For example, when the output of the address counter 2 specifies the address _A1 , the information _PD1 of a total of n memory cells located at each address _A1 of n arrays is read out in parallel via the transfer gate 6. . read n
The bit data PD ₁ is amplified by the sense amplifier 7 and taken into the data latch 8 while the signal SE is at a high level. As the signal SE falls, the data latch 8 is electrically disconnected from the sense amplifier 7, so that the data latch 8 holds the read data _PD1 while the signal SE is at a low level. The read data PD ₁ is transmitted to the output latch 9 and outputted in parallel from n output terminals 12 ₁ to 12 _o . In this way, as shown in FIG. 3, data is read out sequentially in response to changes in the address signal for each cycle of the basic clock _φS .

On the other hand, during the specified period of the same address after the fall of the signal SE, the write circuit 10 operates while the signal WE is at a high level, and writes the n-bit input signal sent from the input latch 11 to I/O. O line 1
7 and rewrites the data in the selected memory cell. For example, immediately after the previous data PD _{1 is read from address A 1 and} stored in data latch 8, new data D ₁ is written to the memory cell at address A ₁ . Data D ₁ is read out when address A ₁ is designated again after M cycles. In this way, the memory cell at each address is read-out every M cycles.
A MODIFIED-WRITE operation is performed, and the newly written data is output after M cycles.
A delay of M cycles can be achieved.

[Problems to be Solved by the Invention] As explained above, the conventional digital delay device must perform reading and writing during one cycle of the basic clock _φS . Therefore, the cycle of the basic clock _φS is determined by taking into consideration the read access time until data latch, write completion time (pulse width of signal WE), pulse width of signal SE, timing margin between address signals, etc. There were problems such as having to do so, making it difficult to increase the speed. For example, the digital delay device used in PAL television receivers requires a cycle time of 56 ns.
When using the conventional process technology and the above conventional configuration, READ-MODIFIED-
WRITE must be performed, making it difficult to operate with sufficient timing margin.

The present invention has been made to solve the above-mentioned problems, and its object is to obtain a digital delay device that is faster than the conventional configuration using the same process technology as the conventional one.

[Means for Solving the Problems] The digital delay device according to the present invention divides the address space of a group of memory cells arranged in a matrix into halves, and the memory cells in each divided address space respond to the basic clock pulse. A READ-MODIFIED-WRITE is completed in twice as many cycles, and the two address spaces are alternately accessed with a phase shift of one cycle of the basic clock pulse, so that the read data from both address spaces is While the clock rate is alternately output, the input data input in synchronization with the basic clock pulse is alternately written into both address spaces.

[Function] In this invention, while each address space is substantially operated at a clock rate equivalent to two cycles of the basic clock pulse, data input/output operations can be completed in apparently the same cycle as the basic clock pulse. Therefore, the digital delay device can be operated at a clock rate of half the minimum operation cycle of each address space, and high-speed performance can be obtained.

[Embodiment of the Invention] FIG. 1 is a block diagram showing an embodiment of the invention. The digital delay device shown in FIG. 1 is for realizing a delay of M cycles for n-bit input data, and the memory cell array is divided into two.
forms an even address plane, the second memory cell array forms an odd address plane, and each memory cell array has an equal storage capacity of (M/2)×n bits. A basic clock φ _S is input to the input terminal 80, and one cycle of the basic clock φ _S is equal to a unit delay. Terminals 101 ₁ to 101 _o are terminals for receiving n-bit input data signals input at the clock rate of the basic clock φ _S , and the input data signals are applied to write circuits 88 and 98 via input latch 90 . The timing generator 99 receives the basic clock _φS and receives various timing signals _φEV ,
φ _OD , SE _EV , SE _OD , WE _EV , WE _OD , OE _EV , OE _OD
is generated in the timing sequence shown in FIG. The signal _φEV is a frequency-divided version of the basic clock _φS , has twice as many cycles as the basic clock _φS , and increments the address counter 81 at its falling edge. The signal φ _OD is a clock having the opposite phase to the signal φ _EV , and the address counter 91 is incremented at its falling edge. Signal SE _EV ,
SE _OD activates the sense amplifiers 86 and 96, respectively, during the high level period. signal
WE _EV and WE _OD are respectively, during the high level period.
The write circuits 88 and 98 are activated. signal
OE _EV controls the output of data latch 87 and outputs the signal
OE _OD controls the output of data latch 97.

The address counter 81 receives the signal φ _EV and inputs an even numbered X address to the X decoder 82 and an even numbered Y address to the Y decoder 83 in the cycle of this signal φ _EV (twice the cycle of the basic clock φ _S ). supply The output of the X decoder 82 is applied to a first memory cell array 84, and the output of the Y decoder 83 is applied to a transfer gate 85. Similarly, the address counter 91 receives the signal φ _{OD and} in the cycle of this signal φ _OD (twice the cycle of the basic clock _φ Supply address. The output of the X decoder 92 is applied to a second memory cell array 94, and the output of the Y decoder 93 is applied to a transfer gate 95. Transfer gate 85
The read data from the first memory cell array 84 is sent to the sense amplifier 86 via the I/O line 102.
Also, data from write circuit 88 sent via I/O line 102 is transmitted to first memory cell array 84 . Similarly, the transfer gate 95 transmits read data from the second memory cell array 94 to the sense amplifier 96 via the I/O line 103, and also transmits the read data from the second memory cell array 94 to the write circuit 98 sent via the I/O line 103. Data from the second
The data is transmitted to the memory cell array 94 of. Sense amplifier 86 is controlled by signal SE _EV , amplifies read data, and supplies it to data latch 87. Data latch 87 temporarily stores the output of sense amplifier 86. When the signal SE _EV is at a low level, the data latch 87 is electrically isolated from the sense amplifier 86. In addition, the data in the data latch 87 is stored during the period when the signal OE _EV is at a high level.
The configuration is such that the signal is transmitted to the output latch 89.
Similarly, sense amplifier 96 is controlled by signal SE _OD to amplify read data and provide it to data latch 97. Data latch 97 temporarily stores the output of sense amplifier 96. When the signal SE _OD is low level, the data latch 97 is connected to the sense amplifier 9.
The configuration is such that it is electrically separated from 6.
Further, the data in the data latch 97 is transmitted to the output latch 89 while the signal _OEOD is at a high level. Output latch 89 outputs an M-cycle delayed output in synchronization with basic clock φ _S and applies it to output terminals 100 ₁ -100 _o . Note that the address counters 81 and 92 each have a reset circuit (not shown), and are reset every M cycles. As described above, a digital delay device according to an embodiment of the present invention is configured.

FIG. 4 is a time chart for explaining the operation of the embodiment shown in FIG. Next, the operation of the embodiment shown in FIG. 1 will be explained with reference to FIG. 4. Note that in the following explanation, the input terminal 101
₁ ~ 101 _o is input to the input latch 11, and A ₁ ~
Let the input data newly stored at each address of A _M be D ₁ to D _M , respectively, and the addresses A ₁ to _{A M}
The output data read from PD ₁ to
Let it be PD _M. A timing generator 99 divides the basic clock φ _S to generate a signal φ _EV and a signal φ _OD having the opposite phase thereof. In response to the signal φ _EV , the address counter 81 generates an even address Ad _EV with twice the cycle of the basic clock φ _S , and sends an even numbered X address to the X decoder 82 and an even numbered Y address to the Y decoder 83. Output. On the other hand, in response to the signal φ _OD , the address counter 91 generates an odd address Ad _OD of twice the cycle of the basic clock φ _S , and transmits the odd address X address to the X decoder 92 and the odd address Output Y address. What should be noted here is that the even address Ad _EV and the odd address Ad _OD are out of phase by one cycle of the basic clock φ _S. Now, in the first memory cell array 84, the output of the address counter 81 is the address A ₂
If , n memory cells located at address A ₂ are accessed by the X decoder 82 and Y decoder 83, and n-bit data PD ₂ that was already stored (M-1) cycles ago is transferred. The output from gate 85 is read out to I/O line 102. The data PD ₂ is amplified by the sense amplifier 86 while the signal SE _EV is at a high level, and is taken into the data latch 87. Since the data latch 87 is electrically disconnected from the sense amplifier 86 as the signal SE _EV falls, the data latch 87 holds the read data while the signal SE _EV is at a low level.
Hold PD ₂ . The data PD ₂ held in the data latch 87 is transmitted to the output latch 89 during the high level period of the signal OE _EV , and is transmitted to the n output terminals 1
Data PD ₂ is output from 00 ₁ to 100 _o . On the other hand, during the high level period of the signal WE _EV , the write circuit 8
8 operates, and the new n input from input terminals 101 ₁ to 101 _o and stored in input latch 90 is activated.
Bit data _D2 is written to the memory cell at the same address _A2 . Thus, READ-MODIFIED-WRITE in _A2 address cycle is completed.

The _A3 address cycle begins in the second memory cell array 94 when one cycle of the basic clock _φS has elapsed from the start of the _A2 address cycle.
The output of address counter 91 specifies address _A8 , and n memory cells located at address _A3 are accessed by X decoder 92 and Y decoder 93. Bit data (PD ₃ ) is transferred to transfer gate 95
The data is read out to the I/O line 103 via the . data
PD ₃ is amplified by the sense amplifier 96 and taken into the data latch 97 while the signal SE _OD is at high level. Since the data latch 97 is electrically disconnected from the sense amplifier 96 as the signal SE _OD falls, the data latch 97 holds the read data PD ₃ while the signal SE _OD is at a low level. Next, when the signal OE _OD becomes high level, the data PD ₃ is transmitted to the output latch 89 and output from the n output terminals 100 ₁ to 100 _o . on the other hand,
The write circuit 98 operates during the high level period of the signal _WEOD , and the new n-bit data _D3 input from the input terminals ₁₀₁₁ to _101o and stored in the input latch 90 is written to the same memory cell _A3 . be included.
Thus, in A ₃ address cycles READ
-MODIFIED-WRIHE operation is complete. During this time, the _A4 address cycle starts in the second memory cell array 84 when one cycle of the basic clock _φS has elapsed from the start of the _A3 address cycle, and the read operation of the data _PD4 is performed.

As described above, the input data inputted at the clock rate of the basic clock _φS is written alternately to the first memory cell array 84 and the second memory cell array 94, and at the same time, the input data is written to both memories from the output terminals ₁₀₀₁ to _100o . The read data from the cell arrays 84 and 94 is output alternately at the clock rate of the basic clock φ _S with a delay of M cycles of the basic clock φ _S from the time when the read data is input. In this way, it operates as a digital delay device that realizes M-cycle delay.

In the above embodiment, the signals OE _EV and OE _OD are used to control the output of the data latch, but the signals φ _EV and φ _OD may be used instead. Also,
Signals WE _EV , WE _OD , signals SE _OD , respectively
It is also possible to substitute SE _EV . Furthermore, in the above embodiment, the signal SE EV is made active during the first half period (one cycle of the basic clock φ _S ) of the even address cycle, and the signal SE _EV is activated during the second half period (one cycle of the basic clock φ _S) .
I activated the signal WE _EV for 1 cycle), but
It may be made active in the latter half of an even address cycle together with the signals SE _EV and WE _EV . In short, READ− during even address cycles
It is sufficient if the MODIFIE-WRITE operation is completed. This means that the signal in odd address cycles
The same applies to SE _OD and WE _OD .

Furthermore, in the above embodiment, since two memory cell arrays having address spaces with the same storage capacity are accessed, it is possible to obtain a data delay that is an even multiple of the unit delay, but in order to obtain a data delay that is an odd multiple of the unit delay, 1 immediately before or after the output latch 89
For example, a stage delay circuit (register) may be provided.

Further, the digital delay device according to the present invention may be realized using a static memory circuit or a dynamic memory circuit.

[Effects of the Invention] As described above, according to the present invention, the address space corresponding to the amount of delay is divided into two memory cell arrays, and each memory cell array has an address space within twice the cycle of the basic clock pulse φ _S. The configuration is such that the READ-MODIFIED-WRITE operation is carried out at 100 kHz, and the phase of the address cycle is shifted by one cycle of the basic clock pulse φ _S between both arrays, so that the read data from both arrays is synchronized with the clock pulse of the basic clock pulse φ _S. Since the input data input at the clock rate of the basic clock pulse φ _S is alternately stored in both arrays while the data is output alternately at the clock rate of the basic clock pulse φ _S , each array is effectively The digital delay device can be operated at a clock rate of half the minimum operation cycle of the memory cell array, since data input/output operations can apparently be completed at the clock rate of the basic clock pulse φ _S while operating at a clock rate of . This has the effect of providing twice the high-speed performance compared to conventional digital delay devices.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is a block diagram showing an example of a conventional digital delay device. FIG. 3 is a time chart for explaining the operation of the conventional digital delay device shown in FIG. FIG. 4 is a time chart for explaining the operation of the embodiment of the present invention shown in FIG. In the figure, 81 and 91 are address counters, 82 and 92 are X decoders, and 83 and 9 are
3 is a Y decoder, 84 is a first memory cell array, 94 is a second memory cell array, 85 and 95 are transfer gates, 86 and 96 are sense amplifiers, 87 and 97 are data latches, 88 and 98 are write circuits, 89 and 90 is an input latch,
99 is a timing generator, 100 ₁ to 10
0 _o indicates an output terminal, and 101 ₁ to 101 _o indicate input terminals.

Claims (1)

[Scope of Claims] 1. A digital delay device whose operation is controlled in synchronization with a basic clock pulse φ _S and which outputs an input signal delayed by a predetermined time width, wherein the input signal synchronized with the basic clock pulse φ _S is an even address signal generating means for generating an even address signal having twice the cycle of the basic clock pulse φ _S ; and an even address signal generating means for generating an _even address signal having twice the cycle of the basic clock pulse φ Odd address signal generating means for generating an odd address signal whose phase differs from the address signal by one cycle of the basic clock pulse φ _S ; 1 memory cell array; a second memory cell array having an odd address space and addressed by the odd address signal; and data of the first memory cell array addressed and read by the even address signal. a first latch means for temporarily storing and holding the data in the first memory cell array; and after the data in the first memory cell array is stored and held by the first latch means, a first data writing means for writing an input signal from the input terminal into a memory cell of the first memory cell array; and a first data writing means for writing an input signal from the input terminal into a memory cell of the first memory cell array; a second latch means for storing and retaining data in the second memory cell array; and after the data in the second memory cell array is stored and retained by the second latch means, the second memory cell array designated by the odd address signal at that time is a second data write means for writing an input signal from the input terminal into a memory cell of the cell array; and a second data write means for writing the input signal from the input terminal into the memory cell of the cell array, and writing the data stored in the first and second latch means at the clock rate of the basic clock pulse _φS . A digital delay device comprising means for alternately outputting the output.