JPH0159782B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for receiving excessive messages, and more particularly, to a system in which a line control device controlled by a processing device receives messages and transfers them to a buffer. Concerning the method of receiving messages.

In this type of system, a line control device corresponding to the line receives a message coming from the line, and temporarily stores it in a buffer under the control of a processing device.
Conventionally, in order to enable continuous reception of messages of various lengths, reception buffers were usually set in consideration of the most common message length, and several reception buffers were chained together. A system was adopted in which when a received message became long and one side of the receiving buffer became full, a new receiving buffer was chained. In order to process the received message, it is necessary that the message has been successfully received, so when receiving a long message, a large buffer area is required to accommodate the long message.
While the received message is being processed, the buffer area is held and exclusively used for processing the received message.

This type of message has the structure shown in FIG. 2, for example. In Figure 2, M indicates a message, and the message M
is composed of telegram information D and check information CH for the telegram information D, and synchronization signals SF ₁ and SF ₂ are added before and after the telegram M, respectively.
When receiving a message, first the synchronization signal SF ₁ is detected, the information following this is determined to be the message M, and then when the synchronization signal SF ₂ is further detected, the completion of the message M is determined. Therefore, when receiving a message using this conventional method, if the synchronization signal SF ₂ indicating the completion of message M is not received correctly due to an abnormality in the communicating party's (sending side) system or an error on the transmission path, the message will not be completed. cannot be determined, resulting in an excessive number of messages.
In this type of system, a processing unit usually controls multiple line control units and sets up a buffer area in a storage device connected to the processing unit, and the buffer area is commonly used by the multiple lines. It is configured as follows. Therefore, when a message that has caused an error and becomes an excessive message is transferred to a buffer, a large amount of the buffer that is commonly used for each line is unjustly monopolized by the excessive message whose termination cannot be determined, and as a result, This results in inconveniences such as insufficient buffer area to transfer and store messages to be input to other line control devices, and reception of messages on other lines may be inhibited.

In order to prevent the above-mentioned inconvenience caused by receiving an excessive message, conventionally a processing device monitors the length of the received message, and when it is determined that the message is excessive, processes such as stopping writing to the buffer are performed. Ta. This conventional method has the disadvantage that the processing load on the processing device is large, and that it is not possible to check whether the message whose reception has been interrupted is the correct message.

The present invention eliminates the above-mentioned drawbacks of the conventional method, and determines in a line control device whether or not a received message has reached the maximum receivable message length, and prevents a message exceeding this length from being written to the reception buffer. to prevent unfair appropriation of reception buffers due to reception of excessive messages,
The present invention also aims to identify whether a message determined to be an excessive message is a correct message or not, thereby reducing the load on a processing device in taking measures against the above-mentioned excessive message.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing an outline of connections in an embodiment of the present invention. In the figure, L is a line, CCU is a line control device, CPU is a processing device, and MM is a storage device. A message in the format shown in FIG. 2 described above is transmitted to the line L.

In the line control unit CCU, CNT is a counter, CMP is a comparison circuit, REG is a register, AG is an AND gate, FD is a synchronization signal (SF ₁ and SF ₂ in Figure 2) detection circuit, CHK is a check circuit,
CONT is a control circuit. and the counter
CNT, comparison circuit CMP, and register REG constitute means for recognizing the length of the received message.

The counter CNT detects the length of the received message, counts the number of bytes in the message, and is reset under normal conditions, and its counting output is 0. register
REG stores a numerical value corresponding to the maximum receivable message length and the number of message bytes. Comparison circuit CMP compares the contents of counter CNT and register REG, and outputs "0" when the contents of counter CNT do not reach the contents of register REG, and outputs "1" when it reaches the contents of register REG.
Output. This output is given to AND gate AG, which is conductive when it is "0" and non-conductive when it is "1".

When receiving a message, the processing unit CPU stores a table for managing the received message in the storage device MM,
Set the so-called CCW (Channel Command Word). CCW includes command code, received message number, buffer received message storage start address,
Similarly, the final storage address of the received message, termination information, etc. are set, and after the received message is stored in the buffer, it is managed by the contents of this CCW.

When the line control unit CCU starts receiving messages,
The message input from line L is sent to the synchronization signal detection circuit.
When the synchronization signal SF ₁ is detected in the FD, it is determined that the message M has started, and the output (B) is sent.
This is sent to the processing unit CPU via the control circuit CONT to notify the start of the message M, and also to the counter CNT.
Start.

The telegram signal input from line L passes through AND gate AG, passes through processing unit CPU, and is stored in a buffer set in storage unit MM. Note that the starting address for storing the buffer's received message is specified by the corresponding address set in the CCW.

When the message M is completed, the synchronization signal _SF2 is input, and when the synchronization signal detection circuit FD detects this, it sends out the output (B) in the same manner as described above. This output (B) notifies the control circuit CONT of the end of the message, and this output (B) also stops the operation of the counter CNT.
Here, the synchronization signal detection circuit is used as a means for detecting the start and end of a message.

In this case, the length of the message does not reach the length set in the register REG, so the output of the comparator circuit CMP will never be "1" and the AND gate will not reach the length set in the register REG.
AG does not become non-conductive, and all received messages are stored in the buffer area of the storage device MM via the processing device CPU.

When the synchronization signal detection circuit FD determines the end of the message as described above, it sends an end information check circuit.
Send to CHK.

Upon receiving the above termination information, the check circuit CHK checks whether the message was correctly received or not, and sends the result to the control circuit CONT.

To check whether the message was received correctly,
For example, this can be done as follows. That is, the check circuit CHK receives the check information CH (Figure 2) sent from the transmitting side from the buffer in the check circuit CHK, based on the above-mentioned message end information.
Extract. On the other hand, the check circuit CHK calculates check information for the received message using a fixed calculation method determined by the check method, and when the message ends, it is compared with the check information sent from the above-mentioned sending side. It is determined that the message was received in error.

In the above case, when a message is received correctly or incorrectly, the message is sent to the processing unit via the control circuit CONT based on the information from the check circuit CHK and the synchronization detection circuit FD.
Sent to CPU and stored in CCW. In the above case, the length of the message does not exceed the length set in the register REG, so the output of the comparator circuit CMP continues to be "0", but this output information "0" is also output by the control circuit CONT. The message is received and sent to the processing unit CPU as information that the message length does not exceed the set length, and is also stored in the CCW.

If the message received is an excessive message,
Suppose that the length set in register REG has been exceeded.
While receiving a message, the length of the received message is stored in the register.
When the length set in REG is reached, the comparator circuit CMP
The output of ``0'' changes to ``1'', so the AND gate AG becomes non-conductive, and the message from line L is blocked here and is no longer sent to the buffer. This causes the buffer to stop storing the portion exceeding the length set in register REG.

However, this received telegram continues to be input to the synchronization signal detection circuit FD and check circuit CHK, where it is monitored. When the synchronization signal _SF2 is detected and the check circuit CHK determines that the message has been received correctly or incorrectly, the same information as above is sent to the control circuit CONT. Further, when the message ends, the counter CNT stops the counting operation and sends the count output at that time, in other words, information on the length of the received message to the control circuit CONT.
Also, the output “1” of the comparison circuit CMP is the control circuit
CONT, so this is sent to the processing unit CPU as information indicating an excessive message as described later.

The control circuit CONT receives the above various information,
The message was received correctly or incorrectly and reception was completed (information from the synchronization detection circuit FD and check circuit CHK), the length of the message exceeded the set value (from the output of the comparison circuit CMP), the received message Sends information on the length (from the output of counter CNT) to the processing unit CPU. The processing unit CPU writes the necessary information to the CCW.

If the synchronization signal SF ₂ added to the end of the message M disappears for some reason, it is impossible to determine the end of the message by detecting the synchronization signal SF _2. In such a case, the synchronization signal detection circuit FD detects the timing. It is possible to determine whether or not the process has finished, and in such a case, the termination information is sent to the processing unit CPU via the control circuit CONT and written into the CCW.

The processing device CPU processes the received message according to the contents of the CCW. If a message that does not reach the set length is correctly received, it will be processed normally; however, for a message that exceeds the set length but is correctly received, the processing unit CPU will process the message correctly. For longer lengths, control circuit CONT
It is possible to request the sending side to retransmit by setting it in register REG via .

The present invention is not limited to the above embodiments, but
Various modifications are possible within the technical scope. For example, it is also possible to provide a buffer in the line control device.

Since the present invention is configured as described above, the line control device determines whether or not the received message exceeds a preset length, and when the length exceeds the length, stops writing the message to the reception buffer from then on. This has the effect of preventing unjust appropriation of the buffer, and also identifying whether or not the above-mentioned excessive message is a correct message, and implementing countermeasures against the above-mentioned excessive message without placing too much load on the processing device.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an outline of connections according to an embodiment of the present invention, and FIG. 2 is a diagram showing an example of the structure of a general message. L...Line, CCU...Line control device, CPU...
…processing unit, MM…memory device, CNT…counter, CMP…comparison circuit, AG…AND gate, FD…synchronous signal detection circuit, CHK…check circuit, CONT…control circuit, SF ₁ , SF ₂ ... Synchronization signal, D... Telegram information of message M, CH... Check information of message information D, M... Telegram.

Claims (1)

[Claims] 1. In a system configured such that a line control device controlled by a processing device receives a message and transfers it to a buffer via the processing device, the line control device includes a counter, a register, and a message. It is equipped with received message length recognition means consisting of a comparison circuit, a synchronization signal detection circuit for detecting the start and end of the message, and a control circuit, and the number of bytes of the message corresponding to the maximum receivable message length is set in the above register in advance. , When receiving a message, the message input from the line to the line control device is transferred to the buffer via the processing device, and the number of bytes of the input message is counted by the counter, and the counted value is sent to the comparison circuit. Therefore, it is compared with the number of bytes set in the register, and when the number of bytes of the input message does not reach the set number of bytes, the synchronization signal detection circuit detects the end of the message, and the signal is sent to the processing device via the control circuit. When the end of message reception is notified and the number of bytes of the input message reaches the set number of bytes, if the synchronization detection circuit does not yet detect the end of the message, the transfer of the input message to the buffer will be blocked, and then When the synchronization signal detection circuit detects the end of the message, it notifies the processing device via the control circuit, and the processing device stores the number of bytes for the message longer than the length of the received message in the register via the control circuit. A method for receiving an excessively large number of messages, which is characterized by requesting retransmission in the case of transmission.