JPH0159817B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an improvement in a change width detection relay that detects and operates when the amount of electricity in a detected power system suddenly changes.

[Technical background of the invention]

As one of the protective relays that protect the power system,
For example, there is a current change width detection relay. This relay is a relay that detects a system failure by detecting a sudden change in the magnitude or phase of the current as the amount of system electricity passing through the system when a system failure occurs.
It has a characteristic that it operates when the magnitude or phase of the input current changes by a certain value or more.

Figure 1 shows the most common phase characteristic diagram of this type of relay, where the steady state input current I ₀
The magnitude of the input current change component IΔ superimposed on
This indicates that the relay operates when the preset detection level ΔI is exceeded.

Next, a conventional circuit configuration for obtaining the characteristics of the current change range detection relay and its operating principle will be explained with reference to FIGS. 2 and 3.

First, in FIG. 2, 1 is a resonant circuit excited by the system electricity quantity and adjusted to resonate with the fundamental wave component of the system electricity quantity, 2 is input with the system electricity quantity and the output signal of the resonant circuit, Each shows a level determination circuit that outputs a detection signal when the difference between the two instantaneous values exceeds a certain value.

Next, in FIG. 3, A is the level determination circuit 2.
is the input waveform, and the solid line represents the system electricity amount, and
The broken line indicates the output of the resonant circuit 1. Here, the output of the resonant circuit 1 is adjusted to have exactly the same phase and amplitude as the input in a steady state where the amplitude and phase of the relay input do not change. Therefore, in a steady state, the difference between the amount of system electricity input to the level determination circuit 2 and the instantaneous value of the output of the resonant circuit 1 is extremely small, and does not exceed the operating level of the level determination circuit 2.

Next, consider a case where a failure occurs in the grid at time t ₁ in FIG. 3 and the amount of input electricity changes suddenly. In this case, the resonant circuit 1 has a high Q and resonates with respect to the input electrical quantity. Therefore, even if the phase or amplitude of the input electrical quantity suddenly changes, the output of the resonant circuit 1 cannot follow it suddenly, and the output of the amplitude and phase before the sudden change in the input is only within a predetermined time depending on the Q of the resonant circuit. Maintain the signal. Therefore, as shown by the shaded areas in FIG. 3A and B, there is a difference in instantaneous values between the two input signals of the level determination circuit 2, which corresponds to the change from the sine wave waveform, and this value When the preset value √2ΔI is exceeded, the level determination circuit 2 determines that the operation is active and outputs a detection signal shown in C in FIG.

[Problems with background technology]

The above is the operating principle of the conventional current change range detection relay shown in Figure 2. However, a major problem with this relay is that the change range detection characteristics are easily affected by frequency fluctuations in the grid electricity quantity. can be given. This point will be explained in detail below.

In the above-mentioned conventional system, a high Q resonance circuit is used in order to maintain the signal output before the change for a certain period of time even after the input electricity amount changes. Generally, a high Q resonant circuit is sensitive to changes in frequency, and even a small difference between the resonant frequency and the input frequency will cause a large change in the phase and amplitude of the output. That is, the resonant circuit 1 in FIG.
The output is adjusted to have the same amplitude and phase during resonance, but if a difference occurs between the resonant frequency of resonant circuit 1 and the frequency of the grid electricity quantity due to fluctuations in the frequency of the grid electricity quantity, the resonance circuit output Signal phase and amplitude will change significantly. For this reason,
Even in a steady state, an error component occurs between the resonant circuit output and the instantaneous value of the input electrical quantity, causing fluctuations in relay operating values and malfunctions.

Also, even if the frequency of the grid electricity is normal,
If there is a constant change in the circuit elements constituting the resonant circuit 1, an error component will similarly occur due to a shift in the resonant frequency, so there is a drawback that the failure detection characteristics of the relay are likely to change over time due to changes in the ambient temperature.

[Purpose of the invention]

The present invention was made in order to solve the above-mentioned drawbacks, and its purpose is to provide a stable relay that is not affected by frequency fluctuations in the amount of electricity in the system or by changes in temperature or aging of the relay itself. An object of the present invention is to provide a change width detection relay having change width detection characteristics.

[Summary of the invention]

In order to achieve the above object, the present invention provides a change width detection relay that receives the system electricity amount of the power system as input and detects a system failure by detecting that the system electricity amount has changed by a certain value or more. a control signal generating means that receives a quantity as an input and outputs a control signal having a frequency corresponding to the frequency of this system electricity quantity; an analog signal delay means for delaying the output by a time proportional to , and a level determination means for inputting the output from the analog signal delay means and the amount of grid electricity, and detecting that the difference between the instantaneous values of the two is greater than or equal to a certain value. It is characterized by being composed of.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 4 is a block diagram showing an example of the structure of a variation range detection relay according to the present invention.

In FIG. 4, the analog signal delay circuit inputs the system electricity amount S ₁ of the power system (not shown) and outputs S ₂ after internally delaying it for a certain period of time. The signal delay time of this analog signal delay circuit 3 is determined by the control signal It is controlled by the frequency of the control signal _S4 applied from the generating circuit 4. Reference numeral 4 designates a control signal generation circuit which receives the system electricity amount S ₁ as an input and outputs a control signal S ₄ having a frequency approximately proportional to the frequency of the system electricity amount S ₁ to the analog signal delay circuit 3.

Furthermore, 5 inputs the above-mentioned system electricity amount S ₁ and the output S ₂ of the analog signal delay circuit 3, and both input signals
This figure shows a level determination circuit that outputs a detection signal S ₃ when the absolute value of the difference between the instantaneous values of S ₁ and S ₂ is greater than or equal to a certain value.

The basic configuration of the present invention has been described above. Next, the functions of each component will be explained in detail.

(a) Analog Signal Delay Circuit The most suitable analog signal delay circuit 3 for use in the present invention is an element called a bucket brigade device (hereinafter referred to as BBD). As shown in FIG. 5, this element is composed of a large number of capacitors C, electronic switches S, and buffers B, and functions as an analog shift register. In other words, the analog signal _S1 applied to the analog signal input terminal is sampled in synchronization with the pulse _S4 applied to the control signal input terminal, and is shifted by one step for each control pulse before finally reaching the output terminal. is output to.

FIG. 6 is an example of signal delay caused by the BBD element, and shows the relationship with control signal input.

The time required for the signal _S1 applied to the analog signal input terminal to appear at the output terminal, that is, the delay time t of the analog signal _S1 , is determined by the number of internal steps of the BBD being M, and the period Δt of the pulse applied to the control signal terminal. Then, it is expressed as t=M×Δt=M/ _c ( _c is the frequency of the pulse).

BBD samples an analog quantity and delays it by shifting between internal capacitors C.
Therefore, if the sampling frequency is set sufficiently higher than the frequency of the input signal, it is possible to faithfully delay the input signal waveform regardless of the frequency components of the input signal waveform.

For example, if the frequency of the control pulse _S4 applied to the control signal input terminal is set to 1000 times the input signal frequency, the error due to sampling between the input and output waveforms will be 0.6% or less. This error can be further reduced by adding a simple low-pass filter to the BBD output terminal.

In addition, the number of internal steps for BBD is currently 128~
Various devices with 4096 steps are commercially available as ICs.

Examples of commercially available BBD elements include Matsushita Electronics' MN3205 (4096 steps) and
Examples include MN3001 (512 steps x 2 units).

(b) Control Signal Generating Circuit An example of the configuration of the control signal generating circuit 4 used in the present invention is shown in FIG. Figure 7 shows PLL (Phase
This is a modified example of the (Lock Loop) circuit, and is widely known as a circuit that outputs a signal _S4 having a frequency that is an integral number n times the input signal _S1 . In other words, by inserting the frequency divider 6 into the feedback loop of the PLL circuit, the comparison input of the phase comparator 7 is passed through the low-pass filter 8 to 1/n of the output frequency of the voltage controlled oscillator 9 (where n is It becomes the frequency of the frequency division ratio of the frequency divider 6).

As is widely known in the PLL circuit, the entire system is controlled so that the comparison input signal has the same frequency and phase as the reference input signal input to the phase comparator.

Therefore, when the frequency of the reference input signal _S1 is set to ₀ , the output frequency of the frequency divider 6 is also controlled to be ₀ , and as a result, the output of the voltage controlled oscillator 9 is synchronized with the input signal and has a frequency is an integer multiple (n ₀ )
A signal with a frequency of is obtained. The above is an explanation of the basic operation of the circuit shown in FIG.

Next, the functions of the control signal generation circuit 4 shown in FIG. 7 will be described.

The first function is to output a signal with a frequency proportional to the frequency of the input signal, as described above. In FIG. 7, the frequency ratio between the input signal and the output signal is equal to the frequency division ratio of the frequency divider 6, which is 1/2×L times the internal step number M of the analog signal delay circuit 3 described above (L is an integer). is set to

The second function is that when the frequency of the input signal changes, the output of the control signal generation circuit quickly follows the change in the frequency of the input signal. As a result, even when the frequency of the relay input electricity varies due to system oscillation or the like, the output frequency of the control signal generation circuit 4 changes almost faithfully following the frequency of the input signal.

In addition, when the reference input signal is zero without inputting the grid electricity amount, the control signal generation circuit 4 generates a signal of a frequency close to the frequency that oscillates when the normal grid frequency is input.

Furthermore, the control signal generation circuit 4 shown in FIG.
is a commercially available PLL IC (for example, Signetics)
NE565, etc.), a frequency dividing IC (for example, Tokyo Shibaura Electric, TC4521, etc.), some capacitors, and resistors can be easily configured.

(c) Level Judgment Circuit FIG. 8 shows an example of the configuration of the level judgment circuit 5 used in the present invention. In FIG. 8, 10 is the input S ₁ and S ₂ of this level determination circuit.
11 is an absolute value calculator that takes the output of the subtracter 10 as an input and outputs its absolute value. 12 takes the output of the absolute value calculator 11 as an input, and the above When the input reaches a preset level √2ΔI or higher, a detection signal is generated.
This is a level detector that outputs _S3 .

FIG. 9 shows the operation of the level determination circuit 5 shown in FIG. 8.

In FIG. 9, A and B indicate the input amounts S ₁ and S ₂ applied to the subtracter 10, and C indicates the level difference output between the inputs A and B calculated by the subtracter 10. The level difference signal C output from the subtracter 10 is input to the absolute value calculator 11 and rectified as shown in d.
2 is input.

The level detector 12 outputs a detection signal shown as e as _S3 when the input signal exceeds a preset level √2ΔI.

By the above operation, the level determination circuit 5 of FIG.
detects the difference between the instantaneous values of input signals S ₁ and S ₂ ,
The difference is a preset value √2 regardless of polarity.
It has a function of outputting a detection signal _S3 when the magnitude exceeds ΔI.

Next, the action of such a change width detection relay will be explained in the 10th section.
This will be explained using figures. In FIG. 10, A is the amount of system electricity input to the relay, B is the output of the analog signal delay circuit 3, C is the instantaneous difference between A and B,
d indicates the output of the level determination circuit 5, respectively.

First, a case where the system is in a steady state and the relay input electricity is a constant sine wave (section t ₀ to t ₁ ) will be described.

Now, if the frequency of the input quantity of electricity is ₀ and the frequency ratio between the input and output of the control signal generation circuit 4 is n, then a control signal with a frequency of _n0 is output from the control signal generation circuit 4 to control the analog signal delay circuit 3. Applied to the signal input terminal. Since the delay time of the delay circuit of the analog signal delay circuit 3 is inversely proportional to the frequency of the control signal as described above, the delay time t is expressed as in the following equation.

t=M/c=M/n ₀ (Here, M is the number of internal steps of the analog signal delay circuit 3, and c is the frequency of the control signal.) Here, as an example, set the device so that M=n. If configured, t=1/ ₀ ≡T ₀ , and the delay time of the analog signal delay circuit 3 becomes equal to the period of the input electric quantity. That is, the configuration shown in FIG. 4 allows the analog signal delay circuit 3 to output a signal one cycle before the input electrical quantity, regardless of the frequency of the input electrical quantity. Therefore, even if the frequency of the input electrical quantity fluctuates due to system fluctuations, etc., the phase difference between the output signal of the analog signal delay circuit 3 and the relay input electrical quantity is always controlled to 0°.
There is no difference in instantaneous values between the inputs of the level determination circuit 5, and the level determination circuit 3 does not determine that it is operating.

Next, consider a case where a failure occurs in the grid at time _t1 in FIG. 10 and the relay input from the grid suddenly changes. In this case, of the two signals input to the level determination circuit 5, the input electric quantity A changes immediately, whereas the input B from the analog signal delay circuit 3 is a signal one cycle earlier. It doesn't change because it exists. Therefore, a difference corresponding to the change occurs in the difference C between the instantaneous values of A and B, and when that value becomes larger than the preset judgment level √2ΔI,
The level determination circuit 5 determines the operation and outputs a detection signal d to the outside.

As mentioned above, this change width detection relay can prevent large fluctuations in operating values and malfunctions when the frequency of the grid changes, and at the same time, it can reliably detect sudden changes in the phase or amplitude of the input electrical quantity. It is possible to do so. Additionally, one of the effects of this relay is that there is little change in characteristics due to changes in the constants of the relay components. In other words, because the resonant circuit used in conventional current change width relays has a high Q, the phase and amplitude of the output signal will increase if there is a slight change in the constant of the circuit elements that make up the resonant circuit. Change. For this reason,
There was a risk that the characteristics of the relay would fluctuate greatly due to changes in ambient temperature or changes over time, but with this relay, the phase difference between the two signals input to the level judgment circuit 5 is always 0°. Since it is corrected, it is hardly affected by changes in circuit constants, and it is possible to obtain a relay with extremely stable characteristics.

Note that the present invention is not limited to the above embodiments.

(a) In the above embodiment, the delay of the input signal by the analog signal delay circuit is explained as one period, but this is not limited to this, and the same applies if the delay time is a multiple of 1/2 period. Applicable. The configuration when this delay time is an even multiple of 1/2 period is exactly the same as that shown in FIG. In addition, when the delay time is set to an odd multiple of 1/2 period, the output of the analog signal delay circuit 3 has a phase difference of 180 degrees from the input signal, so the change component is the output of the analog signal delay circuit 3 and the relay input. It is determined by the sum of the amount of electricity. In this case, the eighth
Instead of the subtracter 10 in the figure, an adder that calculates the sum of the relay input signal and the output of the analog signal delay circuit 3 may be used.

According to this configuration, the relay according to the present invention can be constructed by only delaying the input signal by at least 1/2 period, so that the analog signal delay circuit 3 having a small number of internal steps can be used.

(b) In the control signal generation circuit 4 shown in Fig. 7, a PLL oscillator including a 1/2 frequency divider in the loop is used to generate a control signal with a frequency proportional to the frequency of the input electrical quantity. However, this frequency divider can be omitted, and an example of its configuration is shown in FIG. In FIG. 11, the output of the analog signal delay circuit 3 is directly input to the comparison input terminal in the control signal generation circuit 4'.

In this configuration, the frequency of the control signal output by the voltage controlled oscillator 9 is set around the frequency at which the signal delay time by the analog signal delay circuit 3 is approximately one cycle of the input signal. Further, the input frequency of the voltage controlled oscillator 9 is controlled by the phase between the input signals of the phase comparator 7,
In FIG. 11, when the phase of the output signal of the analog signal delay circuit 3 input to the phase comparator 7 is delayed compared to the phase of the amount of electricity input from the grid, the oscillation frequency increases, and conversely, the phase changes. It is configured so that it decreases as it progresses.

As an example of the operation shown in FIG. 11, if the initial oscillation frequency of the voltage controlled oscillator 9 is the correct oscillation frequency M ₀
(M is the number of internal steps of the analog signal delay circuit 3, ₀ is the frequency of the relay input electrical quantity) will be explained below.

In this case, since the frequency of the control signal input to the analog signal delay circuit 3 is lower than the correct value,
The delay time increases accordingly. That is, the output signal of the analog signal delay circuit 3 is delayed by one period or more of the input signal, and a phase difference occurs between the input signals of the phase comparator 7. In this case, the output phase of the analog signal delay circuit 3 will be delayed compared to the input electrical quantity, and the output frequency of the voltage controlled oscillator 9 will increase.

As the oscillation frequency increases, the delay time of the analog signal delay circuit 3 becomes shorter and the phase delay becomes smaller.

The oscillation frequency continues to increase until the phase difference between the reference input and comparison input becomes 0°, and finally stabilizes when the delay time of the analog signal delay circuit 3 becomes equal to one cycle of the input electrical quantity. . Also,
Even when the initial oscillation frequency of the voltage controlled oscillator 9 is higher than M ₀ , the delay time of the analog signal delay circuit 3 becomes stable when it becomes equal to one period of the relay input electricity quantity through a process reverse to the above.

Due to the above-described operation, the delay time of the analog signal delay circuit 3 in FIG. 11 is always corrected by one cycle of the input signal regardless of changes in the input signal frequency or changes in the constants of the components, resulting in a simpler circuit configuration. The functions necessary for the present invention can be satisfied. Note that the frequency correction operation in FIG. 11 explained above is exactly the same as the principle of a known PLL oscillation circuit.

(c) FIG. 12 shows the configuration of an embodiment in which the present invention is applied to a relay with a plurality of current change widths input from a power system. The frequency of input electricity from a system is almost the same regardless of the phase or observation point if the system is the same. Therefore, if the oscillation frequency of the control signal generation circuit 4 is generated based on one of the plurality of inputs, it can be similarly applied to other input quantities. In FIG. 12, analog signal delay circuits 3a, 3b, . . . , 3x that delay each input amount are collectively driven by a single control signal generation circuit 4.

According to this embodiment, only one control signal generation circuit 4 is required for a relay having a plurality of input electrical quantities, so that the circuit configuration can be simplified.

(d) FIG. 13 shows a configuration example when the present invention is applied to an actual variation range detection relay. In FIG. 13, 13 is a TDE element that prevents malfunction of the relay due to noise contained in the grid electricity amount, and 14 is a TDD element that stretches out and makes continuous the intermittent detection signal output from the level judgment circuit 5. . With the configuration shown in FIG. 13, it is possible to prevent unnecessary reactions due to relay noise, etc., and at the same time, it is possible to output a continuous relay operation signal to the outside when a failure is detected.

(e) In the embodiment described above, the level determination means functions as an overvoltage detection element, but it may function as an undervoltage detection element. In this case, the subtracter 8 in FIG. 8 may be replaced with an adder, the level detector 10 may be replaced with an undervoltage relay, and a not circuit for inverting the output of this undervoltage detector may be provided.

〔Effect of the invention〕

As explained above, according to the present invention, the relay itself can correct its operation according to the frequency of the amount of electricity input from the grid, thereby reducing the effects of frequency fluctuations in the grid and changes in temperature and aging of the relay itself. Therefore, it is possible to provide a change range detection relay that has extremely stable characteristics that are not affected by changes.

[Brief explanation of drawings]

Fig. 1 is a diagram showing the phase characteristics of a current variation width relay, Fig. 2 is a diagram showing a configuration example of a conventional current variation width relay, Fig. 3 is a diagram showing the operating principle of a conventional current variation width relay, 4 is a configuration diagram showing an embodiment of the present invention, FIG. 5 is a diagram showing an example of the configuration of an analog signal delay circuit of the present invention, and FIG. 6 is a diagram for explaining the operation of the analog signal delay circuit. 7 is a diagram showing an example of the configuration of the control signal generation circuit, FIG. 8 is a diagram showing an example of the configuration of the level determination circuit, FIG. 9 is a diagram for explaining the operation of the level determination circuit, and FIG. The figure is a diagram for explaining the operation of an embodiment of the present invention.
FIGS. 11 to 13 are configuration diagrams showing other embodiments of the present invention. 1... Resonance circuit, 2, 5... Level judgment circuit,
3... Analog signal delay circuit, 4... Control signal generation circuit, 6... Frequency divider, 7... Phase comparator, 9...
... Voltage controlled oscillator, 10 ... Subtractor, 11 ... Absolute value calculator, 12 ... Level detector, 13 ...
TDE, 14...TDD.

Claims (1)

[Scope of Claims] 1. In a change width detection relay that receives as input the amount of electricity in a power system and detects a system failure by detecting that the amount of electricity in the system has changed by a certain value or more, the amount of electricity in the system is inputted. control signal generating means for outputting a control signal having a frequency corresponding to the frequency of the grid electricity amount; an analog signal delaying means for delaying the output by a certain amount of time; and a level for inputting the output from the analog signal delaying means and the above-mentioned system electrical quantity, and detecting that a composite value of the instantaneous values of both deviates from a predetermined range. What is claimed is: 1. A variation range detection relay comprising: determination means. 2. The variation range detection relay according to claim 1, wherein the control signal generating means is constructed by inserting a frequency dividing circuit into a feedback loop of a PLL oscillation circuit. 3 In claim 1, the control signal generating means is a reference input, and the delayed output of this input electrical quantity by an analog signal delay circuit is a comparison input.
A change width detection relay constructed from a PLL (Phase Lock Loop) oscillation circuit. 4. In any one of claims 1 to 3, the control signal generating means:
A variation range detection relay configured to supply control signals in parallel to a plurality of analog signal delay means for delaying a plurality of system electrical quantities. 5. In the device set forth in claim 1, the level determining means is configured to detect that the difference between the amount of electricity in the system and the amount of electricity output from the analog delay circuit becomes equal to or greater than a predetermined value. A change width detection relay featuring: 6. In the item set forth in claim 1, the level determining means is configured to detect that the sum of the system electrical quantity and the electrical quantity output from the analog delay circuit deviates from a predetermined range. Characteristic variation range detection relay.