JPH0160766B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit pattern inspection apparatus for inspecting minute circuit patterns formed on photomasks, printed circuit boards, and the like.

A comparative inspection method that compares circuit patterns of the same shape (in some cases, one pattern is a standard pattern based on design values) and detects mismatches when inspecting circuit patterns formed on photomasks, printed circuit boards, etc. is an effective test method. However, this conventional comparative inspection method has a drawback in that it is difficult to detect defects that are less accurate than the alignment accuracy of the two circuit patterns.

The purpose of the present invention is to eliminate the drawbacks of the above-mentioned prior art,
When comparing and inspecting two fine circuit patterns that should be the same, this circuit has a small memory capacity and a simple circuit configuration that enables high-precision detection of defects with alignment accuracy in real time. To provide a pattern inspection device.

That is, in order to achieve the above object, the present invention provides a plurality of imaging devices that image each of a plurality of originally identical circuit patterns, and a plurality of imaging devices that convert video signals obtained from each of the imaging devices into binary signals. The binarization circuit of
The direction edge detection logic circuit detects n X-direction edges in the Y direction indicated by different binary signals in the X direction, and converts the X-direction edge binary signals into m consecutive picture elements in the X direction. At the same time, in the local area, the Y-direction edge detection logic circuit detects n Y-direction edges in the X direction indicated by different binary signals in the Y direction, and converts the Y-direction edge binary signal in the Y direction. A plurality of edge detection circuits are used to extract m continuous picture elements from each edge detection circuit, and X-direction edge binary signals consisting of m continuous picture elements cut out from each of the edge detection circuits are shifted in pixel position. Compare and count over a plurality of scanning lines imaged by the imaging device to create a frequency distribution of the amount of edge position deviation in the X direction of both circuit patterns, and determine the amount of position deviation in the X direction indicating the maximum value. Y-direction edge binary signals consisting of m continuous picture elements extracted from each of the edge detection circuits are compared with each other by shifting the picture element positions, and counting is performed over a plurality of scanning lines imaged by the imaging device. A positional deviation extraction circuit which creates a frequency distribution of edge positional deviation amounts in the Y direction of both circuit patterns and calculates the Y direction positional deviation amount indicating the maximum value, and a binary value obtained from each of the above-mentioned binarization circuits. a plurality of positional deviation correction circuits for performing shift correction on each binary image extracted by the shift register group based on the amount of positional deviation in the X direction and the amount of positional deviation in the Y direction obtained by the positional deviation extraction circuit; , and a determination circuit that compares the binary signals obtained from each of the positional deviation correction circuits to determine a mismatch and performs the inspection. That is, in photo masks, printed circuit boards, etc., fine circuit patterns are drawn using a pattern generator or the like, and then formed by etching. However, the circuit pattern is formed with minute differences in parts due to defocus of the pattern generator, variations in etching conditions, thermal expansion of the substrate, and the like. Therefore, the present invention is to set the maximum value of the frequency distribution of the edge positional deviation amount of the two circuit patterns as the positional deviation amount of the two circuit patterns.

The present invention will be specifically described below based on embodiments shown in the drawings. 1 is a schematic configuration diagram showing an embodiment of an apparatus for carrying out a circuit pattern inspection method of the present invention. X table 103a, Y table 103b,
Originally the same circuit pattern 10 is on the X/Y/θ table 103 composed of the θ table 103c.
A photomask 100 having a large number of numbers 1 and 102 formed in the X and Y directions is placed. circuit pattern 101,
Imaging devices 1 and 2 are provided above the photomask 100 and are capable of capturing images of the photomask 102, respectively, and are equipped with objective lenses 1a and 2a and image sensors 1b and 2b. By the way, the photomask 100 is placed on an
When observed, the above circuit patterns 101 and 102
The optical images of the two are superimposed and formed. Therefore, if there is a large positional deviation in the rotational direction between the circuit patterns 101 and 102, the θ table 103c is manually rotated so that both circuit patterns 101 and 102
The optical images of 1 and 102 are combined. In addition, if there is a large positional shift in the X or Y directions, manually move one of the imaging devices 1 to the base (not shown) that supports this imaging device 1 using the feed screw in the X or Y direction. The light images of both circuit patterns 101 and 102 are brought into alignment by slight movement via a mechanism or the like. In the above embodiment, alignment was performed manually, but an image sensor is provided above the eyepiece, and a video signal obtained from this image sensor is used to
By determining the positional deviation of the simple line patterns formed on the edges of both circuit patterns 101 and 102 and feeding them back to the motor that drives the θ table 103c and the motor that drives the imaging device 1 in the X and Y directions, both circuits can be The optical image of the pattern can be automatically aligned. In addition, the objective lenses 1a, 2a and the circuit patterns 101, 102 are arranged in the imaging devices 1, 2 so that the optical images of the circuit patterns 101, 102 are properly and automatically formed on the light receiving surfaces of the imaging elements 1b, 2b. The image pickup devices 1 and 2 are each moved in the Z direction so that the distance is measured in a non-contact manner using an air micrometer or the like, and the distance is kept constant. That is, the imaging device 1,
Although not shown in FIG. 2, a circuit pattern 101,
102, each of which can be automatically focused. However, even if the optical images of a certain circuit pattern 101 and a certain circuit pattern 102 can be aligned in this way, it is not possible to completely align the positions of all the circuit patterns, and slight positional deviations occur. One of these 1
Mechanical alignment as described above is time consuming and inefficient. Therefore, the above initial alignment is performed only when a new photomask 100 to be inspected is placed on the X/Y/θ table 103, and thereafter all circuit patterns are obtained from the imaging devices 1 and 2 as described below. Electrically aligns the video signal.

That is, 3 and 4 are binarization circuits that binarize the video signals obtained by 1 and 2, and output binarized signals 5 and 6. 7 and 8 are edge detection circuits that input the binary signals of 5 and 6, respectively, and detect the edges of the two images in the X and Y directions. Positional deviation in the X and Y directions of images 5 and 6 (limitation of mechanical alignment at the start of inspection, or difference between the two imaging systems (difference in illumination intensity, difference in sensitivity of the imaging device, etc.) or photomask) This is a positional deviation extraction circuit that extracts the cause of the positioning accuracy of the stage on which the objects 100 and 101 are placed. 11 and 12 are positional deviation correction circuits that correct the positional deviations of 5 and 6 based on 10, 13 is a judgment circuit that inputs the corrected binary signal and makes a judgment, and 14 is a judgment result. be. Below, the amount of positional deviation in the X and Y directions is maximum ±
This will be explained as two picture elements. FIG. 2 shows a specific configuration for detecting edges in the X direction at points 7, 8, and 9 and extracting the amount of positional deviation. Reference numerals 15 and 15' surrounded by broken lines in FIG. 2 have exactly the same configuration, and are edge position extraction circuits that input 5 and 6, respectively, and extract edges in the X direction. 16 is a shift register corresponding to the length of the scanning line, 17 is a binary signal 5
16, the local area of 2×2 pixels is scanned by the imaging device (linear image sensor) of the imaging device, and the X table 103a and Y table 103
It is a local memory that sequentially stores data in synchronization with the scanning of b, and is composed of a serial-in-parallel-out shift register. 18, 19, and 20 are EXOR circuits, 21 is a NAND circuit, and 22 is an AND circuit, which outputs "1" when the contents of the local memory are in the state shown in FIG. 23 is a serial-in-parallel-out shift register; 15, 1
5' outputs 23 three outputs. These outputs are 24, 25, 26, 24', 25', 26',
and 27, 28, 29, 30, 31 are comparators, 3
If 2, 33, 34, 35, and 36 are counters, 27 detects that both 26 and 24' are "1", that is, 5 is ahead of 6 by +2 picture elements in the X direction. Similarly, 28, 29,
30 and 31 are respectively 5 + 1 picture element, 0 picture element,
A state in which -1 picture element or -2 picture element is ahead (- means delayed) is detected. Then, the frequency of that state is counted by counters 32 to 36, and by detecting the maximum value of 32 to 36,
Find the positional shift in the X direction. 37 is a maximum value detection circuit which detects the maximum value of 32 to 36 and outputs a positional deviation value 38 indicating the maximum value. Furthermore, as shown in FIG. 3, the reason why edges are judged based on the state of 2×2 picture elements in edge extraction in the X direction is to reduce the influence of quantization errors caused by binarization. FIG. 4 shows a specific configuration for edge detection and displacement amount extraction in the Y direction. In FIG. 4, 39 and 39' surrounded by broken lines have exactly the same configuration, and are edge position extraction circuits that input 5 and 6, respectively, and extract edges in the Y direction. 40 is a group of shift registers each corresponding to the length of a scanning line;
2 of the local area of 2 × 4 pixels in the local memory of 41
The value images are sequentially stored in synchronization with the scanning of the imaging device. 42-48 are EXOR circuits, 49-5
1 is a NAND circuit, 52 to 54 are AND circuits, and when the 2×2 pixel state shown in FIG. 5 occurs in the 2×4 pixel local memory of 41, 52,5
3 and 54 as outputs. These outputs are 55, 56, 57, 55', 56', 5
7' and comparators 58, 59, 60, 61, 62
Enter. 58, 57 and 55' are both "1"
, that is, a state in which 5 is ahead of 6 in the Y direction by +2 picture elements is detected.

Similarly, for 59, 60, 61, and 62, each 5 is +1 pixel, 0 pixel, -1 pixel in the Y direction from 6,
- Detects a state in which 2 picture elements are advanced. 58-62
The outputs of are input to the counters 63 to 67 as in the case of FIG. 2, the outputs of 63 to 67 are input to the maximum value detection circuit 68, and the amount of positional deviation 69 in the Y direction is extracted.

Next, the positional deviations of 5 and 6 are corrected based on the amount of positional deviation of 38 and 69, and the inspection sheet is run.
The specific configurations of Nos. 2 and 13 will be explained using FIG. In FIG. 6, 70, 71, 72, and 73 are shift registers corresponding to the length of the scanning line;
Both 4 and 75 are selection circuits that use 69 as a selection signal. Input 74, 75 to 76, 77, 78,
79, 80, 81, 69 is 5 is more than 6
When indicating an advance of 2 pixels, +1 pixel, 0 pixel, -1 pixel, -2 pixel, 74, 75 are (78, 79), (77, 79), (76 ,7
9), (76, 80), and (76, 81) are selected, and the positional deviation in the Y direction is corrected. The outputs of 74 and 75 are inputted to selection circuits 86 and 87 using 38 as a selection signal via a 1-bit shift register 82 and an 832-bit shift register 84 and 85. 86, 87
So, when 38 indicates that 5 is ahead of 6 by +2 pixels, +1 pixel, 0 pixel, -1 pixel, -2 pixel, the output is (84, 75), (82, 75) ,
A combination of outputs (74, 75), (74, 83), and (74, 85) is output to correct positional deviation in the X direction. The two binarized signals 88 and 89 after correction are
The EXOR circuit 90 detects a mismatch. Generally, when a video signal is binarized, a quantization error occurs, so even after correcting the positional shift, the quantization error simply causes
Test judgment cannot be made by performing EXOR and detecting a mismatch. Therefore, in the present invention, when a mismatch of 2×2 picture elements or more is detected, it is determined to be a defect. The output of 90 passes through a shift register 91 corresponding to the length of the scanning line, and the output of 2 is formed by a serial-in-parallel-out shift register.
It is sequentially stored in the local memory 92 of ×2 picture elements. 9
The output of 2 is input to an AND circuit 93, and the defect determination signal 14 is generated only when a mismatch is detected in all the local memories of 2×2 picture elements.

Here, the timing for correcting positional deviation will be described. The operation timing of the maximum value detection circuits 37 and 68 generally does not need to be performed all the time. This is because misalignment does not occur suddenly;
It happens gradually. Therefore, maximum value detection is performed every n scanning lines (n is the set value).
32-36, 63-6 each time maximum value detection is performed.
Make sure to clear the counter of 7. Also, if the maximum value obtained by maximum value detection is too small, it means that there are few edges, and it becomes difficult to accurately correct the positional deviation. , 63-67. That is, the maximum value is determined using n+Δn scanning lines.

With the configuration described above, it is possible to realize a method of performing comparative inspection while correcting positional deviation.

When circuit patterns 100 and 101, which are essentially the same and are formed on a photomask, a printed circuit board, etc., are imaged by the positioned imaging devices 1 and 2, the images are taken in the form shown in FIG. 7.
By the way, since the circuit patterns 100 and 101 are drawn by a pattern generator and formed by etching, they are partially formed to have slightly different dimensions depending on drawing conditions, etching conditions, etc. Therefore, the distance between the edges in the X direction △
X ₁ , △X ₂ , △X ₃ , △X ₄ , △X ₅ , △X ₆ , △X ₇ may be different, and the distance between the edges in the Y direction △Y ₁ , △Y ₂ , △ Y ₃ , △Y ₄ , △Y ₅ , △Y ₆ ,
△Y ₇ may also be different. Based on this, the true relative positional deviation between the two circuit patterns can be determined by determining the maximum value of the frequency distribution of the distance between edges.
Then, by correcting the true relative positional deviation amount binary signal obtained in this way and comparing the two binary signals, it is possible to inspect minute defects smaller than the positional deviation amount.

As explained above, according to the present invention, the problem of positional deviation between images of two circuit patterns to be compared, which is the key to comparative inspection, can be solved, and positional deviation can be detected in real time with a simple circuit configuration and excellent performance. It is possible to obtain an apparatus capable of inspecting minute defects of less than 100 mL, which has excellent practical effects.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the overall configuration of the present invention, FIGS. 2 and 4 are diagrams showing specific examples of the edge detection circuit and positional deviation amount extraction circuit shown in FIG. 1, and FIGS. A diagram for explaining edge detection, FIG. 6 is a diagram showing a specific example of the positional deviation correction circuit shown in FIG. 1, and FIG. 7 is a circuit pattern imaged by each of the two imaging devices shown in FIG. 1. FIG. 3 is a diagram showing a state in which . 1, 2...imaging device, 3, 4...binarization circuit, 7,
8... Edge detection circuit, 9... Positional deviation extraction circuit, 1
1, 12... Positional deviation correction circuit, 13... Judgment circuit,
100...Photomask, 101, 102...Circuit pattern, 103...X/Y/θ table.

Claims (1)

[Claims] 1 A plurality of imaging devices that image each of a plurality of circuit patterns that are essentially the same, and a plurality of two-dimensional imaging devices that convert video signals obtained from each of the imaging devices into binary signals.
2 obtained from each of the digitization circuit and the binarization circuit.
The digitized signal is cut out into a local area consisting of n×n picture elements by a shift register, and in the local area, an X-direction edge detection logic circuit displays n pieces in the Y-direction as different binary signals in the X-direction. The X-direction edge is detected and the X-direction edge binary signal is cut out as m consecutive picture elements in the X direction, and the Y-direction edge detection logic circuit cuts out the X-direction edge binary signal as m consecutive picture elements in the X direction. Detects Y-direction edges indicated by binary signals that differ in the direction and
A plurality of edge detection circuits that cut out a direction edge binary signal as m continuous picture elements in the Y direction, and an X direction edge binary signal made up of m continuous picture elements cut out from each of the edge detection circuits. A frequency distribution of the amount of edge position shift in the X direction of both circuit patterns is created by comparing the same pixels by shifting the pixel positions and counting over multiple scanning lines captured by the above-mentioned imaging device, and showing the maximum value. The imaging device captures an image by determining the X-direction positional shift amount and comparing the Y-direction edge binary signals made up of m continuous picture elements extracted from each of the edge detection circuits with the pixel positions shifted. A positional deviation extraction circuit that counts over a plurality of scanning lines to create a frequency distribution of edge positional deviations in the Y direction of both circuit patterns, and obtains the Y-direction positional deviation amount that indicates the maximum value; Shift correction is performed on each binary image extracted from the binary signal obtained from each circuit by the shift register group based on the amount of positional deviation in the X direction and the amount of positional deviation in the Y direction determined by the positional deviation extraction circuit. A circuit pattern inspection device comprising: a plurality of positional deviation correction circuits; and a determination circuit that compares binarized signals obtained from each of the positional deviation correction circuits, determines a mismatch, and performs an inspection. .