JPH0160862B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data transfer method, and specifically to a data transfer method useful in data transfer between devices having different data rates. Recently, with the development of LSI (Large-Scale Integrated Circuits) and microcomputers, system prices have come down significantly. For this reason, a method has been considered in which inexpensive microprocessors are functionally assigned and connected and are operated systematically. That is, a dedicated microprocessor is used for arithmetic control and input/output control, and its software instructions are used to perform device-specific exchanges. Therefore, it is necessary to coordinate the coupling and operation between these multiple microprocessors. The present invention has been made in view of the above-mentioned needs, and uses a buffer device having a certain degree of intelligence in data transfer between a high-speed processor and a relatively low-speed peripheral device. The purpose of this invention is to provide a data transfer method that adjusts rate differences (absorbs processing speed differences). On the other hand, even if two devices can operate at the same data rate, they may not always be able to operate synchronously. Therefore, another object of the present invention is to provide a data transfer system that has the necessary data buffering function and can perform efficient processing even in such a case. The feature of the present invention is that FIFO (First-in-First-
out) has a relatively large capacity, e.g.
By using a 128-byte x 8-bit FIFO type buffer memory, data transfer between two devices can be performed simultaneously at the speed of each device. This aims to improve the throughput of the system. For example, a DMA device that performs high-speed data transfer executes high-speed block transfer to bring the FIFO buffer to the FULL state,
This means that a peripheral device that is relatively slower than this FIFO buffer can read data at the data rate of the device. Hereinafter, the present invention will be explained in detail using the drawings. FIG. 1 shows an embodiment of a data transfer device in which the present invention is implemented. In the figure, 100 is a FIFO buffer control circuit (hereinafter referred to as
(referred to as FIFC). This FIFC 100 is a floppy disk controller (hereinafter referred to as FDC20), which is a dedicated processor for floppy disk devices.
DMA device (hereinafter referred to as DMA device) that performs high-speed data transfer between
DMA 300). It is assumed that the transfer between the blocks ( 100 , 200, 300) is performed by a conventional two-wire handshake as described later. In the diagram, DRQ is FIFC
DACK is a data request signal issued from 100 to DMA 300, and DACK is a data request signal issued from DMA 300 to
This is an acknowledge signal issued from 300.
Further, HRQ is a hold request signal issued from the DMA 300 to the CPU (not shown), and CACK is an acknowledge signal obtained from the CPU in response to this. Due to this hold request, the bus owned by the CPU becomes in a floating state, and during this time the DMA3
0 or the bus can be occupied. On the other hand, DAT is 8 between FIFC 100 and FDC200.
The bit data transfer bus, FDRQ, is a data request signal issued from the FDC 200 to the FIFC 100 .
FACK is an acknowledge signal issued from the FIOC 100 in response to the FDRQ signal. Also, SWD
is serial write data issued to a floppy disk device (not shown), and SRD is serial read data obtained from the floppy disk device. FIG. 2 is a circuit diagram showing the internal configuration of the FIFC in FIG. 1. As is clear from the figure, FIFO
100 is mainly provided for WRITE buffer
FIFO buffer 11, FIFO buffer 12 provided for READ buffer, 8-bit parallel bidirectional bus driver 13, FIFO length counter 1
4. Mode setting flip-flops 15, 16, various gates, and flip-flops (hereinafter referred to as gate groups 17 , 18 , 19 ). The data output Q of the FIFO buffer 11 is supplied to the data input terminal DI of the bidirectional bus driver 13. The data output terminal O is connected to the data input terminal D of the FIFO buffer 12. The CS (chip select) input of the bidirectional bus driver 13 is the OR output of the outputs of mode flip-flops 15 and 16, which will be described later. 15 outputs are provided. Incidentally, a data transfer length is set in the FIFO length counter 14 by software. Applicable
The FIFO length counter 14 is decremented each time data is transferred, and is set to a certain value (for example, "0").
When this happens, a data transfer end instruction TC is given to the FDC 200. Also, each of the mode flip-flops 15 and 16 is set to write mode WRITE and read mode by the same software.
Either READ is set. The Q outputs of these flip-flops 15 and 16 are supplied to a gate group 17 and a gate group 18 , respectively, and the outputs are supplied to a gate group 19 . Also, flip-flop 15
The output of DIEN of the bidirectional bus driver 13 is
Supplied to the terminal. On the other hand, the inputs and outputs in the FIFO buffers 11 and 12 operate asynchronously, and when the input ready (hereinafter referred to as IR) signal is active,
The first shift-in (hereinafter referred to as SI) signal
input to the byte location. At this time, if the second byte location is empty, the data is transferred to the second byte location. When the data is transferred to the final byte location (128th byte), the output ready (hereinafter referred to as OR) signal becomes active and the shift out SO
It is output as a signal. Of the various signal lines, only those related to the operation of the present invention are defined in the operation column. The operation of the present invention will be explained in detail below.
Before that, we will briefly describe how to operate the firmware used in the present invention. First, after resetting the contents of the FIFO buffers 11 and 12, the address length and operation mode of the DMA 300 are set. next
Set the command to FDC2 and set the FIFO length and FIOC 100 operation mode to FIFO respectively.
length counter 14, flip-flop 15,
By setting the flag to 16, data transfer is thereafter performed according to the two-wire handshake control procedure. The value indicated by the FIFO length counter 14 is “0”
TC (Terminal) for FDC200
Count) signal is output, and the FDC 200 issues an interrupt signal to interrupt the firmware. After resetting the contents of the mode flip-flops 15 and 16, the firmware performs result processing on the FDC 200. The write sequence for the operation of the present invention is as follows:
The explanation will be divided into read sequences. Definitions of signal names related to the present invention will also be explained. The write sequence will be explained first. By activating the IR of FIFO buffer 11,
is the Q output of mode flip-flop 15.
The condition with the FFDWM signal is satisfied, and as a result, the DRQ signal is output to the DMA 300.
The DMA3 issues a HOLD request to the CPU to obtain the right to use the bus, reads data from the main memory, and sends the data to the data line DDAT.
At the same time, the synchronization signal DMSYN becomes active,
The data on the DDAT is input to the FIFO buffer 11. The data transferred to the first byte location of the FIFO buffer 11 is sequentially moved to the final byte location. After that, according to the above procedure, the DMA 300 reads data from the main memory,
Data transfer to FIFO buffer 11 is repeated. When data moves to the final byte location in the FIFO buffer 11, the DWBOR signal, which is the OR output, becomes active, and at this time,
When the FDRQ signal (active) arrives from FDC200, the gate condition is met and the shift out signal
DWBSO is supplied to the SO terminal of the FIFO buffer 11. When this DWBSO signal is input, the data at the 128th byte location of the FIFO buffer 11 is output to the data bus FDAT. This FDAT
The above data is output to the data bus DAT via the bidirectional bus driver 13. At this time, the transfer direction is determined by the signals input to CS and DIEN of the bidirectional bus driver 13, but in this case, since the mode flip-flops 15 and 16 are instructing WRITE, data is not transmitted to the FDC2. Writing is performed. In addition, the shift out signal of FIFO buffer 11
DWBSO and the shift-in signal DRBSI of the FIFO buffer 12, which will be described later, are the basic clock of the CPU |S
Sampled by CKCPU. or,
The DWBSO signal becomes a write signal to the FDC 200. At this time, the FDC200 emits
The FACK signal, which indicates permission for the FDRQ signal, also becomes active. After that, in order to receive the data request FDRQ from the FDC 200, the shift out signal DWBSO of the FIFO buffer 11 becomes active and the FDC 20
Data written to 0 is output. Next, the read sequence will be explained. Since the read operation is almost the opposite of the write operation described above except that the Q output of the mode flip-flop 16 is enabled, detailed explanation will be omitted. Read operation is FDC
Every time a data request FDRQ arrives from 200
Only when the IR of FIFO data 12 is active, the DRBSI signal becomes active.
Data is input to this FIFO buffer 12. When the OR of FIFO buffer 12 becomes active, a data request (DRQ) is sent to DMA300.
signal). Obtained from DMA300
Due to the DACK signal, the AND condition is satisfied and the shift-out signal DRBSO becomes active. Data transfer with the DMA 300 is thereby performed. This data transfer is performed asynchronously with the data request from the FDC 200. By the way, the end of the above read/write operation is
The borrow signal of the FIFO length counter 14 (TC signal output from the B terminal) becomes active,
This is done by supplying a TC (Terminal Count) signal to the FDC 200. In each operation, the input and output of the FIFO buffers 11 and 12 operate asynchronously, so in a device with a slow data rate, that is, in the embodiment of the present invention, it is necessary to recognize the number of executed bytes on the FDC 200 side. The FIFO length counter 14 is set to the same value as the transfer length of the DMA 300 by the firmware at the start of the read/write operation. This FIFO length counter 14 is updated (-1) during write operation.
FIFO buffer 11 shift out signal DWBSO
This is performed at the timing when the shift-in signal DRBSI of the FIFO buffer 12 becomes active during the read operation. As explained above, according to the present invention, the following effects can be obtained. (1) Two-wire handshake allows data transfer, and data transfer between devices operating at different speeds can be effectively realized. (2) A device in which the present invention is realized by a DMA device
Data transfer between the FIFC and main memory can be performed every machine cycle, eliminating inefficient transfer sequences in which data must be read from an input/output device and then written to main memory. (3) The DMA device supplies memory addresses and read/write information, and the FIFC of this device sends and receives data, allowing DMA transfer to be performed simultaneously on both sides. According to this method, read/write data transfer with the main memory can be performed at almost the highest bandwidth of the bus. This means that communication with input/output devices is
This means reducing the amount of time the bus is occupied, and is a factor in improving system throughput. According to the embodiment of the present invention, only data transfer between a DMA that performs high-speed block transfer and a low-speed input/output device has been described, but the present invention can also be applied to data transfer between DMAs or between input/output devices. In the former case, the FIFO length counter described above becomes unnecessary, and in the latter case, two FIFO length counters that recognize the data transfer length of both input/output devices are required.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a data transfer device in which the present invention is implemented, and FIG. 2 is a circuit diagram showing the internal configuration of the FIFO buffer control circuit in FIG. 1. 100 ...FIFO buffer control circuit, 2
00...Floppy disk controller, 300
...Direct memory access controller, 11
...Write FIFO buffer, 12...Read FIFO buffer, 13...Bidirectional bus driver, 14...
FIFO length counter, 15, 16...Mode flip-flop, 17 , 18 , 19 ...Gate group.

Claims (1)

[Claims] 1 A device that controls data transfer between devices with different data rates, and the device has independent read/write ports provided for buffering transfer data between the devices.
a FIFO buffer memory, at least one flip-flop whose operating mode is externally set;
The data transfer length is set externally, and subsequent reading/
and at least one FIFO length counter whose value is updated every time a write operation is performed, and when it indicates a certain value, it gives an instruction to end the data transfer to one device that cannot recognize the execution data transfer length. The data transfer direction of this device is defined by the content indicated by the flip-flop, and the transfer data is buffered until the FIFO length counter indicates a certain value, and data transfer is executed between the devices by two-wire handshake. A data transfer method characterized by: