JPH0160985B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to an image signal correction device, and more particularly to an image signal correction device for white density and black density regions in an optical reading device using plane scanning for recorded information having halftones. .

[Technological environment]

An optical reading device for recorded information with halftones scans a continuous-tone photographic original using a laser beam, photoelectrically converts the light reflected from the original, and converts the white of the original into a high-voltage, black A low-voltage image signal is obtained.

In this case, it is well known that in the envelope of the image signal for each scanning line for white, the voltage is high in the middle part and low in the peripheral part due to the characteristics of the optical system.
This is the so-called shedding phenomenon.

Further, the dark current of the photoelectric conversion element changes depending on temperature, driving voltage, and aging, and this change in dark current changes the black voltage value.

Furthermore, some original images have a narrow black-and-white density change range, while others have a high density original mount, but in the photoelectric conversion process, all of these are converted into image signals with voltages corresponding to the density. The image signal is digitally converted to facilitate signal processing, but in this conversion process, it is necessary to remove the effects of the above-mentioned shading and dark current, and to correct the density range relative to the black and white of the original image, in order to achieve high-quality image reproduction. desirable for

[Prior art]

In a conventional image signal correction device, an upper reference voltage and a lower reference voltage are fixed to set values in an analog-to-digital conversion circuit that converts an analog signal read by scanning into a digital signal, and the upper reference voltage and lower limit reference voltage are fixed to set values. The voltage is divided into y-level judgment levels, and the supplied analog image signal is converted into a digital code according to the judgment level.

Therefore, if the highest voltage for white in the analog picture signal is lower than the upper limit reference voltage, or if the lowest voltage for black is higher than the lower limit reference voltage, the y-step resolution of the analog-to-digital conversion circuit cannot be obtained.

Next, the digitally encoded image signal is subjected to necessary correction using digital correction values based on the respective image signal correction elements described above. however,
When the analog-to-digital conversion is not resolved to y stages, the resolution cannot be improved by correction.

That is, although the conventional image signal correction apparatus incorporates a high-precision analog-to-digital conversion circuit, it has the disadvantage that it can only output an image with a lower level resolution than the resolution it has.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide an image signal correction device that can obtain a resolution equal to that of an analog-to-digital conversion circuit.

[Structure of the invention]

The configuration of the image signal correction device of the present invention is such that the determination level between the upper and lower limit voltages of the dynamic range is controlled by the upper and lower reference voltages, and an image signal obtained by photoelectrically converting the density information of the original image is input. an analog-to-digital conversion circuit that performs multi-value decomposition into the determination level corresponding to the level; and a first upper limit voltage whose upper limit reference voltage is equal to the image signal level of the white peak value corresponding to 100% reflectance, and the lower limit reference voltage. When the first lower limit voltage is equal to the image signal level of the black peak value corresponding to 0% of reflected light, the image signal corresponding to one scanning line obtained by scanning the reference white plate is converted into digital by the analog-to-digital conversion circuit. a first storage circuit that stores a white reference signal and reads it out at a predetermined period synchronized with scanning of the original image; the upper limit reference voltage is the first upper limit voltage, and the lower limit reference voltage is the first lower limit; a second storage circuit for storing a black reference signal obtained by digitally converting a photoelectric conversion voltage at zero incident light by the analog-to-digital conversion circuit and reading it out at the predetermined period; When the lower limit reference voltage is the first lower limit voltage at the upper limit voltage, a first white data signal corresponding to the image signal level of the white peak value is output, and the upper limit reference voltage is at the second upper limit voltage and the lower limit. When the reference voltage is a second lower limit voltage, image signals from a plurality of pixels obtained by scanning a specified white density region of the original image are converted into digital signals by the analog-to-digital conversion circuit.
a first extraction circuit for extracting a white data signal of the black peak value when the upper limit reference voltage is the first upper limit voltage and the lower limit reference voltage is the first lower limit voltage; A first black data signal is output, and when the upper limit reference voltage is the second upper limit voltage and the lower limit reference voltage is the second lower limit voltage, the specified black density area of the original image is scanned. a second extraction circuit for extracting a second black data signal obtained by digitally converting image signals from a plurality of pixels by the analog-to-digital conversion circuit; A first white correction signal, a second white correction signal, a first black correction signal, and a second black correction signal whose average values are obtained from the and second black data signals are stored, and the signal is stored at the predetermined period. an average value circuit that reads out the average value circuit, and adds the product of the difference between the black reference signal and the white reference signal and the first or second white correction signal to the black reference signal, and sets the result as the upper limit reference voltage in advance. The first upper limit voltage is determined from data corresponding to a reflectance of 100%, the first upper limit voltage is determined based on the first white correction signal, and the second upper limit voltage is determined based on the first white correction signal.
a white level tracking circuit that calculates a third upper limit voltage based on a white correction signal; and a white level tracking circuit that calculates a third upper limit voltage based on a white correction signal of the black reference signal; is added to the lower limit reference voltage, the first lower limit voltage is determined from data corresponding to a preset reflectance of 0%, the second lower limit voltage is determined based on the first black correction signal, and the second lower limit voltage is determined based on the first black correction signal, and the second lower limit voltage is determined based on the first black correction signal. and a black level tracking circuit for determining a third lower limit voltage based on the black correction signal No. 2, and corrects the image signal by using the third upper limit voltage and the lower limit voltage as the upper limit reference voltage and the lower limit reference voltage, respectively. do.

[Explanation of Examples]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, and the image signal modification device shown in FIG.
2, an average value circuit 3, a white level tracking circuit 4,
a black level tracking circuit 5, an analog-to-digital conversion circuit 6, a scanning circuit 7, a first storage circuit 9,
The second storage circuit 10 is configured to include the second storage circuit 10.

Below, the operation of the image signal correction device shown in FIG. 1 will be explained in detail with reference to FIGS. 2 to 9. 2 is a detailed block diagram of the extraction circuit 1 in the embodiment shown in FIG. 1, FIG. 3 is a detailed block diagram of the average value circuit 3 in the embodiment shown in FIG. 1, and FIG. 4 is shown in FIG. FIG. 5 is a detailed block diagram of the white level tracking circuit in the embodiment shown in FIG. 1. FIG. 6 is a detailed block diagram of the black level tracking circuit in the embodiment shown in FIG. 1. FIG. 6 explains the operation of the extraction circuit 1 shown in FIG. 7 is an explanatory diagram of the image signal extraction operation of the extraction circuit 1 shown in FIG. 2, and FIG.
9 is a waveform diagram for explaining the operation of the embodiment shown in FIG. 1, and FIG. 9 is an apparent waveform diagram for explaining the operation of the embodiment shown in FIG. 1.

[Setting operation of upper limit voltage and lower limit voltage]

During the preparation period prior to the start of scanning the original image, the main scanning start enable signal K is set to "low" in FIG. 1. Main scanning start enable signal K
is phase-inverted by an inverter 15, and an inverted main scanning start enable signal is supplied to a black level tracking circuit 5.

A 10-bit data input and a "low" scan start enable signal K are supplied to the NAND circuit 408 shown in FIG. Bit data is output. The latch 409 is a 1-bit delay circuit for bit alignment, and the output from the latch 409 is converted to an analog voltage amount by a digital-to-analog conversion circuit 410, and unnecessary frequency components are removed by a low-pass filter 411, and the output is converted to the upper limit reference voltage. Output as _VH .

At this time, the value of the upper limit reference voltage V _H is "V ₊ " volts, which corresponds to all the 10-bit digital codes shown in FIG. .

On the other hand, a 10-bit data input and a "high" inverted main scanning start enable signal are supplied to the NOR circuit 504 shown in FIG. be done.
All 10-bit data of "low" is latch 50
After being converted into an analog voltage amount by a digital-to-analog conversion circuit 506, it is outputted as a lower limit reference voltage _VL through a low-pass filter 507.

At this time, the value of the lower limit reference voltage V _L is such that all 10-bit digital codes shown in Figure 8 are "low".
This voltage value is the lower limit voltage of the analog _- to-digital conversion circuit 6.

[Generation operation of white reference signal and black reference signal]

Next, in FIG. 1, the scanning circuit 7 scans a reference white plate prior to scanning the original image, and supplies a white reference signal A _b in the photoelectric conversion signal A shown in FIG. 8 to the analog-to-digital conversion circuit 6. Scanning is performed using the synchronous clock _S2 from the synchronous clock generation circuit 16.
The scan period T shown in FIG.
is set to a predetermined value.

The analog-to-digital conversion circuit 6 has an upper limit reference voltage.
It has a judgment level divided into 256 levels with V _H and lower reference voltage V _L as the upper and lower limit voltages, respectively, and has the function of converting analog input voltage into an 8-bit digital code according to the judgment level. .

The analog-to-digital conversion circuit 6 has an upper limit reference voltage.
V _H is “V ₊ ” volts, lower limit reference voltage V _L is “V _- ”
volts, the white reference signal A _b is converted into an 8-bit digital white reference signal B _b in the digitally encoded signal B. The digital white reference signal B _b passes through the bus switching gate 8 and is stored in the memory circuit 9 for one scanning line.

After scanning the reference white plate, as a reference black, the output voltage from the photoelectric conversion element when the light source is turned off, that is, when the incident light to the photoelectric conversion element is zero, is obtained as the black reference signal A _d in the photoelectric conversion signal A shown in FIG.
Digitally encoded signal B is obtained through the same process as above.
An 8-bit digital black reference signal _Bd is stored in the memory circuit 10.

Next, for convenience of explanation, the operations of the extraction circuits 1 and 2 and the average value circuit 3 for obtaining the white correction signal H and the black correction signal M will be explained before explaining the operations of the white level tracking circuit 4 and the black level tracking circuit 5. Let's talk about the operation.

White level tracking circuit 4 and black level tracking circuit 5
is the upper limit reference voltage V of the analog-to-digital conversion circuit 6 shown in the following equations (1) and (2) based on the digital white reference signal B _b , digital black reference signal B _d , white correction signal H, and black correction signal M. Calculate _H and lower limit reference voltage V _L.

V _H = B _d + (B _b - B _d ) H ... (1) V _L = B _d + (B _b - B _d ) M ... (2) [Operation of white level tracking circuit] White level tracking circuit 4, as shown in Figure 4,
Inverters 401, 403 and 406, addition circuit 4
02,407, AND circuit 404, multiplication circuit 40
5. NAND circuit 408, latch 409, digital-to-analog conversion circuit 410, and low-pass filter 41
1 to calculate the upper limit reference voltage _VH .

In FIG. 1, the digital white reference signal B _b stored in the storage circuit 9 and the digital black reference signal B _d stored in the storage circuit 10 are phase pulses generated every scanning period T from the scanning circuit 7. The pixel clock is started at C and read out by the read address generated by the pixel clock _S1 from the synchronous clock generating circuit 16.

In FIG. 4, a digital white reference signal B _b and an inverted digital black reference signal _d inverted by an inverter 401 are supplied to an adder circuit 402 .

The adder circuit 402 adds "1" to the least significant bit of the inverted black reference signal _d to add the complement of the digital black reference signal B _d and the digital white reference signal B _b . A "high" signal is output from the terminal Co as a carry signal E, and a "low" signal is output when there is no carry.

Therefore, when the carry signal E is "high" in the AND circuit 404, an AND is performed and an 8-bit white envelope signal F is output. This operation performs subtraction and obtains (B _b −B _d ).

The multiplication circuit 405 inputs the 8-bit white envelope signal F and
Multiplying with the 10-bit white correction signal H is performed, and the upper 10 bits of the 18-bit data resulting from the multiplication are taken in as data at the rising edge of the inverted pixel clock ₁ whose phase has been inverted by the inverter 406, and the pixel clock S ₁
It is latched and taken out at the rising edge of . This result [(B _b −B _d )×H] is calculated.

However, at this point, the extraction circuit 1 shown in FIG.
The white data signal L is not generated and represents the reflectance of 100% stored in advance in the storage circuit 304 (see FIG. 3) in the average value circuit 3 shown in FIG.
A white correction signal H ₁₀₀ in the 10-bit white correction signal H of all “1” is supplied to the multiplication circuit 405 .
Therefore, [(B _b −B _d )×H] is equivalent to (B _b −B _d ).

Next, the 10-bit data output from the multiplier circuit 405 and the digital black reference signal _Bd are added in an adder circuit 407, and the addition result is added to the NAND circuit 40.
8. The above process completes the calculation of equation (1), but in the case of the white correction signal H ₁₀₀ , V _H =B _b .

When the main scanning start enable signal K becomes "high", the NAND circuit 408 calculates the NAND, and 10-bit digital code data corresponding to the upper limit reference voltage V _H is output and supplied to the latch 409 . The operations of the latch 409, digital-to-analog conversion circuit 410, and low-pass filter 411 are omitted since they have been described above, but the digital-to-analog conversion circuit 410 converts the supplied 10-bit digital code data into an analog voltage amount corresponding to the supplied data. Upper limit reference voltage
_VH is generated and supplied to the analog-to-digital conversion circuit 6 through a low-pass filter 411.

Therefore, the upper limit reference voltage V _H in the case of the white correction signal H ₁₀₀ becomes "A _b " volts shown in FIG.

[Operation of black level tracking circuit]

Next, the black level tracking circuit 5 shown in FIG.
06 and a low-pass filter 507, the white envelope signal F from the white level tracking circuit 4 and the black reference signal
A lower limit reference voltage V _L is calculated from B _d and the black correction signal M.

The operations of the multiplier circuit 501 and the adder circuit 503 are similar to those of the multiplier circuit 405 and the adder circuit 407 of the white level tracking circuit 4 described above, except that the black correction signal M is used instead of the white correction signal H. )
An operation is performed on the expression.

However, at this point, the extraction circuit 2 shown in FIG.
The black data signal N is not generated, but is a 10-bit all-zero signal representing a reflectance of 0%, which is stored in advance in the storage circuit 305 (see FIG. 3) in the average value circuit 3 shown in FIG. A black correction signal M ₀ in the black correction signal M is supplied to a multiplication circuit 501 . Therefore,
The term [(B _b − B _d ) × M] in equation (2) disappears, and V _L = B _d
is obtained.

The 10-bit digital code data from the adder circuit 503 is supplied to the NOT sum circuit 504. When the main scanning start enable signal K is set to "high", the inverted main scanning start enable signal becomes "low", the negative sum is calculated in the negative sum circuit 504, and the 10-bit digital signal corresponding to the upper limit reference voltage V _L is After the code data is bit-aligned by latch 505, it is supplied to digital-to-analog conversion circuit 506.

The digital-to-analog conversion circuit 506 generates a lower limit reference voltage V _L that is converted into an analog voltage amount corresponding to the 10-bit digital code data, and passes through the low-pass filter 507 to the analog-to-digital conversion circuit 6 shown in FIG. supply

Therefore, the lower limit reference voltage in case of black correction signal M ₀
V _L becomes the "A _d " volt shown in FIG.

[Operation of extraction circuit]

Next, in FIG. 1, the upper limit reference voltage of “A _d ” volts corresponding to the white correction signal H ₁₀₀ and the lower limit reference voltage of “A _d ” volts corresponding to the black correction signal M ₀ are applied to the analog-to-digital conversion circuit 6. The scanning circuit 7 scans the original image.

The scanning circuit 7 outputs an image signal A _a of the photoelectric conversion signal A shown in _FIG . is supplied to extraction circuits 1 and 2 via bus switching gate 8 and buffers 11 and 13.

As shown in FIG. 2, the extraction circuit 1 includes counters 101, 104, 106 and 110, and an inverter 1.
02, 103, OR circuit 105, AND circuit 1
09, flip-flops 107, 108 and 1
11. It includes a NAND circuit 112 and a storage circuit 113, and extracts density data corresponding to a plurality of pixels from a designated white density region of an original image and outputs a white data signal.

Prior to scanning the original image, specify the density area on the original image that you want to make white. That is, in this embodiment, in order to facilitate understanding, in the four main scanning lines starting from the first main scanning line to the nth main scanning line, as shown surrounded by a dashed line in FIG. Each consists of 4 pixels starting at the mth pixel from the main scanning start point.
Suppose you specify an area consisting of 16 pixels.

In the following explanation, the operation of the detailed block diagram shown in FIG. 2 will be explained with reference to the time chart shown in FIG. 6 and FIG. 7.

The counter 101 is set to (n-1) and counts the phase pulses C from when the sub-scanning start enable signal P becomes "high", and outputs a signal at the trailing edge of the (n-1)th phase pulse. a is made "low" and remains "low" until the trailing edge of the next phase pulse.

The counter 104 is set to "4" which corresponds to the number of scanning lines including the pixels to be extracted, and the inverted phase pulse from the counter 101 whose phase is inverted by the inverter 102 and the inverted phase pulse from the counter 101 whose phase is inverted by the inverter 103 are set in the counter 104. An inverted output signal a is supplied.

Counter 104 is activated when the inverted output signal is "high" and counts four phase pulses. Therefore, the output signal b from the counter 104 goes "low" at the leading edge of the nth phase pulse and goes "high" at the leading edge of the (n+4)th phase pulse, as shown in FIG. However, the period in which the output signal b is "low" includes phase pulses for each of the four main scanning lines including the pixels to be extracted.

The OR circuit 105 performs the OR of the output signal b of the counter 104 and the inverted phase pulse, and outputs four extracted phase pulses d starting from the n-th pulse.

Next, the counter 106 is set to (m-1), which corresponds to the number of pixels in the main scanning direction from the main scanning start point, and is activated every time the extraction phase pulse d is supplied to count the pixel clock _S1 . , generates a "low" extraction start position designation signal e that occurs at the trailing edge of the extraction phase pulse d and disappears after (m-1) counts.

The input terminal D of the flip-flop 107 has “+”.
A voltage of "V" is supplied, and is set when the extraction start position designation signal e disappears, making the output terminal Q "high" and being reset by the reset signal R. However, the reset signal R is a signal that remains "low" during a period when the image signal A _a is not generated in the period T of one scanning line.

A "high" output signal from output terminal Q of flip-flop 107 is applied to input terminal D of flip-flop 108. At the leading edge of the next pixel clock _S1 , flip-flop 108 is set and a "high" output signal from output terminal Q is applied. The extracted pixel position signal f is output and reset by a reset signal R.

Next, the logical product of the extracted pixel position signal f and the pixel clock _S1 is taken in the logical product circuit 109, and the extracted pixel clock h is extracted from the m-th pixel clock from the main scanning start point until the reset signal R is generated. It is output every time the start position designation signal e disappears.

The counter 110 is set to "4", which is the number of extracted pixels in the main scanning direction, and the extracted pixel position signal f is "high".
The clock terminal CK of the flip-flop 111 outputs an output signal k which becomes "high" when the number of extracted pixel clocks h is counted and is converted to "low" by the next phase pulse.
supply to.

The flip-flop 111 inputs “+” to the input terminal D.
A voltage of ``V'' is supplied, and when the output signal k becomes ``high'', it is set and reset by the reset signal R, and a ``low'' extraction end position signal r is generated from the output terminal.

Next, the negative product of the extraction pixel clock h and the extraction end position signal r is taken by the negative product circuit 112, and a write signal w having four pixel clocks is outputted and stored in the storage circuit 113 as a digital image signal B _a '. Each one corresponding to the included write signal w instructs writing of 8-bit pixel data.

The storage circuit 113 is composed of 16 8-bit words, and when it has finished storing the white density data of 16 pixels with 8 bits per pixel and the read request signal U from the average value circuit 3 is "high", the stored white density data is stored. The average value circuit 3 reads the data and passes through the buffer 12.
A white data signal L and a white data sending signal _W1 are supplied to the white data signal L and the white data sending signal W1.

Next, the extraction circuit 2 is a circuit that specifies a density area on the original image that is desired to be black, extracts density data corresponding to a plurality of pixels from the area, and outputs a black data signal N. ,104,
The circuit configuration and operation are the same as those of the extraction circuit 1 described above, except that the set values of 106 and 110 are different.

However, the white data signal L of the extraction circuit 1 described above should be read as the black data signal N, the white data sending signal _W1 as the black data sending signal _W2 , and the buffer 12 as the buffer 14.

[Operation of average value circuit]

As shown in FIG. 3, the average value circuit 3 includes an addition circuit 301, a register 302, a division circuit 303, and storage circuits 304 and 305, and calculates the average value of each of the white data signal L and the black data signal N. 10-bit white correction signal H and black correction signal M
Output.

When there is no input data to be calculated, the average value circuit 3 supplies a "high" read request signal U from the division circuit 303 to the extraction circuits 1 and 2 to request data.

In this state, the 8-bit 16-word white data signal L is sequentially supplied from the extraction circuit 1 to the addition circuit 301, so the addition circuit 301 and the register 302 perform cumulative addition word by word, and the addition of 16 words is completed. At that time, the addition result is supplied to the division circuit 303. Further, at the same time as the above addition, the number of words added is counted, and the counted number of words is supplied to the division circuit 303.

The division circuit 303 performs division by using the supplied addition data as a dividend and the counted number of words as a divisor, and outputs only the quotient in 10 bits with the remainder rounded down.

Since the storage circuit 304 is supplied with the white data sending signal W ₁ from the extraction circuit 1 and instructs the storage circuit 304 to write data, the division circuit 303
The 10-bit output data from is stored in storage circuit 304.

The average value of the black data signal N from the extraction circuit 2 is also calculated in the same manner as above, and the output data of the calculation result is stored in the storage circuit 305. However, extraction circuit 1
Extraction circuit 2, white data signal L, black data signal N, white data sending signal W ₁ , black data sending signal W ₂
respectively.

The white correction signal H stored in the storage circuit 304 in this way has a reflectance of 10% for the designated white when the reflectance of the digital white reference signal B _b is 100%.
It is a digital code of bits, and the reason why 10 bits are given is to obtain a resolution of up to 0.1%.

Further, the black correction signal M stored in the storage circuit 305 is a 10-bit digital encoded version of the designated black reflectance when the reflectance of the digital black reference signal _Bd is set to 0%.

White correction signal H read out from memory circuit 304
is supplied to the white level tracking circuit 4, and the black correction signal M read from the storage circuit 305 is supplied to the black level tracking circuit 5.

As shown in FIG. 1, the white level tracking circuit 4 receives a digital white reference signal B _b and a digital black reference signal.
Based on B _d and the white correction signal H, the above-mentioned equation (1) is calculated to generate the upper limit reference voltage V _H of "V _W " volts shown in FIG.

Further, the black level tracking circuit 5 also outputs a white envelope signal F,
Based on the digital black reference signal _Bd and the black correction signal M, the above-mentioned equation (2) is calculated to generate the lower limit reference voltage _VL of " _VB " volts shown in FIG. supply

Next, in FIG. 1, the scanning circuit 7 scans the original image and outputs an image signal A _a shown in FIG. supply

The analog-to-digital conversion circuit 6 converts the upper limit reference voltage of “V _W ” volts to the voltage value of the image signal A _a .
According to the determination level between the upper and lower limit voltages regulated by the lower limit reference voltage V _L of V _H and “V _B ” volts, it is converted into 8-bit digitally encoded data and converted into a digital image via the bus switching gate 8. Output as signal B _a .

FIGS. 8 and 9 show waveform diagrams of the above operation. In FIG. 8, the vertical axis shows the input voltage of the analog-to-digital conversion circuit 6, and the horizontal axis shows the period T of one scan. Further, point X is the value obtained by converting the density average value of the specified area in the white density area into a voltage value, and point Y is the value obtained by converting the density value of the specified area in the black density area into a voltage value.

Now, when the image signal _{A a} shown in Fig. 8 is converted into an analog-digital signal with "V+" volts shown by the dotted line in the figure as the upper limit reference voltage V _{H and} "V _- " volts as the lower limit reference voltage V _L , the analog-digital conversion circuit 6
It is clear that the 256-step resolution that B a possesses cannot be obtained, and if the digital image signal B _a obtained in this way is recorded and reproduced, the white and black density regions cannot be reproduced and an image with good contrast cannot be obtained. I can't.

When the image _{signal A a is digitally converted using the upper limit reference voltage V H and the lower limit reference voltage V L as “V W ” volts shown by} the dashed line in FIG. 8, the hatched _“ The “A” part is white “B”
and “C” portions are black, but other white and black density areas are processed by the analog-to-digital conversion circuit 6.
Full resolution is obtained.

Note that the portions "A", "B", and "C" are portions that are determined not to be reproduced when specifying specific density areas of white and black density areas on the original image. Therefore, when recording and reproducing digital image signal B _a ,
A reproduced image with good contrast can be obtained.

FIG. 9 shows an apparent image signal A a corresponding to the judgment classification of the analog-to-digital conversion circuit 6 when the upper limit reference voltage V _H is set to "V _W " volts and the lower limit reference voltage V _L is set to "V _B " volts _. This is what is shown.

As explained above, in the embodiment of the present invention, the extraction circuit 1 and the extraction circuit 2 have the same circuit configuration, but similar results can be obtained even if they have different configurations. Furthermore, the number of pixels to be extracted may be any number, and may not be the same for white and black.

〔Effect of the invention〕

As described above, the image signal correction device of the present invention includes a first extraction circuit, a second extraction circuit, an average value circuit,
A white level tracking circuit and a black level tracking circuit are provided to determine the specified white and black densities on the original image, including compensation for shading and dark current, instead of fixing the upper and lower reference voltages and performing analog-to-digital conversion. By performing analog-to-digital conversion using the upper limit reference voltage and the lower limit reference voltage based on the correction value corresponding to the region, resolution equal to that of the analog-to-digital conversion circuit can be obtained, which has the effect of improving image quality.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention;
FIG. 2 is a detailed block diagram of the extraction circuit in the embodiment shown in FIG. 1, FIG. 3 is a detailed block diagram of the average value circuit in the embodiment shown in FIG. 1, and FIG. 4 is the embodiment shown in FIG. 5 is a detailed block diagram of the black level tracking circuit in the embodiment shown in FIG. 1, and FIG. 6 is a time diagram for explaining the operation of the extraction circuit shown in FIG. 2. 7 is an explanatory diagram of the image signal extraction operation of the extraction circuit shown in FIG. 2, FIG. 8 is a waveform diagram for explaining the operation of the embodiment shown in FIG. 1, and FIG. 9 is a diagram illustrating the operation of the embodiment shown in FIG. FIG. 3 is an apparent waveform diagram for explaining the operation of the embodiment shown in FIG. In the figure, 1, 2...extraction circuit, 3...average value circuit, 4...white level tracking circuit, 5...black level tracking circuit, 6...analog-digital conversion circuit, 9, 10...memory circuit, A...Photoelectric conversion signal, A _a ...Picture signal, A _b ...White reference signal, A _d ...
Black reference signal, B...digital encoded signal, B _a
...Digital picture signal, B _b ...Digital white reference signal, B _d ...Digital black reference signal, L...
White data signal, N...Black data signal, H...White correction signal, M...Black correction signal, _VH ...Upper limit reference voltage, _VL ...Lower limit reference voltage.

Claims (1)

[Claims] 1 The judgment level between the upper and lower limit voltages of the dynamic range is controlled by the upper limit reference voltage and the lower limit reference voltage, and an image signal obtained by photoelectrically converting the density information of the original image is input, and the judgment level is multiplied at the judgment level corresponding to the input level. an analog-to-digital conversion circuit that decomposes values, a first upper limit voltage whose upper limit reference voltage is equal to the image signal level of the white peak value corresponding to 100% reflectance, and a black peak whose lower limit reference voltage is equivalent to 0% reflected light; A white reference signal obtained by digitally converting an image signal corresponding to one scanning line obtained by scanning a reference white plate at a first lower limit voltage equal to the image signal level of the value by the analog-to-digital conversion circuit, and a first storage circuit that reads data at a predetermined period synchronized with scanning; and a photoelectric conversion voltage at zero incident light when the upper limit reference voltage is the first upper limit voltage and the lower limit reference voltage is the first lower limit voltage. a second storage circuit that stores a black reference signal obtained by digitally converting the signal from the analog-to-digital converter and reads it out at the predetermined period; the upper limit reference voltage is the first upper limit voltage, and the lower limit reference voltage is the first outputting a first white data signal corresponding to the image signal level of the white peak value when the lower limit voltage is 1, and when the upper limit reference voltage is a second upper limit voltage and the lower limit reference voltage is a second lower limit voltage; a first extraction circuit for extracting a second white data signal obtained by digitally converting image signals from a plurality of pixels obtained by scanning a designated white density region of the original image by the analog-to-digital conversion circuit; and the upper limit reference. When the voltage is the first upper limit voltage and the lower reference voltage is the first lower limit voltage, a first black data signal corresponding to the image signal level of the black peak value is output, and the upper limit reference voltage is the first lower limit voltage. When the lower limit reference voltage is the second lower limit voltage and the lower limit voltage is the second lower limit voltage, image signals from a plurality of pixels obtained by scanning a designated black density area of the original image are converted into digital signals by the analog-to-digital conversion circuit. a second extraction circuit for extracting two black data signals; an average value circuit that stores a white correction signal, a second white correction signal, a first black correction signal, and a second black correction signal and reads them out at the predetermined period; The product of the difference between the white reference signals and the first or second white correction signal is added to determine the upper limit reference voltage, and the first upper limit voltage is determined from data corresponding to a preset reflectance of 100%. a white level tracking circuit that determines the first upper limit voltage based on the first white correction signal and determines a third upper limit voltage based on the second white correction signal; and the product of the difference from the white reference signal and the first or second black correction signal is added to determine the lower limit reference voltage, and the first lower limit voltage is determined from data corresponding to a preset reflectance of 0%. and a black level tracking circuit that determines the second lower limit voltage based on the first black correction signal and determines the third lower limit voltage based on the second black correction signal, the third upper limit and 1. An image signal modifying device for modifying an image signal by setting lower limit voltages as the upper limit reference voltage and the lower limit reference voltage, respectively.