JPH0161265B2 - - Google Patents
Info
- Publication number
- JPH0161265B2 JPH0161265B2 JP57210144A JP21014482A JPH0161265B2 JP H0161265 B2 JPH0161265 B2 JP H0161265B2 JP 57210144 A JP57210144 A JP 57210144A JP 21014482 A JP21014482 A JP 21014482A JP H0161265 B2 JPH0161265 B2 JP H0161265B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- stages
- stage
- output
- ring counter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
- H03K23/66—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses
- H03K23/665—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses by presetting
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/40—Gating or clocking signals applied to all stages, i.e. synchronous counters
- H03K23/50—Gating or clocking signals applied to all stages, i.e. synchronous counters using bi-stable regenerative trigger circuits
- H03K23/54—Ring counters, i.e. feedback shift register counters
Landscapes
- Manipulation Of Pulses (AREA)
- Logic Circuits (AREA)
Description
【発明の詳細な説明】
(a) 発明の技術分野
本発明はリングカウンタ回路に係り、特に段
数可変・初期設定可能なリングカウンタ回路に
おいて動作するクロツクを高速化出来るリング
カウンタ回路に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a ring counter circuit, and more particularly to a ring counter circuit capable of increasing the speed of a clock operating in a ring counter circuit in which the number of stages is variable and initial setting is possible.
(b) 従来技術と問題点
第１図はリングカウンタ回路の基本構成を示
すブロツク図、第２図は従来例の段数可変・初
期設定可能なリングカウンタ回路のブロツク図
である。(b) Prior Art and Problems FIG. 1 is a block diagram showing the basic configuration of a ring counter circuit, and FIG. 2 is a block diagram of a conventional ring counter circuit in which the number of stages can be varied and initial settings can be made.
図中１，２，３，Ｍ，Ｎ−１はフリツプフロ
ツプ（以下FFと称す）、１０，１１，１２はナ
ンド回路、２０は段数設定デコード回路を示
す。 In the figure, 1, 2, 3, M, and N-1 are flip-flops (hereinafter referred to as FF), 10, 11, and 12 are NAND circuits, and 20 is a stage number setting decoding circuit.
第１図はリングカウンタ回路の基本構成で
FF１〜FFN−１のＮ−１個のFFの出力Ｑがす
べて“１”レベルの時のみFF１に“０”レベ
ルが入力される。従つて通常はクロツクの数が
Ｎ回に１回だけ“０”レベルがナンドゲート１
０からFF１の入力Ｄに、出力される。又いか
なる初期値が与えられても最大Ｎ−１個のクロ
ツク後にはクロツクの数がＮ回に１回だけ
“０”レベルがナンド回路１０から出力される
正常な状態となる。 Figure 1 shows the basic configuration of a ring counter circuit.
A "0" level is input to FF1 only when the outputs Q of N-1 FFs of FF1 to FFN-1 are all at "1" level. Therefore, normally the "0" level is NAND gate 1 only once every N clocks.
It is output from 0 to input D of FF1. Also, no matter what initial value is given, after a maximum of N-1 clocks, a normal state is reached in which the "0" level is output from the NAND circuit 10 only once every N clocks.
若し初期化が必要な際は、セツト信号により
全部のFF１〜FFN−１の出力Ｑを“１”レベ
ルにセツトすれば、セツト信号解除後最初のク
ロツクでFF１の出力のみに“０”レベルが現
われる状態からスタートする。 If initialization is necessary, if the output Q of all FF1 to FFN-1 is set to the "1" level by the set signal, only the output of FF1 will be set to the "0" level at the first clock after the set signal is released. Start from the state where appears.
このように初期化可能なリングカウンタ回路
の段数を可変にするには従来は第２図のような
回路が用いられている。これは段数を、Ｍ段か
らＮ段の間（Ｍ＜Ｎ）可変したい回路で、
FFMからFFN−１の出力及び段数設定デコ
ード回路２０の出力をナンド回路１１〜１２に
入力しておき、Ｍ段にしたい時は段数設定回路
２０の、ナンド回路１１〜１２、即ちFFMか
らFFN−１の出力の出力が入力しているナ
ンド回路への出力を全て“０”レベルとすれ
ば、FF１〜FFM−１（図示していない）の出
力Ｑが全て“１”レベルの時FF１に“０”レ
ベルが入力されＭ段（Ｍ回に１回“０”レベル
が出力される）のリングカウンタ回路が出来
る。 In order to make the number of stages of the initializable ring counter circuit variable in this way, a circuit as shown in FIG. 2 has conventionally been used. This is a circuit where you want to vary the number of stages between M and N stages (M<N).
The output of FFN-1 from FFM and the output of the stage number setting decoding circuit 20 are input to the NAND circuits 11 and 12, and when you want to make M stages, the outputs of FFN-1 and the output of the stage number setting decoding circuit 20 are inputted to the NAND circuits 11 and 12 of the stage number setting circuit 20, that is, from FFM to FFN- If all the outputs to the NAND circuit to which the output of the output 1 is input are set to "0" level, when the outputs Q of FF1 to FFM-1 (not shown) are all "1" level, FF1 will be set to "0" level. A ring counter circuit of M stages (a "0" level is output once every M times) is formed by inputting a "0" level.
尚任意のFFをリセツトする複雑な回路を追
加すればリセツトしたFFから初期化は可能で
ある。 Note that by adding a complicated circuit to reset any FF, it is possible to initialize from the reset FF.
しかしながら、第２図に示すような従来のリ
ングカウンタ回路では、１段目のFF１に帰還
するループがゲート２段となるので動作するク
ロツクを高速化する場合の妨げになるという欠
点がある。 However, in the conventional ring counter circuit as shown in FIG. 2, the loop that feeds back to the first stage FF1 has two stages of gates, which has the disadvantage of hindering the speeding up of the operating clock.
(c) 発明の目的
本発明の目的は上記の欠点に鑑み、帰還ルー
プのゲートの段数を１段に出来動作するクロツ
クを高速化出来る段数可変・初期設定可能なリ
ングカウンタ回路の提供にある。(c) Object of the Invention In view of the above-mentioned drawbacks, the object of the present invention is to provide a ring counter circuit with variable and initial setting of the number of stages, which can reduce the number of gate stages of the feedback loop to one stage and speed up the operating clock.
(d) 発明の構成
本発明は上記の目的を達成するために、Ｎ段
（Ｎ２）からなる２値素子、並びに該Ｎ段か
らなる２値素子の全段の出力の論理をとつて、
１段目の２値素子の状態を他のＮ−１段の２値
素子の状態と異なる状態に設定するゲートを有
するリングカウンタ回路において、段数をＭ段
（ＭＮ）に設定する際、該Ｍ段目をセツト又
はリセツトするとともに、Ｋ段目（１Ｋ＜
Ｍ）をリセツト又はセツトできる設定回路を設
けたことを特徴とするものである。(d) Structure of the Invention In order to achieve the above object, the present invention takes the logic of a binary element consisting of N stages (N2) and the outputs of all stages of the binary element consisting of the N stages,
In a ring counter circuit having a gate that sets the state of a binary element in the first stage to be different from the state of the binary elements in other N-1 stages, when setting the number of stages to M stages (MN), the M At the same time as setting or resetting the stage, the Kth stage (1K<
The present invention is characterized in that it is provided with a setting circuit that can reset or set M).
(e) 発明の実施例
以下本発明の実施例につき図に従つて説明す
る。(e) Embodiments of the invention Examples of the invention will be described below with reference to the drawings.
第３図は本発明の実施例の段数可変・初期設
定可能なリングカウンタ回路のブロツク図であ
る。 FIG. 3 is a block diagram of a ring counter circuit in which the number of stages can be changed and the number of stages can be initialized according to an embodiment of the present invention.
図中第２図と同一機能のものは同一記号で示
す。３０は設定回路を示す。 Components in the figure that have the same functions as those in FIG. 2 are indicated by the same symbols. 30 indicates a setting circuit.
第３図の回路でリングカウンタ回路をＭ段に
設定したい場合には段数設定信号により設定回
路３０の出力でFFMをセツトすればFFMの出
力Ｑは“１”レベルとなり、動作時にはFFM
〜FFN−１の出力Ｑは常に“１”レベルとな
つているので、FF１〜FFM−１の出力Ｑが全
部“１”レベルの時のみ次のクロツクでFF１
の出力Ｑが“０”レベルに設定出来る。 If you want to set the ring counter circuit to M stages in the circuit shown in Figure 3, set the FFM with the output of the setting circuit 30 using the stage number setting signal, and the output Q of the FFM will be at the "1" level.
~ Since the output Q of FFN-1 is always at the "1" level, FF1 will be output at the next clock only when all the outputs Q of FF1 ~ FFM-1 are at the "1" level.
The output Q of can be set to "0" level.
このようにして段数を任意に可変出来る。 In this way, the number of stages can be changed arbitrarily.
又Ｍ段に設定した状態でＫ段目のFFK（１＜
Ｋ＜Ｍ）（図示していない）から初期化したい
場合には、リセツト信号により設定回路３０か
らFFKをリセツトしFFKの出力Ｑを“０”レ
ベルとすればリセツト信号解除後はＭ−Ｋ個目
のクロツクの後でFF１の出力Ｑが“０”レベ
ルになる位相にセツトできる。 Also, with the M stage set, the Kth stage FFK (1 <
If you want to initialize from K<M) (not shown), reset FFK from the setting circuit 30 with a reset signal and set the output Q of FFK to "0" level. After the second clock, the phase can be set so that the output Q of FF1 becomes "0" level.
尚第３図では全てのFFのセツトリセツト端
子Ｓ，Ｒに信号線が接続されているが、これは
段数を設定したい段数のFF及び初期化したい
段目のFFだけに接続しておけばよい。 In FIG. 3, signal lines are connected to the reset terminals S and R of all FFs, but these need only be connected to the FFs of the desired number of stages and the FFs of the stage desired to be initialized.
このようにすれば１段目のFF１に帰還する
ループがゲート１段となるので動作するクロツ
クを高速化出来る。尚ナンド回路１０をオア回
路とした場合は上記説明のセツト・リセツトを
逆にすればよい。 In this way, the loop that feeds back to the first stage FF1 becomes one stage of gates, so that the operating clock speed can be increased. If the NAND circuit 10 is an OR circuit, the above-mentioned set and reset operations may be reversed.
第４図は本発明のリングカウンタ回路を位相
同期回路等のバツフアメモリ回路に応用した応
用例の回路のブロツク図である。 FIG. 4 is a block diagram of an example circuit in which the ring counter circuit of the present invention is applied to a buffer memory circuit such as a phase locked circuit.
図中４０，４１はリングカウンタ、４２，４
３はメモリ用FF、４３〜４６はアンド回路、
４７はオア回路である。 In the figure, 40 and 41 are ring counters, 42 and 4
3 is a memory FF, 43 to 46 are AND circuits,
47 is an OR circuit.
図は2Mビツトのバツフアメモリ回路で、メ
モリ用FFは2M個有り、入力データを、メモリ
用FF４２，４３……に読込みこのメモリより
書出す位置をリングカウンタ４０，４１にて指
示するものである。読込み書出しクロツクは双
方無関係でよく、リングカウンタ４０，４１の
ヘツダー（１周期に１個だけ例えば“０”レベ
ルになる信号）RPH（Read Pulse Header）、
WPH（Write Pulse Header）を比較して読み
込み書き出し位相がずれているよう、例えば読
込みはメモリ用FFの第１段より、書出しはメ
モリFFのＭ段目からするように制御すれば読
込み書き出しクロツクの位相差を吸収するバツ
フアメモリとなる。初期状態において読込みは
メモリFFの第１段より書込みはメモリFFのＭ
段目からするようにしておけば初期状態の後に
すぐ読書きが最適の状態からスタート出来好都
合である。その場合には、リングカウンタ４０
に第１図の回路を用いて第１段目のFFから初
期化し、リングカウンタ４１には本発明の第３
図の回路を用いて初期化時にＭ段目のFFだけ
を“０”レベルにしておけばよいわけである。 The figure shows a 2M-bit buffer memory circuit, which has 2M memory FFs. Input data is read into memory FFs 42, 43, . The read/write output clocks may be unrelated to each other, and the headers of the ring counters 40 and 41 (a signal that reaches the "0" level only once per cycle) RPH (Read Pulse Header),
If you compare the WPH (Write Pulse Header) and control the read/write phase to be shifted, for example, read from the 1st stage of the memory FF and write from the Mth stage of the memory FF, the read/write clock will change. It becomes a buffer memory that absorbs the phase difference. In the initial state, reading is performed from the first stage of memory FF and writing is performed from stage M of memory FF.
If you do it from the first row, it is convenient because you can start from the optimal state for reading and writing immediately after the initial state. In that case, the ring counter 40
Initialize from the first stage FF using the circuit shown in FIG.
Using the circuit shown in the figure, it is sufficient to set only the M-th stage FF to the "0" level at the time of initialization.
このようにすれば高速のクロツクにも対応出
来るし、尚又リングカウンタ４１の段数変更も
容易に出来る。 In this way, it is possible to cope with a high-speed clock, and the number of stages of the ring counter 41 can also be easily changed.
勿論FF４２，４３…への読込みはアンド回
路４３，４４へのリングカウンタ４０の出力段
の出力及び読込みクロツクが“Ｈ”レベルの時
行ない、書き出しはアンド回路４５，４６への
リングカウンタ４１の出力段の出力及びFF４
２，４３の出力Ｑが“Ｈ”レベルの時行ない、
オア回路４７より出力データは出力される。 Of course, reading to the FFs 42, 43, etc. is performed when the output of the output stage of the ring counter 40 to the AND circuits 43, 44 and the read clock are at "H" level, and writing is performed by the output of the ring counter 41 to the AND circuits 45, 46. Stage output and FF4
Performed when the output Q of 2 and 43 is at “H” level,
Output data is output from the OR circuit 47.
第５図は、本発明の実施例の段数変更の場合
第３図の如くFFのセツト端子を利用する代わ
りに、前段のFF５１の出力Ｑと後段のFF５２
の入力の間にナンド回路５３を挿入したもの
で、ナンド回路５３にセツト信号を入力させて
おく。 FIG. 5 shows that when changing the number of stages in the embodiment of the present invention, instead of using the set terminal of the FF as shown in FIG.
A NAND circuit 53 is inserted between the inputs of , and a set signal is input to the NAND circuit 53 .
セツト信号を“１”レベルとしておくとナン
ド回路はなくFF５１の出力ＱとFF５２の入力
とを接続した場合と同じ動作をし、セツト信号
を“０”レベルとするとFF５２の入力には
“１”レベルが入力することになるので第３図
のセツト端子を利用した場合と等化になる。 When the set signal is set to "1" level, there is no NAND circuit and the operation is the same as when the output Q of FF51 and the input of FF52 are connected, and when the set signal is set to "0" level, the input of FF52 is set to "1". Since the level is input, it is equalized to the case where the set terminal in FIG. 3 is used.
この場合はセツト信号の解除がクロツクと同
期する利点がある。 In this case, there is an advantage that the release of the set signal is synchronized with the clock.
尚この場合はFF間の遅延はゲート１段分大
きくなるが、これは先に説明した通り１段目の
FFへの帰還ループでゲート１段分遅くなるの
で、動作するクロツクを高速化する場合の障害
とはならない。 In this case, the delay between FFs increases by one gate stage, but this is due to the delay in the first stage as explained earlier.
Since the feedback loop to the FF delays the gate by one stage, it does not become an obstacle when speeding up the operating clock.
(f) 発明の効果
以上詳細に説明せる如く本発明によれば、段
数可変・初期設定可能なリングカウンタ回路の
帰還ループのゲートの段数を１段に出来るの
で、動作するクロツクを高速化出来る効果があ
る。(f) Effects of the Invention As explained in detail above, according to the present invention, the number of stages of the gate of the feedback loop of the ring counter circuit with variable stage number and initial setting can be reduced to one stage, so the operating clock speed can be increased. There is.
第１図はリングカウンタ回路の基本構成を示す
ブロツク図、第２図は従来例の段数可変・初期設
定可能なリングカウンタ回路のブロツク図、第３
図は本発明の実施例の段数可変・初期設定可能な
リングカウンタ回路のブロツク図、第４図は本発
明のリングカウンタ回路をバツフアメモリ回路に
応用した応用例の回路のブロツク図、第５図は本
発明の実施例の段数可変回路のブロツク図であ
る。
図中１，２，３，Ｍ，Ｎ−１，４３，４４，５
１，５２はFF、１０〜１２，５３はナンド回路、
４３〜４６はアンド回路、４７はオアー回路、２
０は段数設定デコード回路、３０は設定回路、４
０，４１はリングカウンタを示す。
Fig. 1 is a block diagram showing the basic configuration of a ring counter circuit, Fig. 2 is a block diagram of a conventional ring counter circuit with variable number of stages and initial setting.
The figure is a block diagram of a ring counter circuit with variable stage number and initial setting according to an embodiment of the present invention, FIG. 4 is a block diagram of a circuit of an application example in which the ring counter circuit of the present invention is applied to a buffer memory circuit, and FIG. FIG. 2 is a block diagram of a variable stage number circuit according to an embodiment of the present invention. 1, 2, 3, M, N-1, 43, 44, 5 in the diagram
1,52 is FF, 10-12,53 is NAND circuit,
43 to 46 are AND circuits, 47 is an OR circuit, 2
0 is the stage number setting decoding circuit, 30 is the setting circuit, 4
0,41 indicates a ring counter.
Claims (1)
Ｎ段からなる２値素子の全段の出力の論理をとつ
て、１段目の２値素子の状態を他のＮ−１段の２
値素子の状態と異なる状態に設定するゲートを有
するリングカウンタ回路において、 段数をＭ段（ＭＮ）に設定する際、該Ｍ段目
をセツト又はリセツトするとともに、Ｋ段目（１
Ｋ＜Ｍ）をリセツト又はセツトできる設定回路
を設けたことを特徴とするリングカウンタ回路。[Claims] 1 A binary element consisting of N stages (N2) and the logic of the outputs of all stages of the binary element consisting of N stages are taken to determine the state of the binary element in the first stage from that of other stages. N-1 stage 2
In a ring counter circuit having a gate that is set to a state different from the state of the value element, when setting the number of stages to M stages (MN), the Mth stage is set or reset, and the Kth stage (1
A ring counter circuit comprising a setting circuit capable of resetting or setting K<M.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21014482A JPS59100630A (en) | 1982-11-30 | 1982-11-30 | Ring counter circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21014482A JPS59100630A (en) | 1982-11-30 | 1982-11-30 | Ring counter circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59100630A JPS59100630A (en) | 1984-06-09 |
| JPH0161265B2 true JPH0161265B2 (en) | 1989-12-27 |
Family
ID=16584495
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21014482A Granted JPS59100630A (en) | 1982-11-30 | 1982-11-30 | Ring counter circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59100630A (en) |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4826354A (en) * | 1971-08-10 | 1973-04-06 | ||
| JPS518855A (en) * | 1974-07-10 | 1976-01-24 | Nippon Electric Co | DEIJITARUKUROTSUKUBUNSHUKAIRO |
-
1982
- 1982-11-30 JP JP21014482A patent/JPS59100630A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59100630A (en) | 1984-06-09 |
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