JPH0210579B2 - - Google Patents
Info
- Publication number
- JPH0210579B2 JPH0210579B2 JP59207188A JP20718884A JPH0210579B2 JP H0210579 B2 JPH0210579 B2 JP H0210579B2 JP 59207188 A JP59207188 A JP 59207188A JP 20718884 A JP20718884 A JP 20718884A JP H0210579 B2 JPH0210579 B2 JP H0210579B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- resin
- chip mounting
- fins
- mounting bed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/40—Leadframes
- H10W70/461—Leadframes specially adapted for cooling
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は、樹脂封止型半導体装置に関し、特
に小型で従来品よりも放熱性能が高く且つ製造コ
ストが安価な改良された樹脂封止型半導体装置に
関するものである。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a resin-sealed semiconductor device, and in particular to an improved resin-sealed semiconductor device that is small, has higher heat dissipation performance than conventional products, and is less expensive to manufacture. It is related to the device.
最近の半導体装置は、製造技術の進歩に伴つて
半導体装置の集積度が高くなつており、その結
果、半導体チツプの単位面積当りの発熱量も従来
品のそれにくらべてかなり増大している。このた
め、半導体装置の外囲器構造も従来品のそれより
も高い放熱性能を有するものが必要となつてお
り、最近製造されている樹脂封止型半導体装置に
は、外囲器構造に以下のごとき放熱性能向上の対
策を施したものがある。
The degree of integration of recent semiconductor devices has increased with advances in manufacturing technology, and as a result, the amount of heat generated per unit area of the semiconductor chip has increased considerably compared to that of conventional products. For this reason, the envelope structure of semiconductor devices needs to have higher heat dissipation performance than that of conventional products, and recently manufactured resin-sealed semiconductor devices have the following envelope structures: Some products have measures to improve heat dissipation performance, such as:
第6図乃至第8図に示す公知の樹脂封止型半導
体装置1は、第7図に示すようにチツプ取付ベツ
ド部2に連設された幅広のフイン3を有するリー
ドフレーム4を用いて構成されており、この半導
体装置ではその樹脂モールド部5の側面から該フ
イン3が突出した外囲器構造となつている。な
お、第6図乃至第8図において、6はリードフレ
ーム4の一部であるリード部、7はチツプ取付ベ
ツド部2をリードフレーム4の外枠部分に連結し
ている一対のタイバー、8はチツプ取付ベツド部
2に第8図に示すようにはんだ9等で接着された
半導体チツプ、10は半導体チツプ8上の電極パ
ツドとリードフレームのリード部6とにボンデイ
ングされたボンデイングワイヤであり、第7図の
二点鎖線で囲まれた枠A内に樹脂成形を行うこと
により樹脂モールド部5を成形した後、該枠Aの
外側のリードフレームを図示の一点鎖線、L1、
L2に沿つて切断除去し、更に樹脂モールド部5
の外側に突出したリード部6とフイン3とを折曲
成形して第6図のごとき樹脂封止型半導体装置1
が完成する。 A known resin-sealed semiconductor device 1 shown in FIGS. 6 to 8 is constructed using a lead frame 4 having wide fins 3 connected to a chip mounting bed portion 2, as shown in FIG. This semiconductor device has an envelope structure in which the fins 3 protrude from the side surface of the resin molded portion 5. In FIGS. 6 to 8, 6 is a lead part which is a part of the lead frame 4, 7 is a pair of tie bars connecting the chip mounting bed part 2 to the outer frame part of the lead frame 4, and 8 is a lead part which is a part of the lead frame 4. As shown in FIG. 8, the semiconductor chip is bonded to the chip mounting bed part 2 with solder 9 or the like, and 10 is a bonding wire bonded to the electrode pad on the semiconductor chip 8 and the lead part 6 of the lead frame. After molding the resin mold part 5 by performing resin molding within the frame A surrounded by the two-dot chain line in FIG .
Cut and remove along L 2 , and then remove the resin mold part 5.
A resin-sealed semiconductor device 1 as shown in FIG.
is completed.
前記のごとき外囲器構造の半導体装置1はチツ
プ取付ベツド部2と一体となつたフイン3が樹脂
モールド部5の表面に露出しているので、このよ
うな構造ではない従来のフインなし樹脂封止型半
導体装置よりも放熱性能が高い。 In the semiconductor device 1 having the above-mentioned envelope structure, the fins 3 integrated with the chip mounting bed part 2 are exposed on the surface of the resin mold part 5. It has higher heat dissipation performance than static type semiconductor devices.
一方、第9図に示すように、チツプ取付ベツド
部のないリードフレームを用いて半導体チツプ8
を直接にヒートシンク11上に取り付けた構造の
樹脂封止型半導体装置12も放熱性の高い半導体
装置として従来から製造されている(なお、第9
図において、第6図乃至第8図と同一符号で表示
されている部分は第6図乃至第8図に示した半導
体装置と同じ部分である)。 On the other hand, as shown in FIG.
A resin-sealed semiconductor device 12 having a structure in which the
In the figures, parts indicated by the same reference numerals as in FIGS. 6 to 8 are the same parts as in the semiconductor device shown in FIGS. 6 to 8).
第6図のごときフイン付き構造の樹脂封止型半
導体装置においては、次のような欠点があつた。
The resin-sealed semiconductor device having a finned structure as shown in FIG. 6 has the following drawbacks.
該半導体装置を電子機器に組み込む際に樹脂
モールド部5の側面からフイン3が突出してい
るので占有面積を広く要し、従つて、該半導体
装置を含む回路部品の実装密度が低くなつて電
子機器の小型化を阻害する結果となつている。 When the semiconductor device is assembled into an electronic device, the fins 3 protrude from the side surface of the resin molded portion 5, so a large area is required, and therefore, the mounting density of circuit components including the semiconductor device is lowered. This results in hindering the miniaturization of the device.
樹脂モールド部側面からリード部6ばかりで
なくフイン3も突出しているため、樹脂モール
ド部に湿気が侵入しやすい構造となつている。
特に、樹脂モールド部側面に突出しているフイ
ン3の根元の部分は第8図に示すようにチツプ
取付ベツド部2と連続した同一水平面上にある
ため、湿気の侵入経路が直線的で非常に短く、
従つて半導体チツプ8が湿気に侵されやすい。 Since not only the lead part 6 but also the fin 3 protrude from the side surface of the resin mold part, the structure is such that moisture easily enters the resin mold part.
In particular, the root part of the fin 3 that protrudes from the side surface of the resin mold part is on the same horizontal plane that is continuous with the chip mounting bed part 2, as shown in Figure 8, so the path for moisture to enter is straight and very short. ,
Therefore, the semiconductor chip 8 is easily attacked by moisture.
幅広のフイン3を設けたため、リード部6の
数が少なくなり、従つて半導体装置のピン数
(外部端子の数)を減らさねばならないが、高
集積度の半導体チツプでは逆に従来よりも多く
のピンを必要とするので、該フイン3を設ける
ことは素子の高集積化を阻害することになる。
従つて、チツプ取付ベツド部2にフイン3を設
けたリードフレームを使用して従来品と同じピ
ン数の半導体装置を構成するには半導体装置の
平面面積を大型化しなければならないが、大型
になれば電子機器等における回路部品の実装密
度が低下して該電子機器等の小型化も阻害され
ることになる。また、フイン3を設けるととも
にピン数を従来の半導体装置と同数にすると、
各リード部6の内側端部とチツプ取付ベツド部
2との間の距離を大きくせざるを得なくなり、
その結果、各リード部に接続するボンデイング
ワイヤが長くなつて該ボンデイングワイヤとチ
ツプ取付ベツド部との接触が生じやすくなつた
り、或いはボンデイングワイヤ相互の接触が生
じやすくなる等の問題が起こり、従つて不良品
発生の確率が著しく増大する。 Since the wide fins 3 are provided, the number of lead parts 6 is reduced, and therefore the number of pins (the number of external terminals) of the semiconductor device must be reduced. Since pins are required, providing the fins 3 hinders high integration of the device.
Therefore, in order to construct a semiconductor device with the same number of pins as the conventional product by using a lead frame with fins 3 provided in the chip mounting bed portion 2, the planar area of the semiconductor device must be increased. For example, the mounting density of circuit components in electronic devices and the like is reduced, and miniaturization of the electronic devices and the like is also hindered. Also, if the fins 3 are provided and the number of pins is the same as that of conventional semiconductor devices,
The distance between the inner end of each lead part 6 and the chip mounting bed part 2 has to be increased.
As a result, problems arise, such as the bonding wires connected to each lead become longer and the bonding wires are more likely to come into contact with the chip mounting bed, or the bonding wires are more likely to come into contact with each other. The probability of producing defective products increases significantly.
一方、第9図の如くチツプ取付ベツド部のない
リードフレームを用いるとともにヒートシンク1
1上に半導体チツプ8を取り付けた構造の樹脂封
止型半導体装置12は、第6図の半導体装置より
も更に放熱性能が高いが、このヒートシンク付き
半導体装置は樹脂モールド前のリードフレーム対
する該ヒートシンクの取付をかしめ等によつて行
わなければならぬため、従来の半導体装置にくら
べて製造コストが非常に高額となるという問題点
を有している。 On the other hand, as shown in Fig. 9, a lead frame without a chip mounting bed is used, and a heat sink 1
A resin-sealed semiconductor device 12 having a structure in which a semiconductor chip 8 is mounted on the semiconductor chip 1 has higher heat dissipation performance than the semiconductor device shown in FIG. Since the mounting must be done by caulking or the like, the manufacturing cost is much higher than that of conventional semiconductor devices.
この発明の目的は、放熱性を向上させた前記の
ごとき公知の半導体装置に存する問題点を有しな
い樹脂封止型半導体装置を提供することであり、
更に詳細には、この発明の目的は、小型で且つ放
熱性が良好であるとともに耐湿性の低さやボンデ
イングワイヤに基因する不良品を発生する恐れが
なく、また安価なコストで製造することのできる
樹脂封止型半導体装置を提供することである。
An object of the present invention is to provide a resin-sealed semiconductor device that has improved heat dissipation and does not have the problems of the known semiconductor devices as described above.
More specifically, it is an object of the present invention to be small in size, have good heat dissipation properties, be free from the risk of producing defective products due to low moisture resistance or bonding wires, and be able to be manufactured at low cost. An object of the present invention is to provide a resin-sealed semiconductor device.
この発明による樹脂封止型半導体装置はチツプ
取付ベツド部を有するリードフレームを使用して
構成されており、該チツプ取付ベツド部の外周縁
に下向きに折り曲げた折曲片を形成するとともに
該折曲片の一部もしくは先端部を樹脂モールド部
の下面に露出させたことを特徴とするものであ
る。このような構造の本発明の樹脂封止型半導体
装置は、該折曲片が放熱体となつているため従来
のフインなし半導体装置よりも放熱性にすぐれて
いるうえ、該折曲片の露出端とチツプ取付ベツド
部との間の界面距離が長くしかも屈曲しているの
で耐湿性は従来のフインなし半導体装置と比較し
て少なくともよくなつており、且つ、ヒートシン
クを使用しないため製造コストは前記のフイン付
き半導体装置とほぼ同じである。また、樹脂モー
ルド部の側面に突出するフインがないため従来の
フインなし半導体装置と同じ数の接続リード部
(すなわちピン)を設けることができ、従つて、
ピン数の多い高密度半導体装置を構成することが
できる。
The resin-sealed semiconductor device according to the present invention is constructed using a lead frame having a chip mounting bed, and a bent piece bent downward is formed on the outer periphery of the chip mounting bed. It is characterized in that a part or tip of the piece is exposed on the lower surface of the resin molded part. The resin-sealed semiconductor device of the present invention having such a structure has better heat dissipation than conventional finless semiconductor devices because the bent piece serves as a heat dissipation body. Since the interface distance between the edge and the chip mounting bed is long and curved, the moisture resistance is at least better than that of conventional finless semiconductor devices, and since no heat sink is used, the manufacturing cost is lower than the above. It is almost the same as the semiconductor device with fins. Furthermore, since there are no fins protruding from the side surface of the resin molded part, the same number of connection lead parts (i.e., pins) can be provided as in conventional finless semiconductor devices.
A high-density semiconductor device with a large number of pins can be constructed.
以下に第1図乃至第5図を参照して本発明の実
施例について説明する。なお、同図において、第
6図乃至第9図と同一符号で表示された部分は公
知の半導体装置と同じ部分を表す。
Embodiments of the present invention will be described below with reference to FIGS. 1 to 5. In this figure, parts indicated by the same reference numerals as in FIGS. 6 to 9 represent the same parts as in the known semiconductor device.
第1図及び第2図は本発明による改良された樹
脂封止型半導体装置13及び14の断面図であ
る。 1 and 2 are cross-sectional views of improved resin-sealed semiconductor devices 13 and 14 according to the present invention.
この実施例の樹脂封止型半導体装置13及び1
4は、第3図に示すごときチツプ取付ベツド部1
5を備えたリードフレーム16を用いて構成され
ており、特に、該チツプ取付ベツド部15の外周
縁を下向きに折り曲げることによつて形成した折
曲片17を有していることを特徴とする。該折曲
片17の先端は第1図及び第2図並びに第5図に
おいて明らかであるように樹脂モールド部5の下
面に露出しており、従つて、該折曲片17は公知
のフイン付き半導体装置のフイン3(第6図)と
同じく放熱板としての機能を有している。また、
この樹脂封止型半導体装置13及び14に使用さ
れるリードフレーム16(第5図)においては、
樹脂モールド部5の側面に突出するフインがない
ため該折曲片17と同じ側にも多数のリード部6
を設けることができ、従つて本発明の半導体装置
では総ピン数が公知のフイン付き半導体装置のそ
れよりもかなり多くなつている。 Resin-sealed semiconductor devices 13 and 1 of this example
4 is a chip mounting bed part 1 as shown in FIG.
5, and is particularly characterized by having a bent piece 17 formed by bending the outer peripheral edge of the chip mounting bed portion 15 downward. . As is clear from FIGS. 1, 2, and 5, the tip of the bent piece 17 is exposed on the lower surface of the resin molded part 5, and therefore, the bent piece 17 has a known fin structure. Like the fins 3 (FIG. 6) of a semiconductor device, it has a function as a heat sink. Also,
In the lead frame 16 (FIG. 5) used in the resin-sealed semiconductor devices 13 and 14,
Since there are no fins protruding from the side surface of the resin molded part 5, there are many lead parts 6 on the same side as the bent piece 17.
Therefore, in the semiconductor device of the present invention, the total number of pins is considerably larger than that of a known semiconductor device with fins.
それ故、前記のごとき本発明の半導体装置13
及び14は、公知のフイン付き半導体装置と同じ
程度の放熱性能を有するとともに公知のフイン付
き半導体装置よりも多数のピンを有し、またヒー
トシンクを使用しないので公知のヒートシンク付
き半導体装置にくらべて著しく安価なコストで製
造できる等の利点を有している。 Therefore, the semiconductor device 13 of the present invention as described above
and 14 have heat dissipation performance comparable to that of known semiconductor devices with fins, have a larger number of pins than known semiconductor devices with fins, and do not use a heat sink, so they are significantly more efficient than known semiconductor devices with heat sinks. It has advantages such as being able to be manufactured at low cost.
なお、第2図に示した実施例の半導体装置14
では、第1図に示した実施例のものにくらべて、
チツプ取付ベツド部15がリード部6よりも下方
に位置しているデイプレス型に適用したものであ
るため、ボンデイングワイヤ10がチツプ取付ベ
ツド部15に接触する恐れがなく、より望ましい
構造となつている。 Note that the semiconductor device 14 of the embodiment shown in FIG.
Now, compared to the embodiment shown in FIG.
Since this is applied to a dayless type in which the chip mounting bed section 15 is located below the lead section 6, there is no risk that the bonding wire 10 will come into contact with the chip mounting bed section 15, resulting in a more desirable structure. There is.
また、デイプレス型の場合には、チツプ取付ベ
ツド部の下面と樹脂モールド部下面との間が短い
ため折曲片を絞り加工でなく折曲げ加工ででき、
絞り加工の場合よりも折曲片の肉厚が厚くなつて
放熱性能を高めることができる。 In addition, in the case of the daypress type, since the distance between the lower surface of the chip mounting bed and the lower surface of the resin mold is short, the bent piece can be bent instead of drawing.
The thickness of the bent piece is thicker than in the case of drawing, and heat dissipation performance can be improved.
第1図及び第2図に示した本発明の樹脂封止型
半導体装置並びに公知のフイン付き半導体装置
(第6図参照)及び従来のフインなし半導体装置
に対して熱抵抗値を測定した結果、本発明の半導
体装置の熱抵抗値はフイン付き半導体装置のそれ
よりもわずかに高かつたが、従来のフインなし半
導体装置よりも著しく小さく(約1/5弱)、本発明
の半導体装置がフイン付き半導体装置とほぼ同程
度の放熱性能を有していることが明らかになつ
た。また、製造コストについて試算した結果、本
発明の半導体装置は従来のフインなし半導体装置
とほぼ同コストで製造できることが確認された。
As a result of measuring thermal resistance values for the resin-sealed semiconductor device of the present invention shown in FIGS. 1 and 2, a known semiconductor device with fins (see FIG. 6), and a conventional semiconductor device without fins, Although the thermal resistance value of the semiconductor device of the present invention was slightly higher than that of the semiconductor device with fins, it was significantly lower (about 1/5) than that of the conventional semiconductor device without fins. It has been revealed that the heat dissipation performance is almost the same as that of the semiconductor device with the integrated circuit. Further, as a result of trial calculations regarding manufacturing costs, it was confirmed that the semiconductor device of the present invention can be manufactured at approximately the same cost as a conventional finless semiconductor device.
以上のように、本発明によれば、公知のフイン
付き半導体装置よりも高い実装密度で電子機器等
に実装できるとともに該フイン付き半導体装置と
ほぼ同程度の良好な放熱性能を有し、且つ従来の
フインなし半導体装置の製造コストとほぼ同程度
の安価な製造コストで製造することができる小型
の樹脂封止型半導体装置が提供される。 As described above, according to the present invention, it is possible to mount it in electronic equipment etc. with a higher packaging density than known semiconductor devices with fins, and it has good heat dissipation performance that is almost the same as that of the semiconductor devices with fins. A small resin-sealed semiconductor device that can be manufactured at a manufacturing cost that is approximately the same as the manufacturing cost of a finless semiconductor device is provided.
第1図及び第2図はそれぞれ本発明の実施例の
樹脂封止型半導体装置の断面図、第3図は第1図
及び第2図の半導体装置に使用するリードフレー
ムの平面図、第4図は第3図の−断面図、第
5図は第4図のリードフレームに半導体チツプを
搭載した後に樹脂モールド部を形成した状態の下
面図、第6図は公知のフイン付き樹脂封止型半導
体装置の斜視図、第7図は第6図の半導体装置に
使用するリードフレームに半導体チツプを搭載し
た状態の平面図、第8図は第6図の−矢視断
面図、第9図は公知のヒートシンク付き樹脂封止
型半導体装置の断面図である。
1,12,13,14…樹脂封止型半導体装
置、2,15…チツプ取付ベツド部、3…フイ
ン、4,16…リードフレーム、5…樹脂モール
ド部、6…リード部、7…タイバー、8…半導体
チツプ、9…はんだ、10…ボンデイングワイ
ヤ、11…ヒートシンク、17…折曲片。
1 and 2 are cross-sectional views of resin-sealed semiconductor devices according to embodiments of the present invention, FIG. 3 is a plan view of a lead frame used in the semiconductor devices of FIGS. 1 and 2, and FIG. The figure is a cross-sectional view of Figure 3, Figure 5 is a bottom view of the resin molded part formed after mounting the semiconductor chip on the lead frame of Figure 4, and Figure 6 is a known resin-sealed type with fins. A perspective view of a semiconductor device, FIG. 7 is a plan view of a semiconductor chip mounted on a lead frame used in the semiconductor device of FIG. 6, FIG. 8 is a sectional view taken along the - arrow in FIG. 6, and FIG. 1 is a cross-sectional view of a known resin-sealed semiconductor device with a heat sink. DESCRIPTION OF SYMBOLS 1, 12, 13, 14... Resin-sealed semiconductor device, 2, 15... Chip mounting bed part, 3... Fin, 4, 16... Lead frame, 5... Resin mold part, 6... Lead part, 7... Tie bar, 8... Semiconductor chip, 9... Solder, 10... Bonding wire, 11... Heat sink, 17... Bent piece.
Claims (1)
ベツド部と、該チツプ取付ベツドの周囲に配置さ
れた多数のリード部とを有するリードフレームを
使用し、該チツプ取付ベツド部に固定された半導
体チツプと該チツプ取付ベツド部と該リード部の
一端側とを樹脂モールド部によつて封止して構成
される樹脂封止型半導体装置において、 該チツプ取付ベツド部の表面に対して該チツプ
取付部の外周縁部を折り曲げ又は絞ることなどに
より該チツプ取付ベツド部の外周縁に折曲片を形
成するとともに該折曲片の一部もしくは先端部を
該樹脂モールド部の下面に露出させたことを特徴
とする樹脂封止型半導体装置。[Claims] 1. A lead frame having a chip mounting bed portion for mounting a semiconductor chip and a number of lead portions arranged around the chip mounting bed is used, and the lead frame is fixed to the chip mounting bed portion. In a resin-sealed semiconductor device configured by sealing a semiconductor chip, a chip mounting bed portion, and one end side of the lead portion with a resin mold portion, a resin-molded semiconductor device is provided, in which By bending or squeezing the outer peripheral edge of the chip mounting part, a bent piece is formed on the outer peripheral edge of the chip mounting bed part, and a part or the tip of the bent piece is exposed on the lower surface of the resin mold part. A resin-sealed semiconductor device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59207188A JPS6185846A (en) | 1984-10-04 | 1984-10-04 | Resin-encapsulated semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59207188A JPS6185846A (en) | 1984-10-04 | 1984-10-04 | Resin-encapsulated semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6185846A JPS6185846A (en) | 1986-05-01 |
| JPH0210579B2 true JPH0210579B2 (en) | 1990-03-08 |
Family
ID=16535702
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59207188A Granted JPS6185846A (en) | 1984-10-04 | 1984-10-04 | Resin-encapsulated semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6185846A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19639183A1 (en) * | 1996-09-24 | 1998-04-02 | Siemens Ag | Connection frame for a microelectronic component, method for its production and microelectronic component comprising the connection frame |
-
1984
- 1984-10-04 JP JP59207188A patent/JPS6185846A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6185846A (en) | 1986-05-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7781265B2 (en) | DFN semiconductor package having reduced electrical resistance | |
| US6420779B1 (en) | Leadframe based chip scale package and method of producing the same | |
| US6566164B1 (en) | Exposed copper strap in a semiconductor package | |
| US6157074A (en) | Lead frame adapted for variable sized devices, semiconductor package with such lead frame and method for using same | |
| US7321162B1 (en) | Semiconductor package having reduced thickness | |
| KR940007757Y1 (en) | Semiconductor package | |
| US8575742B1 (en) | Semiconductor device with increased I/O leadframe including power bars | |
| US7847392B1 (en) | Semiconductor device including leadframe with increased I/O | |
| JP2000133767A (en) | Laminated semiconductor package and method of manufacturing the same | |
| KR19980032479A (en) | Surface installation TO-220 package and its manufacturing process | |
| US7102208B1 (en) | Leadframe and semiconductor package with improved solder joint strength | |
| JP2905609B2 (en) | Resin-sealed semiconductor device | |
| US20060145312A1 (en) | Dual flat non-leaded semiconductor package | |
| JPH0210579B2 (en) | ||
| JP2002076234A (en) | Resin-sealed semiconductor device | |
| KR0148078B1 (en) | Lead on chip having forward lead | |
| JP3920753B2 (en) | Semiconductor device and electronic device incorporating the same | |
| US7951651B2 (en) | Dual flat non-leaded semiconductor package | |
| JP2001135767A (en) | Semiconductor device and method of manufacturing the same | |
| KR19990086280A (en) | Semiconductor package | |
| JPH0314229B2 (en) | ||
| JPH05259343A (en) | Manufacture of semiconductor module | |
| JPS5986251A (en) | Leadframe for resin-sealed semiconductor device | |
| JPH11354673A (en) | Semiconductor device | |
| KR100252862B1 (en) | Semiconductor package and method for fabricating the same |