JPH0212016B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to field effect transistors. In recent years, field effect transistors using semiconductors such as gallium arsenide (GaAs) have been developed.

In order to increase the gain and reduce the noise of this field effect transistor, one of the important issues is how to reduce the gate-source resistance. The resistance per unit device width between the gate and source is
The distance between the gate electrode and the source electrode, the thickness of the channel where carriers exist, the carrier concentration,
Depends on carrier mobility. At this time, since the vicinity of the semiconductor surface is depleted, the thickness of the channel portion is narrowed by the amount of depletion. Conventionally, in order to reduce this gate-source resistance, methods such as shortening the distance between the gate electrode and the source electrode and further recessing the gate have been used. However, the gate-source resistance has not been reduced by removing the depletion layer (surface depletion layer) formed on the semiconductor surface.

An object of the present invention is to provide a field effect transistor whose gate-source resistance can be reduced by removing the surface depletion layer of the semiconductor.

According to the present invention, an insulating film is provided on the active layer between the source electrode and the drain electrode of a field effect transistor consisting of three electrodes, a source, a gate, and a drain, and covers the gate electrode. A field effect transistor is obtained, characterized in that a second insulated gate electrode is provided that covers the entire active layer.

In the present invention, the surface depletion layer can be removed by DC biasing the second insulated gate electrode, so that the gate-source resistance is reduced and high gain and low noise can be achieved.

Hereinafter, details of the present invention will be explained using the drawings.

FIG. 1 is a diagram showing a field effect transistor which is an embodiment of the present invention, in which a is a cross-sectional view and b is a plan view.

FIG. 2 shows an amplifier circuit using the field effect transistor of the present invention.

In FIG. 1a, a source electrode 2 made of a metal that forms an ohmic junction and a drain electrode 3 made of a metal that also forms an ohmic junction are provided on an n-layer 4 formed by ion implantation into a semi-insulating GaAs substrate 5. It is being A first gate electrode 1 made of metal and forming a Schottky junction is provided between the source electrode 2 and drain electrode 3.

An insulating film 6 is provided on the surface between the end 42 of the source electrode 2 on the drain electrode side and the end 43 of the drain electrode 3 on the source electrode side so as to cover the first gate electrode 1 as well, A second gate electrode 7 is provided on the insulating film 6. 8 indicates a surface depletion layer when the second gate electrode 7 is not provided.

In FIG. 1b, 9 is a bonding pad of the first gate electrode 1, and 10 is a bonding pad of the second gate electrode 7. In FIG.

In FIG. 2, 32 is a symbol representing a field effect transistor of the present invention, 34 is a source electrode, and 3 is a symbol representing a field effect transistor of the present invention.
3 is a drain electrode, 36 is a first gate electrode, 35
is the second gate electrode. A DC blocking capacitor 23 is provided between the first gate electrode 1 and the amplifier input terminal 21, and the input terminal 21 is provided with a DC blocking capacitor 23.
A resistor 22 for reducing VSWR is provided in parallel. Further, a first gate bias DC negative voltage 25 is applied to the first gate electrode 36 through the resistor 24 . A second gate bias DC positive voltage 26 is applied to the second gate electrode 35 . The source electrode 34 is grounded, and the drain electrode 3
A DC blocking capacitor 31 is provided between the amplifier output terminal 30 and the amplifier output terminal 30. A drain bias positive voltage 29 is applied to the drain electrode 33 through a load resistor 28, and the load resistor 28 and the drain bias positive voltage are short-circuited by a capacitor 27 in an alternating current manner.

In such a field effect transistor, by biasing the second gate electrode to a positive voltage, the depletion layer formed on the n-channel surface can be completely canceled out, and the gate-source resistance can be reduced. This increases the amplification gain,
Moreover, it becomes possible to reduce noise.

As described above, according to the present invention, an insulated second gate electrode is provided above the FET channel portion where a surface depletion layer has occurred, and the surface depletion layer is completely eliminated by biasing this second gate electrode. Therefore, low gate-source resistance can be achieved even in FETs with a planar structure, and this effect is particularly remarkable in integrated circuits.

Note that in this embodiment, the first gate is a Schottky junction gate, but the first gate is not limited to a Schottky junction gate, and may also be a pn junction gate,
It may be any type of insulated gate. Furthermore, the semiconductor substrate is not limited to GaAs. Furthermore, the channel is not limited to an n-channel, but may be a p-channel.

[Brief explanation of drawings]

FIG. 1 shows a field effect transistor that is an embodiment of the present invention, in which a is a cross-sectional view and b is a plan view. FIG. 2 shows an amplifier using the field effect transistor. In FIG. 1, 1 is a first gate electrode, 2 is a source electrode, 3 is a drain electrode, 5 is a semi-insulating GaAs, 4 is an n layer, 6 is an insulating film, 7 is a second gate electrode, 42 and 43 are They represent the ends of the source and drain electrodes, respectively. 9 is a bonding pad for the first gate, and 10 is a bonding pad for the second gate. In Figure 2, 2
2, 24, and 28 are resistors, 23, 27, and 31 are capacitors, 25, 26, and 29 are DC voltage sources, 21 is an amplifier input terminal, and 30 is an amplifier output terminal.
32 is a field effect transistor according to the present invention;
3, 34, 35, 36 are drain, source,
These are the electrodes of the second gate and the first gate.

Claims (1)

[Claims] 1. An insulating film covering the gate electrode is provided on the active layer between the source electrode and the drain electrode of a field effect transistor consisting of three electrodes, a source, a gate, and a drain, and the entire active layer is covered on the insulating film. A field effect transistor characterized in that a covering insulated second gate electrode is provided.