JPH0212406B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an amplifier circuit, and particularly to a transistor amplifier suitable for obtaining a large output voltage.

Generally, in the case of an oscilloscope's vertical output amplifier, the delay line output of a specific impedance (for example, 50Ω) is used to drive the vertical deflection plate of a cathode ray tube.
Amplify to a push-pull voltage of volts. A typical example of a conventional circuit is a common-base stage _Q1 with emitter resistors Ro and Ro' for delay line termination, as shown in Figure 1.
_Q1 ', a common emitter amplifier stage _Q2 - _Q2 ', and a cascode-connected amplifier stage including a common emitter stage _Q3 - _Q3 ' and a common-base stage _Q4 - _Q4 '.

By the way, in the conventional circuit as shown in Fig. 1,
Since the gain is determined by the current amplification factor of the transistor, various complicated compensation circuit networks are required due to the problem of drift due to temperature and variations in gain and frequency characteristics due to temperature.

In view of these points, the present invention provides an amplifier circuit in which the gain is easily and precisely determined by using a material whose gain is not easily affected by the current amplification factor of the transistor, and has stable temperature characteristics without drift problems. It provides:

An embodiment of the present invention will be described in detail below with reference to FIGS. 2 to 8.

FIG. 2 shows an embodiment of the present invention in block configuration. In the figure, A ₁ is a voltage-to-current conversion type feedback amplifier stage, A ₂ is a current amplification type feedback amplifier stage, and A ₃ is a current amplification type feedback amplifier stage.
is a common base amplifier stage. Each of these amplifier stages can be connected in cascade to obtain a large output voltage.

FIG. 3 shows a specific example of the circuit shown in FIG. In the figure, input terminals 1 and 1' are connected to the bases of transistors Q ₃₁ -Q ₃₁ ', respectively.
Further, resistors for determining input impedance, such as delay line terminating resistors 2 and 2', are connected in series between the input terminals 1 and 1', and the connection point of these resistors is grounded. The emitter of transistor Q ₃₁ is connected to the transistor through emitter resistors 3 and 3' connected in series.
It is connected to the emitter of Q ₃₁ ', and the connection point of resistors 3 and 3' is connected to the negative power supply via resistor 4. The collectors of transistors Q ₃₁ and Q ₃₁ ′ are each a transistor.
Q ₃₂ - Connected to the base of Q ₃₂ ′. In addition, the collector of these transistors Q ₃₁ and the transistor
A positive power supply is applied to the base of Q ₃₂ via a resistor, while a positive power supply is similarly applied to the collector of transistor Q ₃₁ ′ and the base of transistor Q ₃₂ ′ via a resistor. The collector of transistor Q ₃₂ is connected to the collector of transistor Q ₃₂ ′ through series-connected resistors 5 and 5′.
connection point is connected to the negative power supply. The collector of transistor Q ₃₂ is connected to the emitter of transistor Q ₃₁ via feedback resistor 6, while the collector of transistor Q ₃₂ ' is connected to the emitter of transistor Q ₃₁ ' via feedback resistor 6'. These transistors Q ₃₁ -Q ₃₁ ′ and Q ₃₂ -Q ₃₂ ′ constitute a voltage-current conversion type feedback amplifier stage A ₁ .
In other words, the transistor is connected from input terminals 1 and 1'.
When an input signal voltage is supplied to the bases of Q ₃₁ -Q ₃₁ ', a corresponding output signal current is extracted from the emitter side of the transistors Q ₃₂ -Q ₃₂ '. As will be described later, the gain of this feedback amplifier stage _A1 is determined by the resistors 3,
It is determined by the resistance values of 5 and 6.

The emitters of transistors Q ₃₂ -Q ₃₂ ' are connected to the emitters of transistors Q ₃₃ -Q ₃₃ ' in the next stage, respectively. A desired positive bias voltage is applied to the bases of transistors Q ₃₃ -Q ₃₃ ' via a resistive voltage divider. The collector of transistor Q ₃₃ is connected to the positive power supply through a resistor and to the base of transistor Q ₃₄ , while the collector of transistor Q ₃₃ ' is connected to the positive power supply through a resistor and to the base of transistor Q ₃₄ '. connected to the base. The collector of transistor Q ₃₄ is connected to the collector of transistor Q ₃₄ ' via series-connected resistors 7 and 7', and the connection point of resistors 7 and 7' is connected to the negative power supply. The collector of transistor Q ₃₄ is connected to the emitter of transistor Q ₃₃ via feedback resistor 8, and the collector of transistor Q ₃₄ ' is connected to the emitter of transistor Q ₃₃ ' via feedback resistor 8'. These transistors Q ₃₃ - Q ₃₃ ' and Q ₃₄ - Q ₃₄ ' constitute a current-amplifying feedback amplifier stage A ₂ , which outputs a signal corresponding to the emitter input signal current to the transistors Q ₃₃ - Q ₃₃ '. Current is obtained from the emitters of transistors Q ₃₄ -Q ₃₄ '.

The emitters of the transistors Q ₃₄ -Q ₃₄ ' are connected to the emitters of the output stage transistors Q ₃₅ -Q ₃₅ ', respectively. The base of transistor Q ₃₅ is connected to the base of transistor Q ₃₅ ' via series-connected resistors 9 and 9', and the connection point of resistors 9 and 9' is connected to the positive power supply. In addition, the collector of the transistor _Q35 is connected in series with inductors 10, 10' and resistors 11, 1.
1' to the collector of transistor Q ₃₅ '. The connection point of resistors 11 and 11' is connected to a positive power supply of several tens of volts, and the inductor 1
Output terminals 12, 0 and 10' from intermediate taps, respectively.
12' is taken out. These transistors Q ₃₅
-Q ₃₅ ' constitutes a common base output stage.

Here, the gains of the feedback amplifier stages A ₁ and A ₂ are calculated as follows with reference to the equivalent circuits shown in FIGS. 4 and 5, respectively.

First, regarding the gain of the feedback amplifier stage _A1 , assuming that the current amplifier factors β of the transistors _Q31 - _Q32 are equal, the input signal _e1 supplied to the input terminal 1 is expressed by the following equation. .

e ₁ = Re {(1 + β) i ₁ + i ₂ } ...(1) However, in the above equation (1), Re is the resistance value of resistor 3, i ₁ is the base current flowing to the base of transistor Q ₃₁ , and i ₂ is the resistance value of resistor 6. is the current flowing through.

Further, the following equation is established from a closed circuit including resistors 3, 5, and 6.

Rc (β ² i ₁ − i ₂ ) = R _f i ₂ + Re {(1 + β) i ₁ + i ₂ }…(2) However, in the above equation (2), Rc is the resistance value of resistor 5, and R _f is the resistance value of resistor 6. is the resistance value of

From the above equations (1) and (2), {β ² R _c −(1+β)R _e }i ₁ =(R _c +R _f +R _e )i ₂ (3) is obtained. From this formula (3), i ₂ = β ₂ R _c − (1 + β) R _e /R _c +R _f +R _e i ₁ β ² R _c /R _c
+R _f +R _e i ₁ (4) Therefore, from the above equations (1) and (4), the input signal e ₁ is expressed by the following equation.

e ₁ R _e {(1+β)+β ₂ R _c /R _c +R _f +R _e }i ₁ β ² R _c R _e /R _c +R _f +R _e i ₁ …(5) Therefore, the output signal current, that is, the transistor
The current I ₁ flowing through the emitter of Q ₃₂ is expressed by the following equation.

I ₁ = β (1 + β) i ₁ β ² i ₁ R _c +R _e +R _f /R _c R _e e ₁ …(
6) From this equation (6), it can be seen that the output current I ₁ is determined by the resistance values of the resistors 3, 5, and 6, and is hardly affected by temperature drift. Note that the transistors Q _{31 ′} , which are paired with the transistors Q _{31 and Q 32 ,}
Q ₃₂ ′ can also be found in the same way.

Next, use FIG. 5 to calculate the gain of the feedback amplifier stage _A2 . Here, it is assumed that the current amplification factors β of transistors Q ₃₃ and Q ₃₄ are also equal.

Now, if the resistance value of the resistor 7 is R _c , the resistance value of the resistor 8 is R _f , the current flowing through the emitter of the transistor Q ₃₃ is i ₁ , and the current flowing through the collector is i ₂ , the following equation holds true.

R _f (i ₁ − i ₂ )=R _c {(1+β) i ₂ −i ₁ } …(7) Rearranging this equation (7), (R _f +R _c )i ₁ = {R _f +(1+β) R _c }i ₂ …(8) is obtained. From this formula (8), i ₂ = R _f + R _c / (1 + β) R _c + R _f i ₁ R _f + R _c / (1 + β
) R _c i ₁ …(9) Therefore, the output signal current, that is, the transistor Q ₃₄
The emitter current I ₂ of is expressed by the following equation.

I ₂ = (1 + β) i ₂ R _f + R _c /R _c i ₁ ...(10) From the above equation (10), the output signal current I ₂ is also determined by the resistance values of resistors 7 and 8, which almost eliminates the temperature problem. It turns out that this does not occur. Note that the same applies to transistors Q _{33 ′} and Q ₃₄ ′ that form a pair with transistors Q ₃₃ and Q ₃₄ .

FIG. 6 shows an example of application of the amplifier circuit according to the present invention, in which a selective amplifier is configured.

That is _, in FIG. 6, _the output of _the amplifier stage A ₁ of FIG _.
Utilizing the novel configuration of Q ₃₃ ′, we added transistors to it.
An amplifier consisting of Q ₄₁ - Q ₄₁ ′ is added.

In FIG. 6, input terminals 41 and 41' to which the first input signal e ₁ is supplied are connected to transistors Q _{31 and 41} ', respectively.
Q ₃₂ ' and resistors 42, 42' are connected in series between these bases, and these resistors 42, 42' are connected in series between these bases.
Bias voltages V ₁ and V ₂ are selectively applied to the transistors by switching switch 43 via terminal 42'.
It should be supplied to the bases of Q ₃₂ and Q ₃₂ ′.

Further, the emitter connection point of transistors Q ₃₂ and Q ₃₃ is connected to the collector of transistor Q ₄₁ , and the emitter connection point of transistors Q ₃₂ ′ and Q ₃₃ ′ is connected to the collector of transistor Q ₄₁ ′. Also, the emitter of transistor _Q41 is connected to resistors 44 and 4.
4' to the emitter of the transistor Q ₄₁ ', and the connection point of the resistors 44 and 44' is connected to the negative power supply via a switch 45 and a constant current source 46. Also, the bases of transistors Q ₄₁ and Q ₄₁ ' are connected to the second
input terminals 47, 47' to which the input signal e ₂ of
Connect to.

In other words, in the circuit example shown in Figure 6, the output side of amplifier stage A ₁ in Figure 3 is a base input and emitter output, and the input side of amplifier stage A ₂ is a grounded base configuration. A selective amplifier is constructed by combining the transistors with other grounded-emitter transistors Q ₄₁ -Q ₄₁ '.

With this configuration, by switching the switches 43 and 45, the transistors Q ₃₂ -Q ₃₂ ' and the transistor Q ₃₃
- Q ₃₃ ' or the two pairs of transistors Q ₄₁ - Q ₄₁ ' and transistors Q ₃₃ - Q ₃₃ ' are supplied to the input terminals ₄₁ , 41'. 47, 47' and selectively amplifies the second input signal e ₂ supplied to transistors Q ₃₃ -
output terminals 48 connected to the collectors of Q _{33 ′} , respectively;
48'. That is, this circuit can selectively take out a plurality of desired input signals without inserting any switches in series in the signal path, and is therefore particularly useful for high frequency signal processing.

FIG. 7 shows an example of an amplifier circuit suitable for the digital storage oscilloscope vertical output amplifier 85 shown in FIG. 8, which is essentially a combination of the circuit shown in FIG. 3 and the circuit shown in FIG. be.

In FIG. 7, transistors Q ₅₁ and Q ₅₂ are further provided to perform a selection operation. The base of transistor Q ₅₁ is connected to control signal input terminal 53 via resistor 51 and diode 52 . This input terminal 53
A switching control signal corresponding to the switching signal from the switch circuit 91 shown in FIG. 8 is supplied to the switch circuit 91 shown in FIG. Further, the emitter of the transistor Q ₅₁ is connected to a positive power source, and the collector is connected to the base of a transistor Q ₅₂ via a resistor 54 and to a negative power source via a resistor 55. Further, the collector of transistor Q ₅₁ is connected to the emitters of transistors Q ₃₁ and Q ₃₁ ' via diodes 56 and 57, respectively. These diodes 56, 57 act as switch 43 in FIG. The emitter of transistor Q ₅₂ is connected to the negative power supply, and the collector is connected to resistor 58,
59 to the emitters of the transistors Q ₄₁ -Q ₄₁ ', that is, to both ends of the resistor 60. A first input signal e ₁ is supplied to input terminals 1 and 1',
On the other hand, a second input signal e ₂ is supplied to the input terminals 47 and 47', and these signals e ₁ and e ₂ are selectively taken out to the output terminals 12 and 12'.

Next, the operation of this circuit will be explained. Now, when the control signal supplied to the control signal input terminal 53 is at a low level, the transistor _Q51 is turned on, the level at the connection point P becomes high level, and the diode 56,
57 turns on. Therefore, transistor Q ₃₁ -
Q ₃₁ ′ is off. In other words, this is equivalent to the switch 43 in FIG. 6 being connected to the high voltage _V1 . Also, transistor Q ₅₂ is turned on due to the high level of connection point P, and along with this, transistor Q 52 is turned on.
Q ₄₁ -Q ₄₁ ′ becomes active. Therefore, the second input signal e ₂ supplied to the input terminals 47, 47' is connected to the cascode-connected transistors Q ₃₃ - Q ₃₃ ', Q ₃₄
- Q ₃₄ ', Q ₃₅ - Q ₃₅ ' via output terminals 12, 1
It is taken out at 2'.

On the other hand, when the control signal goes high, transistor Q ₅₁ turns off, resulting in diode 5
6 and 57 become non-conductive and the transistor
Q ₅₂ is also turned off, and the circuit in Figure 7 is connected to input terminals 1 and 1'.
The first input signal _e1 supplied to the transistor
It becomes a voltage-to-current conversion type feedback amplifier stage consisting of Q ₃₁ ―Q ₃₁ ′ and Q ₃₂ ―Q ₃₂ ′, and after converting the input signal voltage to the output signal current, the transistor Q ₃₃ ―Q ₃₃ ′ and the transistor Q ₃₄ ―Q ₃₄ ' is amplified by a current amplification type feedback amplifier stage, and further voltage amplified by a common base output stage composed of transistors _Q35 - _Q35 ', and corresponding outputs are taken out from output terminals 12 and 12'.

In this way, the input terminals 1, 1'
It operates as a selection amplifier that selectively takes out the first input signal e ₁ supplied to the input terminals 47, 47' or the second input signal e ₂ supplied to the input terminals 47, 47' to the output terminals 12, 12'.

FIG. 8 shows a block diagram of an example of a digital storage oscilloscope suitable for applying the amplifier circuit according to the present invention. Here, the amplifier circuit according to the present invention can be applied to the vertical output amplifier 85 of the oscilloscope.

The signal from the input terminal 81 is supplied to the amplifier 82 and amplified, and a part of the output is sent to the input amplifier 83.
The delayed output is supplied to one input terminal of a vertical output amplifier 85. In other words, this delayed output is the first
This corresponds to the input signal e ₁ of .

On the other hand, part of the output of the amplifier 82 is passed through a sample and hold circuit 86 to an analog/digital (A/
D) The signal is supplied to a converter 87, where the analog signal is converted into a digital signal, and then supplied to a memory 88, where it is stored at a predetermined address location in response to a write signal from a logic circuit 89. Then, the read signal from the logic circuit 89 causes the memory 8 to
8 is read out and supplied to a digital-to-analog (D/A) converter 90,
Here, the digital signal is converted into an analog signal and then supplied to the other input terminal of the vertical output amplifier 85. In other words, the signal from this D/A converter 90 corresponds to the second input signal _e2 in FIG. Note that the sample/hold circuit 86,
A/D converter 87 and D/A converter 90 are memory 8
Similarly to 8, it is controlled by a clock signal from a logic circuit 89. Further, a switching control signal is supplied to the vertical output amplifier 85 from a switch circuit 91. That is, this corresponds to the control signal supplied to the control signal input terminal 53 in FIG. The output of the vertical output amplifier 85 is supplied to a cathode ray tube 92 for driving a vertical deflection plate.

Further, the output of the amplifier 82 is supplied to a trigger circuit 94 via an internal/external changeover switch 93, and the output of the trigger circuit 94 is further supplied to a sweep generator 95 to obtain a desired sawtooth wave from its output side. This sawtooth wave is supplied to a horizontal output amplifier 97 via a switch 96, and the output of this amplifier 97 is supplied to a cathode ray tube 92 for driving a horizontal deflection plate. Further, 98 is an external signal input terminal, and 99 is a sweep generator that outputs a sawtooth wave in response to the clock from the logic circuit 89. The switch is selectively switched.

As described above, according to the present invention, as can be understood from equations (6) and (10) above, the gain of each stage is almost determined by the parameters of the passive elements regardless of the current amplification factor, so the gain Setting and adjustment are easy and highly accurate. Also, since the gains of amplifier stages A ₁ and A ₂ are both inversely proportional to the resistance value R _c of resistors 5 and 5', one or more RC series networks can be used in parallel with resistors 5 and 5' for high frequency compensation. good. Furthermore, because of the novel combination of amplifier stages A ₁ , A ₂ , a selective amplifier can be constructed very easily using additional amplifiers. Furthermore, since there is no problem of drift due to temperature and fluctuations in gain and frequency characteristics due to temperature, there is no need to use a complicated compensation network as in the past, and the circuit configuration becomes simple.

[Brief explanation of drawings]

FIG. 1 is a connection diagram showing an example of a conventional circuit, FIG. 2 is a block diagram showing an embodiment of the present invention, FIG. 3 is a connection diagram showing an example of a specific circuit configuration of the present invention, and FIGS. Fig. 5 is an equivalent circuit for explaining the operation of Fig. 3, Fig. 6 is a connection diagram showing an example of an applied amplifier of the present invention, and Fig. 7 is another example of an amplifier to which the present invention is applied. The connection diagram and FIG. 8 are block diagrams showing an example of a digital storage oscilloscope suitable for applying the present invention. A ₁ is a voltage-to-current conversion type feedback amplifier stage, A ₂ is a current amplification type feedback amplifier stage, and A ₃ is a common base amplifier stage.

Claims (1)

[Claims] 1. A first transistor whose base receives an input signal and whose emitter is connected to a power supply via a first resistor;
a second transistor whose base is connected to the collector of the first transistor and whose collector is connected to the power supply via a second resistor; a third resistor connected between the collector of the second transistor and the emitter of the first transistor; a voltage-to-current converting amplifier stage having an emitter connected to the emitter of the second transistor and a third transistor having a base receiving a bias voltage; a base connected to the collector of the third transistor, the collector having a fourth resistor; a current amplifier stage having a fourth transistor connected to a power supply through the current amplifier stage, a fifth resistor connected between the collector of the fourth transistor and the emitter of the third transistor, the emitter being connected to the emitter of the fourth transistor; , a common base amplifier stage having a fifth transistor generating an output signal at the collector.