JPH02124493A - timing device - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a timekeeping device that measures time.
The purpose of the present invention is to freely input and output timekeeping information to and from the outside, and to enable a series of timekeeping functions such as clocks, stopwatches, timers, and alarms by combining it with an external device (microcomputer C), and to enable a series of timekeeping functions such as clocks, stopwatches, timers, and alarms. By effectively utilizing signals for the microcomputer and notification means, the burden on the microcomputer is lightened and the number of peripheral devices is reduced.

Another object of the present invention is to input and output data to and from a microcomputer in addition to timekeeping information, thereby increasing multi-functionality. A further object of the present invention is to integrate a timekeeping device into a one-chip integrated circuit using low power elements such as C-MOS, so that timekeeping can be continued for a long time even when the main power of the microcomputer is turned off.

In the program store method, microcontrollers that enable specification changes and multifunctional processing are rapidly expanding in popularity. However, performing the timekeeping function with a microcontroller requires a timer calculation method, which cannot perform all calculations other than the timekeeping function, so it can be said that this is an impossible method for making it multifunctional.Other calculation methods are regular and accurate. It is possible to input the lock as an interrupt and perform timekeeping processing each time. However, with this method, the CRV is always occupied for timekeeping processing with a constant duty, and the timekeeping interrupt occurs during real-time processing, making real-time control difficult. The operation, etc. will be inaccurate.An even bigger drawback is that the microcontroller, which consumes a large amount of power, may turn on and off the main switch, or may turn on and off when moving, and the time information will evaporate during this time. Therefore, electronic circuits with timekeeping functions are desired to have low power and low voltage so that they can operate for long periods of time even with small-capacity batteries.

Another requirement is to simplify the input and output of information to and from the microcontroller. It can be accessed easily in the same way as Ilo and memory through a system bus or the like.

The present invention will be explained below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the invention.

1 is a 4.0MH2 crystal oscillator, 2 is an oscillation circuit, 3 is a frequency dividing circuit, 4 to 7 are counters, 8 is a latch circuit for write data bus, 9 is a latch circuit for selected data bus, IO is address information and A switching circuit 11 for switching data information, a switching circuit IO, a latch circuit 9. 12 is a read data bus, and 13 is a write data bus.

14 is a selection data bus, 15 is an address/data bus for exchanging data with an external device (microcomputer), 16 is a control circuit control signal sent from the external device to the control circuit 11, 17 is a buzzer drive control circuit, and 18 is a buzzer drive The circuit 19 is an in-loved signal generation circuit. A counter is omitted between counters 5 and 6, and each counter has a BCD 4-bit configuration.The 1 o'clock and month digits are 1-1.
It is a decimal number of 2. Counter 4-6. The buzzer drive control circuit 17 and the interwoven signal generation circuit 19 use the selection data bus 14 (SB, -SB,). Addresses are assigned to each and are shown in Table 1.

1st table counters 4-6. Buzzer drive control circuit 17. The interlaced signal generation circuit 19 has a built-in decoder for decoding data sent from the selected data bus, and 2
More than one digit is never selected at the same time, and the address/data bus 15 is used as a common input/output for digit addresses, time data, interlabel data, and buzzer data.The read data bus 12 and write data bus 13 and selective data bus 14 (.

By inputting and outputting address information and data information through a common bus, the number of bins is reduced, which is extremely advantageous in terms of cost. The latch circuit 8 holds the write data and outputs it to the write data bus 13. The latch circuit 9 holds address information and outputs it to the selection data bus 14. Control circuit 11
As shown in FIG. 5, a chip select C3, a read signal RD, a write signal WR, and a switching control signal S/D between address information and data information are output. Switching control signal S/D
The configuration is such that a high level selects an address and a low level selects data.

The output signals of the buzzer drive control circuit 17 and the interwoven signal generation circuit 19 can be changed by an external device, and these two circuits serve as signal synthesis means. The 2MH2 signal output from the frequency dividing circuit 3 is used as a clock signal for external equipment.

Figure 2 shows the counter 5 in Figure 1, which is 1/l.
It is a circuit diagram of O seconds digit. BCD decimal code 000
0 to 0101 are composed of D-type FFs 24 to 27, and gate 3
3, the code 0101 is latched into the master-only FF32, and gates 35 and 34 reset the FFs 24 to 27 to return the code to 0000. At this time, the set priority set reset FF made up of gates 36 to 39 is set to move up the line to the upper digit.

When modifying the counter, modify the address information ((
1, in which case the 1/10 second digit (code 0001) is sent via the address/data bus. The simultaneous J-coupling control signal S/D, chip select signal C8, and write signal WR are set to high level. Therefore, the latch signal 2A becomes high level and the latch circuit 9 holds 0001. This operation opens the gate 42, turns on the output buffers 728-31, and sends the contents of the counter (time data) to the switching circuit 1o via the read data bus (RB, -RB,).

Therefore, by next setting the read signal RD and the chip select signal C8 to high level, the time data can be called out from the address/data bus 15. When modifying the counter, the address data bus 15 is further supplied with modification data (for example, o.

When the switching control signal S/D is set to low level and the chip select signal C8 and write signal WR are set to high level, the signal W1 becomes high level and data is transferred to latch circuit 8.
to hold. Then gate 40.34 opens and FF24~
Reset 27. When the reset process is completed, the signal w2 becomes high level and the set signal (001O) from the write data bus is sent to the FFs 24 to 27 by the gates 20 to 23.
Set to . Therefore, the content of the 1/10 second digit is 2 (001
0).

As described above, correction and reading of the counter can be easily and quickly performed from outside.

FIG. 3 is a circuit diagram of the interwoven signal generating circuit 19 of FIG. 1. The address (1101) of 4 lines of interlaced (hereinafter referred to as INT) is sent from the address/data bus 15, and at the same time, control circuit control signals (S/D, C5, WR) are sent to the sum circuit 11 and held in the latch circuit. Then, the address/data bus 15 sends the INT signal selection data, and at the same time, the control circuit control signal (S/
D, C5, WR) are sent and the data is held in the latch circuit 8. The data held in the latch circuit 8 is sent to the latch circuit 43 via the write data bus l 3 (WB, -WB,). Next, the signal w2 is generated and the latch signal generated by the gate 48 causes the launch circuit 43 to hold the write data bus 13.

INT signal selection data is 500 when code is oooo
HZ, 0010 (71) hours 200H2,0100 hours 1
00H2,1000 50Hz (7) 4ff
fi XI is configured. For example, when INT signal selection data 0010 is sent, TG45 of transmission gates TG44 to TG47 is selected. Therefore, 200H2 is output as the INT signal. 2
The signal 00H2 is differentiated by a differentiating circuit comprising an FF 50 and a gate 51. During differentiation, it is preferable to do so during a relatively short pulse in which the INT signal ends while interwoven is being performed.

By changing the software of the external device, you can select the interlaced signal required by the external device.

In the example, the data consists of 4 bits, so the maximum is 16f! INT signals of the following types can be selected. It can also be configured to select the medium of differentiation using a similar consideration λ.

The INT signal output from the interlat generation circuit can be used for various purposes such as a reference signal for a timer of an external device, a key scan signal, etc.

FIG. 4 is a circuit diagram of the buzzer drive control circuit and buzzer drive circuit of FIG. 1. When the address information 1111 (tlUZ2) is sent from the address/data bus 15, the gate 52 opens in the same way (0th address/data bus 15
Similarly, when data information is sent, the latch circuit 54 holds the data on the write data bus 13 (WB, -WB,) by a latch signal generated from the gate 53. The output of the latch circuit 54 is connected to TGs 55-57.

When 0OIX (2nd bit is high), TG57 is on, when 0IOX (3rd bit is high), TG56 is on, and when 100X (4th bit is high), TG55 is on.
is turned on. The drive frequency (tone) of the buzzer can be changed by TG55-57. A write data bus (WBo) is connected to the gate 58, and its output is connected to the FF 59. This is XXX
When I (1st bit is high), the buzzer is turned on. When XXX0 (1st bit is low), the buzzer is off, and the Q output of FF59 is connected to gate 70 and TG5
Controls output signals 5 to 57.

As described above, when using the address information 1111, it is possible to select whether the buzzer is on or off and to select the buzzer drive frequency.

Address information 1110 from address data bus 15
When (BUZI) is sent, the gate 60 opens (
When data information is sent from the address/data bus 15 in the 0th order, the latch circuit 62 receives a latch signal generated from the gate 61 in the same manner as the write data bus l 3 (W
B, WB, ) data is held. The output of the latch circuit 62 is directly connected to TGs 63-66. 6 code 0
When 001 (1st bit high), TG63 is on, 00
TG64 is on when it is 1O, TG65 is on when it is 0100.
When it is on, 1000, TG66 is turned on. The outputs of TG63-66 are sent to shift registers 67-
69 clock signal, and is used as a clock signal for shift register 6
The Q output of 9 is connected to the reset terminal of FF59. The shift registers 67 to 69 are timers that determine the driving time of the buzzer.As described above, when the address information 1110 (BUZI) is used, the ON time of the buzzer can be selected.

FIG. 5 shows a timing chart of control circuit control signals. Address data bus A/D, chip select signal C8, disconnection control signal S/D, read signal RD, write signal WR1 signal W7, signal W1, latch signal 2A.

As described above, the present invention freely inputs and outputs time information to and from external equipment, thereby enabling a timekeeping function. Moreover, it has means for outputting a time signal obtained by time measurement to an external device, thereby reducing the burden on the external device and allowing the external device to change the output signal. It deepens the connection between external equipment and the timekeeping device, and is useful for multi-functionality with external equipment.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention. FIG. 2 is a circuit diagram of the counter shown in FIG. 1. FIG. 3 is a diagram of the interlat signal generation circuit shown in FIG. 1. FIG. 4 is a diagram of the buzzer drive control circuit and buzzer drive circuit of FIG. 1. FIG. 5 is a timing chart of the control circuit. that's all

Claims (1)

[Scope of Claims] 1. Frequency dividing means for dividing the frequency of a standard signal, a plurality of counters that time the divided signal from the frequency dividing means and having means for reading and writing time information, and reading each of the counters. and a data bus connected to the writing means, a counter selection means for selecting and connecting the counter to the data bus, a data input/output means for connecting the data bus and the counter selection means to an external device for data transmission and reception;
A timekeeping device comprising a signal synthesizing means for synthesizing an output from the frequency dividing means and an output signal from the counter and outputting the synthesized signal to the outside. 2. The timekeeping device according to claim 1, which is configured as an integrated circuit on a single substrate. 3. The timekeeping device according to claim 1, wherein the signal synthesis means comprises the data input/output means and a control means for controlling the data input/output means.