JPH02129729A - Data processor - Google Patents

Abstract

PURPOSE:To realize the detection of an abnormal state of a processor by a small number of hardwares by confirming whether response information is held in a holding means or not by a diagnostic processor through a diagnostic bus. CONSTITUTION:First holding means 41, 51 for holding response request information from a diagnostic processor 3 inputted through diagnostic buses 101 - 103, and second holding means 43, 53 for holding response information for showing a fact that a microprogram confirms a fact that the response request information is held in first holding means 41, 51 are provided on processors 4, 5. In this state, whether the response information is held in second holding means 43, 53 or not is confirmed by the diagnostic processor 3 through the diagnostic bus. In such a way, the performance of a system is not deteriorated, and even with respect to a processor which is not connected to the system buses 101 - 103, its normal operation is monitored, and the detection of an abnormal state of the processor is realized by a small number of hardwares.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data processing apparatus, and more particularly to a method for checking the normal operation of processors constituting a distributed processor system.

BACKGROUND ART In recent years, system configurations in which a plurality of processors are connected via a bus have become widespread, and in this system configuration, it is important for system operation that each processor is operating normally.

However, as the number of processors configuring a system increases, it has become difficult to monitor whether each processor is operating normally.

Conventionally, as a method for monitoring the normal operation of a processor as described above, a diagnostic processor checks whether a response from each processor to a response request message written to the main memory is written to the main memory. There is a way to do that.

That is, the diagnostic processor connected to each processor and the main memory via the system bus writes a response request message to the message communication area on the main memory using inter-processor communication.

Each processor accesses the message communication area on the main memory at regular intervals, and when it learns that there is a response request from the diagnostic processor, writes a response to this response request in the message communication area on the main memory.

By accessing the message communication area on the main memory, the diagnostic processor checks whether responses from each processor are written in the message communication area, and thereby checks whether each processor is operating normally. I was checking.

In such conventional data processing devices, each processor checks whether a response from each processor to a response request message written in the main memory is written in the main memory. Since the normal operation of the processor was monitored, the diagnostic processor utilized inter-processor communication via the system bus, which had the disadvantage that the diagnostic processor had to be located under the system bus.

Additionally, the system bus is used at regular intervals to monitor the normal operation of each processor.

This has the disadvantage that system performance deteriorates, and the normal operation of processors not connected to the system bus cannot be monitored, making control of the system bus complicated.

The present invention was made in order to eliminate the drawbacks of the conventional system as described above, and without degrading the performance of the system.
An object of the present invention is to provide a data processing device that can monitor the normal operation of a processor even if it is not connected to a system bus, and can detect an abnormal state of the processor using less hardware.

A data processing device according to the present invention is a data processing device in which a diagnostic processor and a processor controlled by a microprogram are connected by a diagnostic bus, and the diagnostic processor is connected to a processor controlled by a microprogram. a first holding unit that holds response request information from the processor; and a second holding unit that holds response information indicating that the microprogram has confirmed that the response request information is held in the first holding unit. A holding means is provided in the processor, and the diagnostic processor checks whether or not the response information is held in the second holding means via the diagnostic bus.

K1 Screen Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In FIG. 0, an input/output processor (IOP) 1 is a main memory! (MMU) 2 and a diagnostic processor (DGP) 3 via a system bus 100, respectively.

Further, the input/output processor 1 is connected to the diagnostic processor 3 via a diagnostic bus 101 and to each processor (PU) 4.5 via a local bus 104.

Each processor 4.5 has a respective diagnostic bus 102.103.
a request register (
RQ) 41.51 and response register (AK) 43.5
3 and microprogram control mechanism (MPC) 42.5
2 is provided.

This microprogram control mechanism 42.52 is connected to the input/output processor 1 via the local bus 104, receives the contents of the request register 41.51, and sets and resets the response register 43.53.

The request register 41.51 of each processor 4.5 is set by the diagnostic processor 3 via the diagnostic bus 1 (12, 103) and its contents are transferred to the microprogram controller m42.
52 to notify the microprogram that it has been set.

The diagnostic processor 3 uses diagnostic buses 102 and 10 to monitor whether each processor 4.5 is operating normally.
Set the request register 41.51 via 3. Thereafter, the response register 43 via the diagnostic buses 102 and 103
．． 53 is set.

In each processor 4.5 request register 41.51
When the request register 41.51 is set, the contents of the request register 41.51 are output to the microprogram control mechanism 42.52, and the microprogram is notified that the request register 41.51 has been set.

If each processor 4.5 is operating normally, response registers 43.53 are set by the microprogram.

The diagnostic processor 3 reads the contents of the response register 43.53 via the diagnostic bus 102.103, and the contents are “1”.
” by confirming that each processor 4.
5 is in normal operation.

If each processor 4.5 is in a stalled or stopped state, even if the request register 41.51 is set, the response register 43.53 will not be set by the microprogram, so the diagnostic processor 3 It is possible to know the abnormal state of each processor 4, 5.

The diagnostic processor 3 performs the above-mentioned processing so that each processor 4,
5 are sequentially checked for normal operation.

In the input/output processor 1, a request register (not shown) is set by the diagnostic processor 3 via the diagnostic bus 101, and a response register (not shown) is set in the input/output processor 1, similar to the normal operation check in each processor 4.5 described above. Normal operation is checked by the diagnostic processor 3 checking whether it is set or not.

In this way, the input/output processor 1 and each processor 4
．． Diagnostic buses 101 to 10 are stored in request registers provided in
A response request from the diagnostic processor 3 is set via the input/output processor 1 and the response register provided in each processor 4. By having the diagnostic processor 3 check via the diagnostic buses 101 to 103 whether the input/output processor 1 and each processor 4. Monitoring of the normal operation of the processor 1 and each processor 4.5 can be realized with less hardware.

Furthermore, since the diagnostic processor 3 monitors the normal operation of the input/output processor 1 and each processor 4 through 103 via the diagnostic buses 101 to 103, the diagnostic processor 3 does not need to be under the system bus 100 and can be connected to the diagnostic bus. If so, even the processors 4.5 not connected to the system bus 100 can be monitored for normal operation, and the processors to be checked can be expanded from the processors under the system bus 100 to all processors.

Furthermore, input/output processor 1 and each processor 4.5
Since the system bus 100 is not used to monitor the normal operation of the system, the performance of the system is not degraded by monitoring the normal operation, and the control of the system bus 100 is not complicated.

As explained above, according to the present invention, the first holding means holds the response request information from the diagnostic processor input via the diagnostic bus, and the first holding means holds the response request information. The processor is provided with a second idle means for retaining response information indicating that the microprogram has confirmed that the microprogram is retained, and the diagnostic bus determines whether or not the response information is retained in the second retainer. This allows the processor to monitor its normal operation even if it is not connected to the system bus, without degrading the performance of the system. This has the advantage that it can be realized with less hardware.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. Explanation of symbols of main parts 1... Input/output processor (IOP) 2...
...Main memory unit (MMU) 3...Diagnostic processor (DGP) 45...
...Processor (PU) 41.51 ...Request register (RQ) 42.5
2...Microprogram control mechanism (MPC) 43.53...Response register (AK) 101~
103・Old・Diagnosis bus

Claims (1)

[Claims] (1) A data processing device in which a diagnostic processor and a processor controlled by a microprogram are connected via a diagnostic bus, the data processing device holding response request information from the diagnostic processor input via the diagnostic bus. 1
and a second holding means for holding response information indicating that the microprogram has confirmed that the response request information is held in the first holding means. said second via the diagnostic bus.
A data processing apparatus characterized in that the diagnostic processor checks whether or not the response information is held in a holding means.