JPH0213466B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to the production of Pb alloy-based and Nb-based Josephson junction elements, and particularly to a method of producing a through-hole for junction.

[Background of the invention]

Conventional Josephson junction devices have a problem with the method of manufacturing through-holes for junctions, making it impossible to obtain a pattern with the design dimensions, resulting in large variations in current density between each junction, resulting in a reduction in the operating margin of logic, memory circuits, etc. It was the cause.

First, the manufacturing process of a conventional bonding through hole and its problems will be explained using figures.

FIGS. 1A and 1B are explanatory diagrams showing a process of manufacturing a through-hole for joining of a conventional Josephson junction element. In the figure, 11 is a substrate, and 12 is a resist tencil mask (hereinafter referred to as "resist tencil mask") having an overhang formed of AZ resist (trade name of Shipley Co., Ltd., USA).
13 is a SiO film (referred to as a lift-off mask).

As shown in FIG. 1a, the lift-off mask 12
A SiO film 13, which is an insulating film material, is deposited using
Patterns were created using lift-off treatment using a solvent.

However, the deposition particles of SiO are strongly scattered and adhere to the bottom and side walls of the overhang of the lift-off mask 12, and in the subsequent lift-off process, as shown in FIG. ) etc. remained, making it impossible to fabricate a through hole according to the design dimensions. For this reason, as described above, variations in current density between each junction have been a cause of a reduction in the operating margin of logic and memory circuits.

[Purpose of the invention]

An object of the present invention is to provide a method for manufacturing an element having a pattern of Josephson junction through-holes according to the designed dimensions without burrs or the like.

[Summary of the invention]

In order to realize this, the present invention has been studied by changing various insulating film materials. That is, In ₂ O ₃ ,
The targets were SnO ₂ , GeO, etc. As a result, it was found that GeO can be easily deposited using the resistance heating method, and that the scattering of the deposited particles is extremely low and there is no wraparound.

FIGS. 2a and 2b show an explanatory diagram of the fabrication of a through-hole for bonding according to the present invention.

In a, as in the conventional case, a lift-off mask 22 having an overhang part is prepared on a substrate 21, and a GeO film 2 is formed.
3 shows the cross-sectional shape after vapor deposition of No. 3.
Moreover, b shows the cross-sectional shape of the through-hole pattern after lift-off. As is clear from the figure, there are no burrs or the like, and the pattern is manufactured according to the designed dimensions.

Note that in the manufacturing process of Josephson junction elements, pattern formation and lift-off processes are repeatedly performed in various processes in addition to through-hole formation using photolithography technology. It is desirable that the lift-off masks produced in each process have overhangs, and the lift-off masks are used in various processes in the process of producing the Josephson junction device of the present invention.

The method for producing a lift-off mask having an overhang part is a known technique, and the details are, for example,
Described in IBM Tech Bull.19.4048 (1977).

Usually, a positive type AZ1350J (trade name, manufactured by Shipley, Inc., USA) resist is used. Lift-off masks are manufactured by forming an altered layer on the resist surface using a pattern exposure machine and chlorobenzene immersion treatment, and by making the surface of the exposed area particularly difficult to dissolve in the developer during development treatment, undercuts are caused. Form an overhang.

Examples will be described in detail below.

[Embodiments of the invention]

Example 1 Figures a to i are manufacturing process diagrams showing an example of the present invention, and figure i shows NbN, NbN, and
FIG. 2 is a cross-sectional view of the main part of a Josephson junction element using a Pb-In-Au alloy for the counter electrode. The main steps will be explained in accordance with the order a to i in the figure.

(a): The substrate is 50 mmφ, 400 μm thick, <100> Si
A substrate 31 is used, and a 200 nm interlayer insulating film of GeO 32 is deposited thereon. Next, the NbN film 33 that will become the base electrode is placed on top of this under a pressure of 5
The film was deposited to a thickness of 200 nm by direct current high speed sputtering in a 10% N ₂ -Ar mixed gas of mTorr.

(b): A resist mask for ion etching the NbN film 33 was prepared under the following conditions.
After applying AZ1350J resist to a thickness of 1 μm on the NbN film 33, pre-baking it at 70°C for 30 minutes, and then applying ultraviolet light (7 mw/
cm ² ) (360 to 450 nm) for 15 seconds, and then developed for 90 seconds using a developer with a composition of AZ developer solution (manufactured by Shipley, USA): water = 1:1 to form a resist pattern 34.
Formed. After this, post-baking was not performed in order to maintain the cross-sectional shape of the resist pattern 34.

(c): Insert the Si substrate 31 into a vacuum chamber, and then
After reducing the pressure to 10 ^-7 Torr, Ar pressure 1×
10 ^-4 Torr, acceleration voltage 600eV, ion current density
Ion etching was performed under the condition of 0.5 mA/cm ² . After etching, the substrate 31 was taken out from the vacuum chamber, unnecessary resist on the NbN film 33 was removed by plasma ashing using oxygen gas, and a base electrode 33 was formed.

(d): Next, a lift-off mask 35 for forming bonding through holes was manufactured under the following conditions. After applying AZ resist to a thickness of 1.2 μm on the base electrode 33 and interlayer insulating film 32, pre-baking at 70°C for 30 minutes, pattern exposure for 20 seconds at an illuminance of 7 mw/cm ² , and then applying chlorobenzene. A dipping treatment was performed for 10 minutes, and the same composition as in (b) was developed for 90 seconds.

(e): Ar spatter cleaning was performed again in the vacuum chamber. The conditions at this time are RF power 5W,
The Ar pressure was 3×10 ^-3 Torr, and the sputtering time was 5 minutes. GeO was deposited to a thickness of 270 nm using a resistance heating method.

(f): Lift-off was performed in acetone to form an interlayer insulating film 36 having bonding through holes.

(g): Next, a lift-off mask 37 for forming a counter electrode was produced under the following conditions. After applying AZ resist to a thickness of 1.5 μm on the interlayer insulating film 36,
℃, after pre-baking for 30 minutes, illuminance 7 mw/cm ²
Perform pattern exposure for seconds, then chlorobenzene immersion treatment for 10 minutes, and develop as described above.
It was formed using the same composition as (b) and (d) and developed for 90 seconds.

(h): Insert the Si substrate 31 into a vacuum chamber, reduce the vacuum level to 4×10 ^-7 Torr, and then apply Ar
Clean spatter. The conditions at this time are
The Ar pressure was 3×10 ^-3 Torr, the acceleration voltage was 800 V, and the sputtering time was 20 minutes. After this, once, 4×
After the pressure was reduced to 10 ⁻⁷ Torr, O ₂ gas was injected into the vacuum chamber to bring the pressure to 1 atm, and thermal oxidation treatment was performed at a substrate temperature of 40° C. and an oxidation time of 30 minutes to form a tunnel barrier 38. Next, after reducing the degree of vacuum in the vacuum chamber to 4×10 ⁻⁷ Torr, Pb, Au, and In were deposited in this order using a resistance heater to form a film with a thickness of 400 nm. As an example, the film thicknesses are 320 nm, 8 nm, and 72 nm, respectively. Note that the SiO film for the protective film was omitted in this process since there is no problem with corrosion.

(i): The lift-off mask 37 is attached to the base electrode 33.
The counter electrode 39 was formed by performing lift-off in Ascent in the same manner as in the fabrication of . Next, a lift-off mask (not shown) for forming a protective film was produced in the same manner as the lift-off mask for forming a counter electrode. The film thickness of the lift-off mask is
Thickness of the protective film 40 to be coated later (for example, 1 μm)
Since the film becomes thick, the film thickness was set to 1.5 μm to facilitate lift-off.
After inserting it into a vacuum chamber and performing Ar sputter cleaning, GeO was deposited to a thickness of 1 μm. Lift-off was performed in the same manner as for forming the counter electrode described above, and a protective film (SiO film) 40 was formed.

Through the above steps, the base electrode of the present invention
A Josephson junction device consisting of NbN and a Pb-In-Au alloy for the counter electrode was completed.

〔Effect of the invention〕

The Josephson junction device according to the present invention uses the insulating film material GeO as described in the embodiment, and as a result,
SEM (scanning electron microscopy) images revealed that the bonding dimensions were extremely faithful to the design dimensions, and a device with uniform bonding characteristics was confirmed.

The specific variation range of dimensions was ±3% with a diameter of 2.5 μm and 200 connections. By the way, in the conventional method, it is about ±11%.

In addition, it is clear that GeO is an extremely stable insulating film, with no damage caused by reactions (mutual diffusion) with Pb alloys or stress, etc., and with sufficient dielectric strength. It became.

Furthermore, it was also revealed that GeO is extremely chemically stable, without dissolving or leaking in solvents or aqueous solutions.

As described above, in the present invention, the insulating film is replaced with GeO from SiO, but the conventional process can be used as is for vapor deposition of GeO, and there is no particular problem.

Finally, the present invention can be applied to an all-Pb alloy process and also to a Nb alloy process.
When applied to a system process, we were able to obtain excellent results with excellent bonding properties.

[Brief explanation of drawings]

Figures 1a and b are explanatory diagrams of the manufacturing process of a through-hole for joining in a conventional Josephson junction element, Figures 2a and b are explanatory diagrams of the manufacturing process of a through-hole for junction according to the present invention, and Figures 3a to i are FIG. 2 is a process diagram showing an example of the present invention. 11, 21, 31...Substrate, 12, 22,...
Lift-off mask, 13... SiO film, 23...
GeO film, 32... Interlayer insulating film (SiO film), 33,
35, 37...lift-off mask, 34,...base electrode (NbN film), 36...interlayer insulating film for bonding (GeO film), 38...tunnel barrier layer, 39...
... Counter electrode (Pb-Au-In film), 40... Protective film (SiO film).

Claims (1)

[Claims] 1 (a) a step of forming a base electrode made of a superconducting thin film; (b) a step of forming a resist mask of a predetermined shape on the base electrode; (c) a step of forming a resist mask of a predetermined shape on the resist mask and the base electrode. To,
a step of forming a GeO film by vapor deposition; (d) a step of removing the GeO film on the resist mask together with the resist mask to form a through hole; (e) a step of forming a through hole in the exposed portion of the base electrode from the through hole. forming a tunnel barrier layer; and (f) covering at least the tunnel barrier layer;
1. A method for manufacturing a Josephson junction element, comprising the steps of: forming a counter electrode made of a superconducting thin film. 2 The step of forming the GeO film by vapor deposition is as follows:
2. The method of manufacturing a Josephson junction device according to claim 1, wherein the vapor deposition step is performed by a resistance heating method.